Microprocessor 8085

Chapter 1

Microprocessor:-The microprocessor is a semi programmable logic device that can

be used to control processes.it can also be used as a data processing device or a

computing unit of a computer.8085 is 8 bit microprocessor that can access 8 bits of

data and 16 bit address line used to fatch aproximately 64k memory location

internally.

Difference between microprocessor and microcontroller

Microprocessor is an IC which has only the CPU inside them i.e. only the

processing powers. These microprocessors don’t have RAM, ROM, and other

peripheral on the chip. A system designer has to add them externally to make them

functional. Application of microprocessor includes Desktop PC’s, Laptops,

notepads etc.

Microcontroller has a CPU, in addition with a fixed amount of RAM, ROM and

other peripherals all embedded on a single chip. At times it is also termed as a mini

computer or a computer on a single chip. Microcontrollers are designed to perform

specific tasks. Specific means applications where the relationship of input and

output is defined. Depending on the input, some processing needs to be done and

output is delivered. For example, keyboards, mouse, washing machine, remote,

microwave, cars, bikes, telephone, mobiles, watches, etc. Since the applications are

very specific, they need small resources like RAM, ROM, I/O ports etc and hence

can be embedded on a single chip.

Microprocessor find applications where tasks are unspecific like developing

software, games, websites, photo editing, creating documents etc. In such cases the

relationship between input and output is not defined. They need high amount of

resources like RAM, ROM, I/O ports etc.

The clock speed of the Microprocessor is quite high as compared to the

microcontroller. Whereas the microcontrollers operate from a few MHz to 30 to 50

MHz, today’s microprocessor operate above 1GHz as they perform complex task.

Chapter2

Block diagram of 8085 microprocessor:-

Description of block diagram:-

1. ALU:-The ALU performs the actual numerical and logic operation such as

‘add’, ‘subtract’, ‘AND’, ‘OR’ etc.It uses data from memory and from

Accumulator to perform arithmetic operation and always stores result of operation

in Accumulator. The ALU consists of accumulator, flag register and temporary

register.

a. Accumulator: The accumulator is an 8-bit register that is a part of

arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform

arithmetic and logical operations. The result of an operation is stored in the

accumulator.The accumulator is also identified as register A.

b. Flag registers:-8085 has 8-bit flag register. There are only 5 active flags. Flags

are flip-flops which are used to indicate the status of the accumulator and other

register after the completion of operations. These flip-flops are set or reset

according to the data condition of the results.

c. Timing and control unit:-This unit produces all the timing and control signal for

all the operation. This unit synchronizes all the MP operations with the clock and

generates the control signals necessary for communication between the MP and

peripherals.

3. Instruction register and decoder:-The instruction register and decoder are part of

ALU. When an instruction is fetched from memory, it is loaded in the instruction

register.The decoder decodes the instruction and establishes the sequence of events

to follow.

4. Register array:-The register unit of 8085 consists of Six general-purpose data

registers B, C,D,E,H. Two 16-bit address registers PC (program counter) and SP

(stack pointer),One increment/decrement counter register and one multiplexer

(MUX). The six general-purpose registers are used to store 8-bit data. They can be

combined as register pairs BC, DE, and HL to perform some 16-bit operations.

Stack Pointer:- SP is 16-bit registers used to point the address of data stored in the

stack memory. It always indicates the top of the stack.

Program Counter:- PC is 16-bit register used to point the address of the next

instruction to be fetched and executed stored in the memory.

5. System bus:-

a. Data bus:-It carries ‘data’, in binary form, between MP and other external

units, such as memory. Typical size is 8 or 16 bits.

b. Address bus:-It carries ‘address’ of operand in binary form. Typical size is 16-

bit.

c. Control Bus:-Control Bus are various lines which have specific functions for

coordinating and controlling MP operations.E.g.: Read/Write control line.

6. Interrupt Control:-

Interrupt is a signal, which suspends the routine what the MP is doing, brings the

control to perform the subroutine, completes it and returns to main routine.

E.g. INTR, TRAP, RST 7.5, RST 6.5, RST 5.5

7. Serial I/O Control :-The MP performs serial data input or output (one bit at a

time). In serial transmission, data bits are sent over a single line, one bit at a

time.The 8085 has two signals to implement the serial transmission: SID (serial

input data) and SOD (serial output data).

Pin diagram of 8085 MP:-

Discription of Pin diagram of 8085:-

Address bus:- A15-A8, it carries the most significant 8-bits of memory/IO address.

Data bus:-AD7-AD0, it carries the least significant 8-bit address and data bus.

Control and status signals:-

These signals are used to identify the nature of operation. There are 3 control

signal and 3 status signals.Three control signals are RD, WR & ALE.

RD − This signal indicates that the selected IO or memory device is to be

read and is ready for accepting data available on the data bus.

WR − This signal indicates that the data on the data bus is to be written into

a selected memory or IO location.

ALE − It is a positive going pulse generated when a new operation is started

by the microprocessor. When the pulse goes high, it indicates address.

When the pulse goes down it indicates data.

Three status signals are IO/M, S0 & S1.

IO/M (input/output or Memory):-

This signal is used to differentiate between IO and Memory operations, i.e. when

it is high indicates IO operation and when it is low then it indicates memory

operation.

S1 & S0

These are sort of control singles.These signals are used to identify the type of

current operation.

Power supply

There are 2 power supply signals − VCC & VSS. VCC indicates +5v power

supply and VSS indicates ground signal.

Clock signals

There are 3 clock signals, i.e. X1, X2, CLK OUT.

X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is

used to set frequency of the internal clock generator. This frequency is

internally divided by 2.8085 requires approximately 3.2MHz of frequency

whereas crystal generate 6.14MHz of frequency.

CLK OUT − This signal is used as the system clock for devices connected

with the microprocessor.

Interrupts & externally initiated signals

Interrupts are the signals generated by external devices to request the

microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST

7.5, RST 6.5, RST 5.5, and INTR. We will discuss interrupts in detail in interrupts

section.

INTA − It is an interrupt acknowledgment signal.

RESET IN − This signal is used to reset the microprocessor by setting the

program counter to zero.

RESET OUT − This signal is used to reset all the connected devices when

the microprocessor is reset.

READY − This signal indicates that the device is ready to send or receive

data. If READY is low, then the CPU has to wait for READY to go high.

HOLD − This signal indicates that another master is requesting the use of

the address and data buses.

HLDA (HOLD Acknowledge) − It indicates that the CPU has received the

HOLD request and it will relinquish the bus in the next clock cycle. HLDA

is set to low after the HOLD signal is removed.

Serial I/O signals

There are 2 serial signals, i.e. SID and SOD and these signals are used for serial

communication.

SOD (Serial output data line) − The output SOD is set/reset as specified by

the SIM instruction.

SID (Serial input data line) − The data on this line is loaded into

accumulator whenever a RIM instruction is executed.

Applications of microprocessor

o The microprocessor is used in personal computers (PCs).

o The microprocessor is used in LASER printers for good speed and making

automatic photo copies.

o The microprocessors are used in modems, telephone, digital telephone sets,

and also in air reservation systems and railway reservation systems.

o The microprocessor is used in medical instrument to measure temperature and

blood pressure.

o It is also used in mobile phones and television.

o It is used in calculators and game machine.

o It is used in accounting system and data acquisition system.

o It is used in military applications.

o It is also used in traffic light control.

o Microprocessor is used in home appliances such as microwave ovens, washing

machine etc.

Chapter 3

Instruction cycle in 8085 microprocessor :-

Time required to execute and fetch an entire instruction is called instruction cycle.

It consists:

Fetch cycle – The next instruction is fetched by the address stored in program

counter (PC) and then stored in the instruction register.

Decode instruction – Decoder interprets the encoded instruction from

instruction register.

Reading effective address – The address given in instruction is read from

main memory and required data is fetched. The effective address depends on

direct addressing mode or indirect addressing mode.

Execution cycle – consists memory read (MR), memory write (MW), input

output read (IOR) and input output write (IOW)

The time required by the microprocessor to complete an operation of accessing

memory or input/output devices is called machine cycle. One time period of

frequency of microprocessor is called t-state. A t-state is measured from the falling

edge of one clock .

Timing diagram for fetch cycle or opcode fetch:

Above diagram represents:

05 – lower bit of address where opcode is stored. Multiplexed address and

data bus AD0-AD7 are used.

20 – higher bit of address where opcode is stored. Multiplexed address and

data bus AD8-AD15 are used.

ALE – Provides signal for multiplexed address and data bus. If signal is high

or 1, multiplexed address and data bus will be used as address bus. To fetch

lower bit of address, signal is 1 so that multiplexed bus can act as address bus.

If signal is low or 0, multiplexed bus will be used as data bus. When lower bit

of address is fetched then it will act as data bus as the signal is low.

RD (low active) – If signal is high or 1, no data is read by microprocessor. If

signal is low or 0, data is read by microprocessor.

WR (low active) – If signal is high or 1, no data is written by microprocessor.

If signal is low or 0, data is written by microprocessor.

IO/M (low active) and S1, S0 – If signal is high or 1, operation is performing

on input output. If signal is low or 0, operation is performing on memory.

Chapter 4

Instruction Word Size:-

Three types of instruction are: 1-byte instruction, 2-byte instruction, and 3-byte

instruction.

1. One-byte instructions –In 1-byte instruction, the opcode and the operand of an

instruction are represented in one byte.

For example:- MOV B, A

Opcode- MOV

Operand- B, A

Hex Code- 47H

Binary code- 0100 0111.

2.Two byte Instructions:- Two-byte instruction is the type of instruction in which

the first 8 bits indicates the opcode and the next 8 bits indicates the operand. For

example:- MVI A, 32H Opcode- MVI ,Operand- A, 32H,Hex Code- 3E 32,Binary

code- 0011 1110,0011 0010

3. Three-byte instructions –

Three-byte instruction is the type of instruction in which the first 8 bits indicates

the opcode and the next two bytes specify the 16-bit address. The low-order

address is represented in second byte and the high-order address is represented in

the third byte.For example:- JMP 2085H,Opcode- JMP,Operand- 2085H,Hex

Code- C3,85 20,Binary code- 1100 0011,1000 0101,0010 0000

Addressing Modes in 8085:-

These are the instructions used to transfer the data from one register to another

register, from the memory to the register, and from the register to the memory

without any alteration in the content. Addressing modes in 8085 is classified into

5 groups −

Immediate addressing mode

In this mode, the 8/16-bit data is specified in the instruction itself as one of its

operand.

For example: MVI K, 20F: means 20F is copied into register K.

Register addressing mode

In this mode, the data is copied from one register to another.

For example:MOV K, B: means data in register B is copied to register K.

Direct addressing mode

In this mode, the data is directly copied from the given address to the register.

For example: LDB 5000K: means the data at address 5000K is copied to register

B.

Indirect addressing mode

In this mode, the data is transferred from one register to another by using the

address pointed by the register.

For example: MOV K, B: means data is transferred from the memory address

pointed by the register to the register K.

Implied addressing mode

This mode doesn’t require any operand; the data is specified by the opcode

itself. For example: CMP.

Instruction Set of Intel 8085 microprocessor

Data Transfer Group:

This group of instructions transfers data to and from registers and memory.

Condition flags are not affected by any instruction in this group.

Move Register : MOV 1 2,r r 1 2r r

The content of register 2r is moved to register 1r .These are single byte

instructioThis machine instruction indicates

MOV A, B

i.e. the contents of register B will be moved to accumulator A.

The op-code of this machine instruction in hexadecimal is 7 8.and this is a single

byte instruction

MOV r, M (Move from memory)

r H L

The content of the memory location, whose address is in registers H and L, is

moved to register r.Example:

Assume that the contents of H is 10H and L is 00 H . Then the instruction

Moves the contents of memory location 1000H to accumulator. The op-code of this

machine instruction in hexadecimal is 7E

MVI r, data (Move immediate)

byte 2r

It is a 2-byte instruction, the content of the byte 2 of the instruction is moved to

register r.

Example

0 1 1 1 1 1 1 0

0 0 D D D 1 1 0

data

0 0 0 0 0 1 1 0

0 0 1 1 0 0 1 1

The data 0 0 1 1 0 0 1 1 i.e 33H will be moved to register B.

The machine instruction in hexadecimal is

06 33H H

MVI M, data (Move to memory immediate)

byte2H L

The content of byte 2 of the instruction is moved to the memory location whose

address is in register H and L .

L I rp , data 16 (Load register pair immediate)

byte3

byte 2

rh

rl

Byte 3 of the instruction is moved in to the higher order register rh of the register

pair rp . Byte 2 of the instruction is moved into the low-order register rl of the

register pair rp .

0 0 1 1 0 1 1 0

data

The bit pattern in RP designating one of the register pairs B, D, H & SP :

RP Register-Pair

0 0 B-C

0 1 D-E

1 0 H-L

1 1 SP

For example:

This instruction loads the register pair H-L by 1000H .

The machine instruction in hexadecimal format is

0 0 R P 0 0 0 1

low-order data

high-order data

0 0 1 0 0 0 0 1

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0

21 00 10H H H

LDA addr (Load accumulator direct)

A((byte 3) (byte 2))

The contents of the memory location, whose address is specified in byte 2 and byte

3 of the instruction, is moved to register A. It is a three byte instruction.

The instruction 3 00 20H H HA moves the contents of memory location 2000H to

accumulator.

STA addr (store accumulator direct)

((byte-3) (byte-2)) A

The content of the accumulator is moved to the memory location whose address is

specified in byte 2 and byte 3 of the instruction.

0 0 11 1 0 1 0

low-order Adress

high-order Address

The instruction 32 10 20H H H moves the contents of accumulator into memory

location 2010H

LHLD addr (Load H and L direct)

(L) ((byte 3)(byte 2)

(H) ((byte 3)(byte 2) +1)

The contents of the memory location, whose address is specified in byte 2 and byte

3 of the instruction, is moved to register L. The content of the next memory

location is moved to register H.

SHLD addr (store H and L direct)

0 0 11 0 0 1 0

low-order Adress

high-order Address

0 0 1 01 0 1 0

low-order Adress

high-order Address

((byte 3) (byte 2)) (L)

((byte 3) (byte 2) +1) (H)

The content of register L is moved to the memory location whose address is

specified in byte 2 and byte 3. The content of register H is moved to the next

memory location.

For example:

22 00 10H H H

This instruction moves the content of register L to the memory location 1000H and

moves the content of register H to the memory location 1001H

LDA ((rp))

The content of memory location, whose address is in the register pair rp, is moved

to accumulator.

0 0 1 0 0 0 1 0

low-order Adress

high-order Address

rp A

The content of register A is moved to the memory location whose address is in the

register pair rp

XCHG (Exchange H and L with D and E)

H D

L E

The contents of register H and L are exchanged with the contents of register D and

E.

Arithmetic Group:This group of instructions performs arithmetic operations on

data in registers and memory.Most of the instructions in this group affect the flag

bits according to the standard rules.All subtraction operations are performed via

2’s complement arithmetic and set the carry flag to one to indicates a borrow and

clear it to indicate no borrow.

ADD r (Add Register)

A A r

The content of register r is added to the content of the accumulator. The result is

placed in the accumulator.

e.g.

0 0 R P 0 0 1 0

1 0 0 0 0 S S S

1 0 0 0 0 0 0 1 indicates the operation A A C ADDC because the binary

coding for register C is 001. The op-code for ADD C in hexadecimal is 81H .

The content of accumulator is added to the content of register C, and the result is

stored in accumulator.Depending on the result of the operation, the flags bits are

set or reset.If the result of the operation is zero, then the Z flag is set to 1.

Generally it will follow the standard rule to set the flags.

The other operation in arithmetic group is listed below..

Addition group

Operation Operation

Performed

OP code Flags affected

ADD r

(Add register)

A A r 1 0 0 0 0 S S S Z, S, P, CY, AC

ADD M

(Add memory)

A A H L 1 0 0 0 0 1 1 0 Z, S, P, CY, AC

ADI data

(Add

Immediate)

byte2A A 1 1 0 0 0 1 1 0

(data)

Z, S, P, CY, AC

ADC r

(Add register

with carry

A A r CY 1 0 0 0 1 S S S Z, S, P, CY, AC

AMC M

(Add memory

A A H L CY 1 0 0 0 1 1 1 0 Z, S, P, CY, AC

with carry

ACI data

(Add Immediate

with carry)

byte2A A CY 1 1 0 0 1 1 1 0

(data)

Z, S, P, CY, AC

Subtraction group

Operation Operation

Performed

OP code Flags affected

SUB r

(Subtract

Register)

A A r 1 0 0 10 S S

S Z, S, P, CY,

AC

SUB M

(Subtract

Memory)

A A H L 1 0 0 1 0 1 1

0

Z, S, P, CY, AC

SUI data

(Subtract

Immediate)

byte2A A 1 1 0 1 0 1 1

0

(data)

Z, S, P, CY, AC

SBB r

(Subtract

Register with

borrow)

A A r CY 1 0 0 1 0 S S

S

Z, S, P, CY, AC

SBB M

(Subtract

Memory with

borrow)

A A H L CY

1 0 0 1 1 1 1

0

Z, S, P, CY, AC

Logical Instruction Set:-

This group of instructions perform logical (Boolean) operations on data in registers

and memory and on condition flags.All instructions in this group affect the Zero,

Sign, Parity, Auxiliary carry and carry flags according to the standard rules.

Operation Operation

Performed

Op-code

ANA r

(AND Register)

A A r 1 0 1 0 0 S S S

ANA M

(AND memory)

A A H L 1 0 1 0 0 1 1 D

ANI data

(AND immediate)

byte2A A 1 1 1 0 0 1 1 0

(data)

XRA r

(Exclusive OR

Register)

A A r 1 0 1 0 1 S S S

XRA M

(Exclusive OR

memory)

A A H L 1 0 1 0 1 1 1 0

XRI data

(Exclusive OR

immediate)

byte 2A A 1 1 1 0 1 1 1 0

(data)

ORA r

(OR Register)

A A r 1 0 1 1 0 S S S

ORA M

(OR memory)

A A H L 1 0 1 1 0 1 1 0

ORI data

(OR immediate)

byte2A A 1 1 1 1 0 1 1 0

CMP r

(Compare register)

A r

the accumulator remains

unchanged.

Z flag is set to 0 if A r

CY flag is set to 1 if A r

1 0 1 1 1 S S S

CMP M

(Compare memory)

A H L 1 0 1 1 1 1 1 0

CPI data

(Compare immediate)

byte2A 1 1 1 1 1 1 1 0

data

RLC

(Rotate left)

1 0 7

7

,n nA A A A

CY A

0 0 0 0 0 1 1 1

RRC

(Rotate right)

1 7 0

0

,n nA A A A

CY A

0 0 0 0 1 1 1 1

RAL

(Rotate left through

carry)

1 7

0

,n nA A CY A

A CY

0 0 0 1 0 1 1 1

RAR

(Rotate right through

carry)

1 0

7

,n nA A CY A

A CY

0 0 0 1 1 1 1 1

CMA

(Complement

accumulator)

A A 0 0 1 0 1 1 1 1

CMC CY CY 0 0 1 1 1 1 1 1

(complement carry)

STC

(Set carry)

1CY 0 0 1 1 0 1 1 1

Flag Register or Status Registers:-

The Flag register is a Special Purpose Register. Depending upon the value of result

after any arithmetic and logical operation the flag bits become set (1) or reset (0).

In 8085 microprocessor, flag register consists of 8 bits and only 5 of them are

useful.

The 5 flags are:

1. Sign Flag (S) – After any operation if the MSB (B(7)) of the result is 1, it

indicates the number is negative and the sign flag becomes set, i.e. 1. If the

MSB is 0, it indicates the number is positive and the sign flag becomes reset.

2. Zero Flag (Z) – After any arithmetical or logical operation if the result is 0

(00) H, the zero flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.

3. Auxiliary Carry Flag (AC) – This flag is used in BCD number system(0-9). If

after any arithmetic or logical operation D(3) generates any carry and passes on to

B(4) this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.

4. Parity Flag (P) – If after any arithmetic or logical operation the result has even

parity, an even number of 1 bits, the parity register becomes set i.e. 1, otherwise it

becomes reset i.e. 0.

5. Carry Flag (CY) – Carry is generated when performing n bit operations and

the result is more than n bits, then this flag becomes set i.e. 1,or it is reset i.e. 0.

Chapter 5 Memory interfacing:-Memory is a very Important part of microprocessor system.

During the instruction memory need to be operated many times.there is a

interfacing ckt. The interfacing ckt. will match the requirements of memory with

microprocessor so that data and instruction can be read from the memory or written

into the memory.ti read or to write data into memory by the microprocessor

,following operation has to be performed.

To select the required memory chip

To identify the required register of memory

To enable the required input and output buffer

Memory mapped I/O and I/O mapped I/O schemes:-The 8085 has a 16 bit of

address bus.while addressing memories ,it places 16 bit address of the memory

location on the address bus.IO/M signal is held low to operated with memory and

high while oprated with input output devices.

Memory mapped I/O :-In this scheme the 8085 treats the I/O device as memory

location The device adddress is of 16 bits and occupy a space in memory.No

memory location has the same address which is assigned to I/O device.The

instruction MOV,LDA,STA,LDAX are used to transfer data between device and

8085.The I/O device respond to the read or write signal only when control signal is

low and memory read or memory write signal are used.

I/O mapped I/O scheme:-In this scheme ,the device is connected to the 8085 as an

I/O device. While accessing the device the microprocessor place the 8 bit address

on address bus. In this mod 256 I/O devices can be connected to the 8085.the I/O

devices responds to the read or write signal only when control signal is high.IOR

and IOW signal are used to read and writ operation of the I/O devices.

Chapter 6 Interrupts:-

Interrupts in 8085 :-

An interrupt is a process between an external device and the microprocessor for

transfer of data. Interrupts are the signals generated by the external devices to

request the microprocessor to perform a task. There are 5 interrupt signals, i.e.

TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

Interrupt are classified into following groups based on their parameter −

Vector interrupt − In this type of interrupt, the interrupt address is known

to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP.

Non-Vector interrupt − In this type of interrupt, the interrupt address is not

known to the processor so, the interrupt address needs to be sent externally

by the device to perform interrupts. For example: INTR.

Maskable interrupt − In this type of interrupt, we can disable the interrupt

by writing some instructions into the program. For example:RST7.5,

RST6.5, RST5.5.

Non-Maskable interrupt − In this type of interrupt, we cannot disable the

interrupt by writing some instructions into the program. For

example: TRAP.

Software interrupt − In this type of interrupt, the programmer has to add

the instructions into the program to execute the interrupt. There are 8

software interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5,

RST6, and RST7.

Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware

interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.

Interrupt Service Routine (ISR)

A small program or a routine that when executed, services the corresponding

interrupting source is called an ISR.

TRAP :-It is a non-maskable interrupt, having the highest priority among all

interrupts. By default, it is enabled until it gets acknowledged. In case of failure, it

executes as ISR and sends the data to backup memory. This interrupt transfers the

control to the location 0024H.

RST7.5 It is a maskable interrupt, having the second highest priority among all

interrupts. When this interrupt is executed, the processor saves the content of the

PC register into the stack and branches to 003CH address.

RST 6.5-It is a maskable interrupt, having the third highest priority among all

interrupts. When this interrupt is executed, the processor saves the content of the

PC register into the stack and branches to 0034H address.

RST 5.5-It is a maskable interrupt. When this interrupt is executed, the processor

saves the content of the PC register into the stack and branches to 002CH address.

INTR-It is a maskable interrupt, having the lowest priority among all interrupts. It

can be disabled by resetting the microprocessor.

When INTR signal goes high, the following events can occur −

The microprocessor checks the status of INTR signal during the execution

of each instruction.

When the INTR signal is high, then the microprocessor completes its

current instruction and sends active low interrupt acknowledge signal.

When instructions are received, then the microprocessor saves the address

of the next instruction on stack and executes the received instruction.

Chapter 7 Data Transfer Techniques

The MP transmits/Receives data in 2 modes :

* parallel IO mode

* Serial IO mode •

8085 MP is a Parallel Device, since it transfers 8 bits of data at a time over 8

data lines. • In many situation parallel IO mode is either Impossible Eg: CRT

terminal, That parallel data communication is not possible. • These device

need serial IO mode is used which transfer a single bi on a single line at a

time. • That’s why there is parallel to serial conversion or serial to parallel

conversion.

Programmed I/O Data transfer:-

Synchronous Data Transfer: -• • Synchronous means “at the same time” . In

this format of data transfer transmitter and receiver device are synchronized

with the same clock pulse. • This type of data transfer format is used in

between the devices that match in speed. This method is invariably used in

between memory and microprocessor as they are compatible.

Disadvantage: Its not suitable when speed of character is not known. start

Execute I/O instruction stop.

Asynchronous Data Transfer: - • Asynchronous means “at a regular interval”.

In this method data transfer is not based on predetermined timing pattern in

this technique the status of the IO device is checked by the microprocessor

before the data is transferred. This method is invariably used in between

microprocessor and IO devices. Its used when the speed of the IO devices is

slower than the speed of the MP(MISMATCH) Its asynchronous to each

other. Its also called as “HANDSHAKING” mode. Handshaking Mode MP IO

Device Data Bus Ready ACK Advantage: can be used even when the speed

character is not known.

Disadvantages: It keeps checking the looping and the processor time is

wasted by just waiting and checking

Interrupt driven data transfer. Data transfer scheme the IO device informs the

MP for the data transfer whenever the IO device is ready. This is achieved by

Interrupting the MP. MP IO device Data bus INTR ACK INTR REQUEST

start Send ready signal to IO device Fetch & exe next instr Is the interrupt

High? Save pc to stack & exe ISS Start ISS Push status of the processor to

stack Exe IO instru Restore status of the processor Return to main program

NO Yes Single Interrupt system • When only one interrupt line is available

with the MP and several IO devices are to be connected.

DMA(Direct Memory Access):-Direct memory access (DMA) is a method that

allows an input/output (I/O) device to send or receive data directly to or from the

main memory, bypassing the CPU to speed up memory operations. The process is

managed by a chip known as a DMA controller (DMAC). So now come to

working principle of direct memory access data transfer. For the data transfer using

DMA process, a request to the microprocessor in form of HOLD signal, by the I/O

device is sent. When microprocessor receipt of such request, the microprocessor

relinquishes the address and data buses and informs the I/O devices of the situation

by sending Acknowledge signal HLDA. The I/O device withdraws the request

when the data transfer between the I/O device and external memory is complete.

If we discuss in brief about working principal of DMA controller. Then we should

mention that DMA controller is used with the microprocessor that helps to

generate the addresses for the data to be transferred from the I/O devices. The

peripheral device sends the request signal (DMARQ) to the DMA controller and

the DMA controller in turn passes it to the microprocessor (HOLD signal). On

receipt of the DMA request the microprocessor sends an acknowledge signal

(HLDA) to the DMA controller. On receipt of this signal (HLDA) the DMA

controller sends a DMA acknowledge signal (DMACK) to the I/O device. The

DMA controller then takes over the control of the buses of microprocessor and

controls the data transfer between RAM and I/O device. When the data transfer is

complete, DMA controller returns the control over the buses to the microprocessor

by disabling the HOLD and DMACK signals.

(a) Burst Mode DMA :-Entire block of data is transferred in one continuous

sequence. Once the DMA controller is granted access to the system bus by CPU, it

transfer all bytes of data in the data block before relinquishing control of system

buses back to the CPU. This mode is useful for loading programs or data files into

memory, but it keeps CPU idle for relatively long period of time.

(b) Cycle Stealing DMA :-DMA controller obtains access to system bus as in burst

mode; transfers one byte of data and returns the control of the system bus to CPU.

It continually issues requests using Bus Request (BR) signals, transferring one byte

of data per request, until it has transferred its entire block of data. (steals one CPU

cycle).The data block is not transferred as quickly as in burst mode, but the CPU is

not idled for long period of time as in burst mode.

Handshaking:- Handshaking is a I/O control method to synchronize I/O device

with the microprocessor. As many I/O devices accepts or release information at a

much slower rate than the microprocessor, this method is used to control the

microprocessor to work with a I/O device at the I/O devices data transfer rate.The

signal which exchanges in between MP and other devices prior to actual

transmission of data is called handshakes signals.

Chapter 8

Peripheral Devices :-A peripheral device provides input/output (I/O) functions for

a computer and serves as an auxiliary computer device without computing-

intensive functionality. Peripheral devices connect with a computer through several

I/O interfaces, such as communications (COM), Universal Serial Bus (USB) and

serial ports.

8255 PPI (Programmed peripheral interface)

PPI 8255 is a general purpose programmable I/O device designed to interface the

CPU with its outside world such as ADC, DAC, keyboard etc. We can program it

according to the given condition. It can be used with almost any microprocessor.

It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT

C. We can assign different ports as input or output functions.

Block diagram of 8255

Pin Diagram of 8255

Description of 8255:- It consists of 40 pins and operates in +5V regulated power

supply. Port C is further divided into two 4-bit ports i.e. port C lower and port C

upper and port C can work in either BSR (bit set rest) mode or in mode 0 of input-

output mode of 8255. Port B can work in either mode or in mode 1 of input-output

mode. Port A can work either in mode 0, mode 1 or mode 2 of input-output mode.

It has two control groups, control group A and control group B. Control group A

consist of port A and port C upper. Control group B consists of port C lower and

port B.

Depending upon the value if CS’, A1 and A0 we can select different ports in

different modes as input-output function or BSR. This is done by writing a suitable

word in control register (control word D0-D7).

PA0 – PA7 – Pins of port A

PB0 – PB7 – Pins of port B

PC0 – PC7 – Pins of port C

D0 – D7 – Data pins for the transfer of data

RESET – Reset input

RD’ – Read input

WR’ – Write input

CS’ – Chip select

A1 and A0 – Address pins

Configuration of different ports

CS’ A1 A0 SELECTION ADDRESS

0 0 0 PORT A 80 H

0 0 1 PORT B 81 H

0 1 0 PORT C 82 H

0 1 1

Control

Register 83 H

1 X X

No

Seletion X

Different Operating modes of 8255:-

1. Bit set reset (BSR) mode – If MSB of control word (D7) is 0, PPI

works in BSR mode. In this mode only port

C bits are used for set or reset.

1. Input-Output mode –

If MSB of control word (D7) is 1, PPI works in input-output mode. This is

further divided into three modes:

Mode 0 –In this mode all the three ports (port A, B, C) can work as simple

input function or simple output function. In this mode there is no interrupt

handling capacity.

Mode 1 – Handshake I/O mode or strobbed I/O mode. In this mode either port

A or port B can work as simple input port or simple output port, and port C

bits are used for handshake signals before actual data transmission. It has

interrupt handling capacity and input and output are latched.

Example: A CPU wants to transfer data to a printer. In this case since speed of

processor is very fast as compared to relatively slow printer, so before actual

data transfer it will send handshake signals to the printer for synchronization

of the speed of the CPU and the peripherals.

Mode 2 – Bi-directional data bus mode. In this mode only port A works, and

port B can work either in mode 0 or mode 1. 6 bits port C are used as

handshake signals. It also has interrupt handling capacity.

DMA Controller 8257

Block diagram of DMAcontroller

Pin Diagram of 8257

DRQ0−DRQ3:-As seen in the above diagram these are the four individual

asynchronous channel DMA request inputs, which are used by the peripheral

devices to obtain DMA services. When the rotating priority mode is selected, then

DRQ0 will get the highest priority and DRQ3 will get the lowest priority among

them.

DACKo − DACK3:-These are the active-low and high (inactive) DMA

acknowledge lines, which updates the peripheral requesting device service about

the status of their request by the CPU. These lines can also act as strobe lines for

the requesting devices.

Do − D7:-These are bidirectional, data lines which help to interface the system bus

with the internal data bus of DMA controller. In the Slave mode, command words

are carried to 8257 and status words from 8257. In the master mode, the lines

which are used to send higher byte of the generated address are sent to the latch.

This address is further latched using ADSTB signal.

IOR:-It is an active-low bidirectional tri-state input line, which helps to read the

internal registers of 8257 by the CPU in the Slave mode. In the master mode, it

also helps in reading the data from the peripheral devices during a memory write

cycle.

IOW:-It is an active low bi-direction tri-state line, which helps in loading the

contents of the data bus to the 8-bit mode register or upper/lower byte of a 16-bit

DMA address register or terminal count register. In the master mode, it is used to

load the data to the peripheral devices during DMA memory read cycle.

CLK:-It is a clock frequency signal which is required to perform internal operation

of 8257.

RESET:-This signal is used to RESET the DMA controller by disabling all the

DMA channels.

Ao - A3:-These are the four least significant address lines. In the slave mode, they

perform as an input, which selects one of the registers to be read or written. In the

master mode, they are the outputs which contain four least significant memory

address output lines produced by 8257.

CS:-It is an active-low chip select line. In the Slave mode, it enables the read/write

operations to/from 8257. In the master mode, it automatically disables the

read/write operations to/from 8257.

A4 - A7:-These are the higher nibble of the lower byte address generated by DMA

in the master mode.

READY:-It is an active-high asynchronous input signal, which helps DMA to

make ready by inserting wait states.

HRQ:-This signal helps to receive the hold request signal sent from the output

device. In the slave mode, it is connected with a DRQ input line 8257. In Master

mode, it is connected with HOLD input of the CPU.

HLDA:-It is the hold acknowledgement signal which indicates the DMA controller

that the bus has been granted to the requesting peripheral by the CPU when it is set

to 1.

MEMR:-It is the low memory read signal, which is used to read the data from the

addressed memory locations during DMA read cycles.

MEMW:-It is the active-low three state signal which is used to write the data to the

addressed memory location during DMA write operation.

ADST:-This signal is used to convert the higher byte of the memory address

generated by the DMA controller into the latches.

AEN:-This signal is used to disable the address bus/data bus.

TC:-It stands for ‘Terminal Count’, which indicates the present DMA cycle to the

present peripheral devices.

MARK-The mark will be activated after each 128 cycles or integral multiples of it

from the beginning. It indicates the current DMA cycle is the 128th cycle since the

previous MARK output to the selected peripheral device.

Vcc-It is the power signal which is required for the operation of the circuit.

Programmed interval timer(8253):- The Intel 8253 and 8254 are Programmable

Interval Timers (PTIs) designed for microprocessors to perform timing and

counting functions using three 16-bit registers. Each counter has 2 input pins, i.e.

Clock & Gate, and 1 pin for “OUT” output. To operate a counter, a 16-bit count is

loaded in its register. On command, it begins to decrement the count until it

reaches 0, then it generates a pulse that can be used to interrupt the CPU.

Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10

MHz

It uses N-MOS technology It uses H-MOS technology

Read-Back command is not available Read-Back command is available

Reads and writes of the same counter

cannot be interleaved.

Reads and writes of the same counter

can be interleaved.

Features of 8253 / 54

It has three independent 16-bit down counters.

It can handle inputs from DC to 10 MHz.

These three counters can be programmed for either binary or BCD count.

It is compatible with almost all microprocessors.

8254 has a powerful command called READ BACK command, which

allows the user to check the count value, the programmed mode, the current

mode, and the current status of the counter.

Architecture of 8253

8253 Pin Description

In the above figure, there are three counters, a data bus buffer, Read/Write

control logic, and a control register. Each counter has two input signals -

CLOCK & GATE, and one output signal - OUT.

Data Bus Buffer

It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54

to the system data bus. It has three basic functions −

Programming the modes of 8253/54.

Loading the count registers.

Reading the count values.

Read/Write Logic

It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the

peripheral I/O mode, the RD and WR signals are connected to IOR and IOW,

respectively. In the memory mapped I/O mode, these are connected to MEMR and

MEMW.

Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the

8253/54, and CS is tied to a decoded address. The control word register and

counters are selected according to the signals on lines A0 & A1.

A1 A0 Result

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

X X No Selection

Control Word Register

This register is accessed when lines A0 & A1 are at logic 1. It is used to write a

command word, which specifies the counter to be used, its mode, and either a read

or write operation. Following table shows the result for various control inputs.

A1 A0 RD WR CS Result

0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1

1 0 0 1 0 Read Counter 2

1 1 0 1 0 No operation

X X 1 1 0 No operation

X X X X 1 No operation

Counters

Each counter consists of a single, 16 bit-down counter, which can be operated in

either binary or BCD. Its input and output is configured by the selection of modes

stored in the control word register. The programmer can read the contents of any

of the three counters without disturbing the actual count in process.

Programmed interrupt Controller(PIC) 8259 :-8259 microprocessor is defined

as Programmable Interrupt Controller (PIC)microprocessor. There are 5

hardware interrupts and 2 hardware interrupts in 8085 and 8086 respectively. But

by connecting 8259 with CPU, we can increase the interrupt handling capability.

8259 combines the multi interrupt input sources into a single interrupt output.

Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7.For example,

Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085

microprocessor from 5 to 8 interrupt levels.

Features of 8259

1. It can be programmed either in level triggered or in edge triggered interrupt

level.

2.We can masked individual bits of interrupt request register.

3.We can increase interrupt handling capability upto 64 interrupt level by

cascading further 8259 PIC.

4.Clock cycle is not required

Pin Diagram of 8259 –

Block Diagram of 8259 PIC microprocessor –

The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write

Logic, Cascade Buffer Comparator, Control Logic, Priority Resolver and 3

registers- ISR, IRR, IMR.

1. Data bus buffer – This Block is used as a mediator between 8259 and 8085/8086 microprocessor

by acting as a buffer. It takes the control word from the 8085 (let say)

microprocessor and transfer it to the control logic of 8259 microprocessor.

Also, after selection of Interrupt by 8259 microprocessor, it transfer the

opcode of the selected Interrupt and address of the Interrupt service sub

routine to the other connected microprocessor. The data bus buffer consists of

8 bits represented as D0-D7 in the block diagram. Thus, shows that a

maximum of 8 bits data can be transferred at a time.

2. Read/Write logic – This block works only when the value of pin CS is low (as this pin is active

low). This block is responsible for the flow of data depending upon the inputs

of RD and WR. These two pins are active low pins used for read and write

operations.

3. Control logic – It is the centre of the microprocessor and controls the functioning of every

block. It has pin INTR which is connected with other microprocessor for

taking interrupt request and pin INT for giving the output. If 8259 is enabled,

and the other microprocessor Interrupt flag is high then this causes the value

of the output INT pin high and in this way 8259 responds to the request made

by other microprocessor.

4. Interrupt request register (IRR) – It stores all the interrupt level which are requesting for Interrupt services.

5. Interrupt service register (ISR) – It stores the interrupt level which are currently being executed.

6. Interrupt mask register (IMR) – It stores the interrupt level which have to be masked by storing the masking

bits of the interrupt level.

7. Priority resolver –

It examines all the three registers and set the priority of interrupts and

according to the priority of the interrupts, interrupt with highest priority is set

in ISR register. Also, it reset the interrupt level which is already been serviced

in IRR.

8. Cascade buffer – To increase the Interrupt handling capability, we can further cascade more

number of pins by using cascade buffer. So, during increment of interrupt

capability, CSA lines are used to control multiple interrupt structure.SP/EN

(Slave program/Enable buffer) pin is when set to high, works in master mode

else in slave mode. In Non Buffered mode, SP/EN pin is used to specify

whether 8259 work as master or slave and in Buffered mode, SP/EN pin is

used as an output to enable data bus.