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  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Chapter 10

    Memory Interface

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Objectives Describe various memory types Describe memory pin connections Use decoders and PLDs (programmable logic

    devices) to decode memory addresses Explain how to interface RAM and ROM to a

    microprocessor Interface dynamic RAM to the microprocessor Explain operation of dynamic RAM controller Interface memory to all Intel microprocessors using

    8-, 16-, 32-, and 64-bit data buses

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Types of Memory DevicesTwo main types of memory:

    ROM - Read Only Memory - Non Volatile data storage (remains valid after power off)- For permanent storage of system software and data- Can be PROM, EPROM or EEPROM (Flash) memory

    RAM - Random Access Memory (a misnomer - better Read/Write)- Volatile data storage (data disappears after power off)- For temporary storage of application software and data- Can be SRAM (static) or DRAM (dynamic)

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Address Inputs:- Select the required location in memory. - Address lines are numbered from A0 to as many as required to address all memory locationse.g. 12-bit address: A0-A11 212 = 4K memory locations- Todays memory devices have capacities upto around 1G locations (30 address lines)- Example: 4K memory: 12 bits: 000H-FFFH. e.g. from 301000H to 301FFFH on an 80286 system

    Memory Pin Connections Address Data Control

    Chip Select

    OutputEnable

    OutputEnable

    Chip Select

    WriteEnable

    M

    -Select chip-Specify whether you want a READ or WRITE operation

    ROMs have no WE control

    Decodethis part for CS

    Only forRAM

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Data Inputs/Outputs (RAM)Data Outputs (ROM)- Number of lines = width of data storage, usually a byte D0-D7 (M=7)- Processor with wider data buses use multiple of such byte-wide memory devices, e.g. 64-bit 8 x 8-bit devices- Sometimes the total memory capacity is expressed in bits, e.g. a 64K x 8-bit = 512 Kbit

    Memory Pin Connections Address Data Control

    OutputEnable

    Chip Select

    WriteEnable

    M

    Only forRAM

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Control Inputs- Chip Enable (#CE), or Chip Select (#CS), or simply Select (#S). Select the memory device for READ or WRITE operations. Could be multiple pins- In addition, Indicate whether you want to READ or Write: READ: Enable device output for READ operations (only operation on ROMs) using #OE or #G. If not enabled, output will be Hi-Z (floating), ORWRITE: (for RAM only) Enable device for writing using #WE input. Should not be active simultaneously with #OE- Some memory devices have one READ/WRITE control: R/#W

    Memory Pin Connections Address Data Control

    OutputEnable

    Chip Select

    WriteEnable

    M

    Only forRAM

    Or #CE#S Or #G

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Memory Organization

    Many memory device are 8-bits in width. A 4K x 8 memory chip contains 4,096 (4K)

    memory locations, each containing 8-bits A 16M x 4 memory chip has 16 M memory

    locations, each being 4-bits wide A 512M byte DDR* memory card for your PC

    is organized as a 64M x 8 bytes. It contains eight 64M x 1-byte memory devices

    ___________________________________* Double Data Rate, SDRAM with data transfer at both clock edges

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Read Only Memory DevicesTypes of read only memory: (Programming getting easier)

    ROM- Device permanently programmed in factory by manufacturer- Must be large number (10,000 pieces) to justify cost- Once manufactured, can not be erased or reprogrammed

    PROM- Programmable ROM (Programmed once)- When number of devices required is too small to justify high factory programming cost- Programmed in a PROM programmer that burns fuse links (not in situ)- Once programmed, can not be erased for reprogramming- Changes? Throw device away and program another one!

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Read Only Memory Devices EPROM

    - Erasable Programmable ROM (Programmed many)- Used when:

    * Contents need to be changed, e.g. during the development phase of a product

    - Erased and reprogrammed in an EPROM programmer (i.e. not in situ)

    - Erasing is by exposure to UV light for say 20 minutes

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Read Only Memory Devices, Contd. EEPROM

    - Electrically Erasable Programmable ROM (Programmed many many and in situ)- Other names: RMM (Read mostly memory), NOVRAM (Non Volatile RAM), Flash memory- Erasing and reprogramming is made so easy (and in situ) that it can be thought of as writing (hence RAM, but with data not volatile)- Erasing/writing takes longer time than writing into a RAM, but this is OK since it is done less frequent- Applications: BIOS, Memory for digital cameras and MP3 audio players, USB storage devices, etc.

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Memory Example: The 2716 EPROM

    2

    7

    1

    6

    2K x 8 read only memory

    1 bit + 10 bits = 11 Address inputs

    8 Data outputs

    Members of the 27XXXX family:- 2704 : 512 x 8- 2708 : 1K x 8- 2716 : 2K x 8- 2732 : 4K x 8- 2764 : 8K x 8- 27128 : 16K x 8- 27256 : 32K x 8- 27512 : 64K x 8- 271024: 128K x 8

    = Memory capacity in K bits

    All devices are 8-bit wide

    Address

    Data

    Ctrl

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    = OE/PREAD/Program

    #R/W

    Vpp: ProgrammingSupply Voltage

    = OE/P

    2 Control Pins

    8 Columns

    256 Rows

    Program: Apply Desired Data Content DIN to Outputs

    ChipSelect

    #OE/P

    The 2K memory locations are organized as a matrix of 256 rows x 8 columns3-bit8-bit11-bit address

    3-bit

    8-bit

    Byte

    8 Bytes

    SameEffect

    Select aByte

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Memory Access Time = 450 ns Max

    For the 8088/86: Max memory access time allowed was 420 nsSo, this EPROM needs 1 wait state inserted!

    #RD from P

    A0-A10 from PA11-A19 from P ? Decode for #CS

    Note: Here #CS and PD/PGMare used interchangeably. We Prefer to have CS obtainedthrough address decoding

    Device is being read

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Writing is needed more often than with EEPROMs should be easier, faster

    Two main types of RAM:- Static RAM- Dynamic RAM

    RAM Memory Devices

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Static RAMRAM Memory Devices

    A memory device that retains data for as long as power is applied. A static RAM memory cell consists of a pair of inverters connected as a flip flop for each bit of storage

    BistableMulti-vibrator

    Has 2 stable states.(O/P=1 or O/P =0).It remains indefinitely in its current stateUntil changed by the inputs, or power is brought down

    Flip Flopkeeps Input data savedafter it disappears from the input

    1 00

    Momentarily to 0 to write a Permanent 1 at output

    Momentarily to 0 to write a Permanent 0 at output

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Static RAM (SRAM) A relatively complex cell circuit (several transistors

    per bit storage) That is why static RAM devices are more

    expensive and are typically smaller in capacitycompared to dynamic RAM(A given # of transistors available on a chip gives fewer memory locations)

    Faster than dynamic RAMs, speeds down to 1 ns access time are now available

    Used for high speed cache memories (small, fast) It is rarely the case that a large computer RAM

    system uses only static memory type

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

    Static RAM Example: the 4016 2K x 8 RAM (same size as the 2716) 11 bit address (A0-A10),

    8-bit data (DQ1-DQ8): Data in/Data out Also produced with the numbers 2016

    and 4116 #CS is #S, #OE (#RD) is #G,

    #WR is #W Range of speeds: access times in

    the range 120 ns to 250 ns (various chip versions, e.g. TMS4016-25 has 250 ns access time)

    All can be interfaced with the 8088/8086 without wait states (ta< 420 ns)

    Control

    Address

    Data

    Control

    D Q(I/P) (O/P)

  • 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey:

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