microprocessor 1

7/16/2019 Microprocessor 1

http://slidepdf.com/reader/full/microprocessor-1-5633884286525 1/73

© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

Chapter 10

Memory Interface




Objectives

• Describe various memory types

• Describe memory pin connections• Use decoders and PLDs (programmable logic

devices) to decode memory addresses

• Explain how to interface RAM and ROM to amicroprocessor

• Interface dynamic RAM to the microprocessor

• Explain operation of dynamic RAM controller

• Interface memory to all Intel microprocessors using8-, 16-, 32-, and 64-bit data buses




Types of Memory Devices Two main types of memory:

• ROM

- Read Only Memory

- Non Volatile data storage (remains valid after power off)

- For permanent storage of systemsoftware and data

- Can be PROM, EPROM or EEPROM (Flash) memory

• RAM

- Random Access Memory (a misnomer - better Read/Write)

- Volatile data storage (data disappears after power off)

- For temporary storage of application software and data

- Can be SRAM (static) or DRAM (dynamic)


http://slidepdf.com/reader/full/microprocessor-1-5633884286525 4/73© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

• Address Inputs:- Select the required locationin memory.- Address lines are numberedfrom A0 to as many as requiredto address all memory

locationse.g. 12-bit address: A0-A11⇒212 = 4K memory locations- Today’s memory devices

have capacities upto around1G locations (30 addresslines)- Example: 4K memory: 12 bits:

000H-FFFH. e.g. from301000H to 301FFFH on an80286 system

Memory Pin Connections

• Address • Data • Control

ChipSelect OutputEnable

OutputEnable

ChipSelect

WriteEnable

M

-Select chip-Specify whether you want

a READ or WRITE operation

ROMs have no WE control

Decodethis partfor CS

Only for

RAM



• Data Inputs/Outputs (RAM)Data Outputs (ROM)

- Number of lines = width of data storage, usually a byteD0-D7 (M=7)

- Processor with wider databuses use multiple of suchbyte-wide memory devices,

e.g. 64-bit⇒ 8 x 8-bit devices- Sometimes the total memorycapacity is expressed in bits,e.g. a 64K x 8-bit = 512 Kbit



OutputEnable

ChipSelect

WriteEnable

M

Only for

RAM



• Control Inputs

- Chip Enable (#CE), or Chip Select(#CS), or simply Select (#S). Select the

memory device for READ or WRITEoperations. Could be multiple pins- In addition, Indicate whether you wantto READ or Write:

Æ READ: Enable device output forREAD operations (only operation onROMs) using #OE or #G. If notenabled, output will be Hi-Z (floating),

ORÆWRITE: (for RAM only) Enabledevice for writing using #WE input.Should not be active simultaneouslywith #OE- Some memory devices have oneREAD/WRITE control: R/#W



OutputEnableChipSelect

WriteEnable

M

Only for

RAM

Or #CE#S Or #G



Memory Organization

• Many memory device are 8-bits in width.

• A 4K x 8 memory chip contains 4,096 (4K)memory locations, each containing 8-bits

• A 16M x 4 memory chip has 16 M memorylocations, each being 4-bits wide

• A 512M byte DDR* memory card for your PC

is organized as a 64M x 8 bytes. It containseight 64M x 1-byte memory devices

___________________________________ * Double Data Rate, SDRAM with data transfer at both clock edges



Read Only Memory Devices Types of read only memory: (Programming getting easier…)

• ROM

- Device permanently programmed in factory by manufacturer

- Must be large number (≈10,000 pieces) to justify cost

- Once manufactured, can not be erased or reprogrammed

• PROM

- Programmable ROM (Programmed once)

- When number of devices required is too small to justify highfactory programming cost

- Programmed in a PROM programmer that burns fuse links(not in situ)

- Once programmed, can not be erased for reprogramming

- Changes? Throw device away and program another one!



Read Only Memory Devices

• EPROM

- Erasable Programmable ROM (Programmed many)

- Used when:

* Contents need to be changed, e.g. during

the development phase of a product- Erased and reprogrammed in an EPROM

programmer (i.e. not in situ)

- Erasing is by exposure to UV light for say 20 minutes



Read Only Memory Devices, Contd.

• EEPROM

- Electrically Erasable Programmable ROM

(Programmed many many … and in situ)- Other names: RMM (Read mostly memory),NOVRAM (Non Volatile RAM), Flash memory

- Erasing and reprogramming is made so easy (and insitu) that it can be thought of as writing (hence RAM,but with data not volatile)

- Erasing/writing takes longer time than writing into aRAM, but this is OK since it is done less frequent

- Applications: BIOS, Memory for digital cameras and

MP3 audio players, USB storage devices, etc.



Memory Example: The 2716 EPROM

2 7 1 6

• 2K x 8 read only memory

• 1 bit + 10 bits = 11 Address inputs

• 8 Data outputs

• Members of the 27XXXX family:- 2704 : 512 x 8

- 2708 : 1K x 8

- 2716 : 2K x 8

- 2732 : 4K x 8- 2764 : 8K x 8

- 27128 : 16K x 8

- 27256 : 32K x 8

- 27512 : 64K x 8

- 271024: 128K x 8

= Memory capacity

in K bits

All devices are 8-bit wide

Address

Data

Ctrl

Vpp: Programming 2 Control Pins



= OE/PREAD/Program

≈ #R/W

Vpp: Programming

Supply Voltage

= OE/P

2 Control Pins

8 Columns

256 Rows

Program: Apply Desired Data Content DIN to Outputs

Chip

Select

#OE/P

The 2K memory locations are organized as a matrix of 256 rows x 8 columns3-bit8-bit11-bit address

3-bit

8-bit

Byte

8 Bytes

SameEffect

Select a

Byte

D i i b i d




Memory Access Time = 450 ns Max

For the 8088/86: Max memory access t ime allowed was 420 ns

So, this EPROM needs 1 wait state inserted!

#RD fromμP

A0-A10 fromμP

A11-A19 fromμP ? Æ Decode for #CS

Note: Here #CS and PD/PGMare used interchangeably. We

Prefer to have CS obtained

through address decoding

Device is being read

RAM M D i




• Writing is needed more often than withEEPROMs → should be easier, faster

• Two main types of RAM:

- Static RAM

- Dynamic RAM

RAM Memory Devices

RAM M D i




Static RAM

RAM Memory Devices

• A memory device that retains data for as long as

power is applied. A static RAM memory cellconsists of a pair of inverters connected as aflip flop for each bit of storage

Bistable

Multi-vibrator

Has 2 stable states.

(O/P=1 or O/P =0).

It remains indefinitely in its current stateUntil changed by the inputs, or power is brought down

Flip Flopkeeps Input data savedafter it disappearsfrom the input

1 00

Momentarily to 0 to write a

Permanent 1 at output

Momentarily to 0 to write aPermanent 0 at output

St ti RAM (SRAM)




Static RAM (SRAM)• A relatively complex cell circuit (several transistors

per bit storage)

• That is why static RAM devices are more

expensive and are typically smaller in capacitycompared to dynamic RAM

(A given # of transistors available on a chip gives

fewer memory locations)

• Faster than dynamic RAMs, speeds down to 1 ns

access time are now available• Used for high speed cache memories (small, fast)

• It is rarely the case that a large computer RAM

system uses only static memory type




Static RAM Example: the 4016

• 2K x 8 RAM (same size as the 2716)• 11 bit address (A0-A10),

8-bit data (DQ1-DQ8): Data in/Data out

• Also produced with the numbers 2016and 4116

• #CS is #S, #OE (#RD) is #G,#WR is #W

• Range of speeds: access times inthe range 120 ns to 250 ns(various chip versions, e.g.

TMS4016-25 has 250 ns access time)• All can be interfacedwith the 8088/8086 withoutwait states (ta<420 ns)

Control

Address

Data

Control

D Q

(I/P) (O/P)

4016 SRAM




4016 SRAM• See Fig. 10-5 fornotes and timingdetails

READ Cycleta(A) = Access time (from address)

= 250 ns for the TMS4016-25

#WR is inactive high throughout

WRITE Cycle

Note setup (su) and hold (h)time requirements forAddress (A), data (D),and control (S)relative to #W

Same pin

Enable O/P

Disable O/P (makes O/P Hi-Z)

O/P goes Hi-Z

to enable data in

Stored data

appears at O/P

Strobe data in

by memory at #W edge

Min Cycle time

Generated by

decoding A11-A19

& M/#IO

(#RD)

(#RD)

(#WR)

#RD isInactive

Highthroughout Can be late

Hi-Z

Note #G is #OE:So, Output is disabled i.e. HiZwhenever #G is high

(not shown)

Generated by

decoding A11-A19

& M/#IO

: Active Control

Strobe data inby μP at start of T4

1 Electrical Characteristics




4016 SRAM: Data Tables1. Electrical Characteristics

2. Minimum Timing Requirements

3. Timing Characteristics

Delays, etc. that actually take place

in the device. Guaranteed values, e.g.Max access time.

Specified as: (Max or Min)

Minimumtiming requirements thatmust be satisfied for the device towork properly, e.g. on pulsewidths, setup times, hold times.

Specified as: Min

DC supply voltage and currents. Rangeof output voltages and currentsrecommended to ensurespecified operating characteristics

Specified as: (Min or Max)

Several Models with different speeds

Figure 10-5




Dynamic RAM (DRAM)

• Unlike static RAM, data is store as a voltage across a capacitor (charge)• Charge of course leaks with time, and data needs to be refreshed

(re-written) every say 2-4 ms• Recent devices usually organized as XX K x 1 bit, largest is say 2G x 1

• Advantages:– Simpler cell circuit (1 Transistor/bit)– Hence larger capacities allowed:

With Largest SRAM ≈ 8 Mbits,

Largest DRAM ≈ 1024 Mbits– and lower cost than SRAM

• Disadvantages:– Slower access times (e.g. 20 ns Vs 1 ns)

– Needs refreshing: e.g. every 4 ms max (added complexity)But not that bad!:Occurs also during normal reads and writes. Special hidden refreshcycles occurring simultaneously with other memory accesses (cycle

stealing). Dedicated DRAM refresh controller chips available.– Large storage capacity→ large address inputs → large number of chip

pins required→ Need for chip pin multiplexing (added complexity)

DRAM Example: the 4464




DRAM Example: the 4464• 64 K x 4 DRAM

• 6 bits + 10 bits = 16 bits memory address• But only 8 address lines on the chip!

• 16 address lines split into row and column8-bit parts:

• MS 8-bit row address is first latched inusing the #RAS input (Row Address Select)

• Then 8-bit column address is latched in using

the #CAS input• This loads the 16-bit address into a latchon the chip

• #CAS also acts as #CS

• #OE is #G, #WE is #W, #CS is #CAS• Access time: Fastest version is 100 ns?

15 9 8 7 3 2 1 0

Row Column

MSB

*

* and chip select

D Q(I/P) (O/P)

16-bitAddress

Also

a chip

select #S

(Read)

Timing Diagramfor Address Strobing




Timing Diagram for Address Strobing

Setup Times

Hold Times

#CS

Multiplexing the Row/Column Address




8-bit Muxed Address+ Row Strobe

To 4464 DRAM chip A0-A7: 8-bit Column

Address (LS)

A8-A15: 8-bit Row

Address (MS)

Multiplexing the Row/Column Address

S = 1 (Row)

74157 Data Multiplexers

2 x (4 x 2-to-1 MUXs)

Select Input

MUX Delay

MUX delay > Required Hold timefor row address

So #RAS can be used as aselector I/P for the MUX and alsoas input to the DRAM to strobe

Row address in,i.e. #RAS signal select the row thenthe Col address & its falling edgestrobes in the row address

MUX O/P

Select RowAddress

S = 0 (Column))

Select ColumnAddress

16-bit Full AddressFromμP

Muxing: The opposite of Demuxing

8 address

Inputs to chipCarry row then

Column addressRA Selector & Strobe

Row Strobe

We stil l require A #CAS Strobe

Internal Structure of a DRAM

512 Col A whole row can be refreshed at once




256 K x 1 bit DRAM = (256 x 256 x 4) x 1 bit (on the chip organization)

8 bits + 10 bits

= 18 bit address

Select

Section

Select

Column

8 Column

Selectors

Muxed to the chip on 9 Row/Column Address Lines

• 4 sections of 256 x 256 bits each• Each section is addressed by 8 bits of rows and 8 bits for columns• Remaining 2 address bits select the section addressed• Row and column addresses are common to all 4 sections• A whole row of 4 x 256 = 1024 bits is addressed simultaneously (Speeds up refreshing)• The 4 data bits in the addressed column in the 4 sections are addressed simultaneously

• Only the bit from the required section is selected by the remaining 2 address bits usingMUX # 3

Select

Row

8 8 2

2 bits of address

4 data bits from the 4 sections

Same row enabled

in all 4 sections

Same column enabled

in all 4 sections

8

512

Row

Refresh whole

rows: Only 512

refresh ops

DRAM M R f hi




DRAM Memory Refreshing• When a row is accessed in a refresh cycle, all memory cells on that row are

refreshed• This means that we need only 256 refresh operations to refresh all the 256K x 1

DRAM described in the previous slide• To refresh the whole memory at the minimum rate of once every 4 ms, we need to do

a refresh cycle every 4 ms/256 = 15.6 μs

• If a refresh cycle needs a bus cycle (4T with the 8088/86), the % of bus cycles lostfor refreshing an 8088/86 running at a clock speed of 5 MHz is:

= 4 x 0.2 μs / 15.6 μs = 5.1% (not bad … for the cost saving we achieve using

dynamic RAM)

• For a Pentium 4 with a clock cycle of 3 GHz and a bus/instruction cycle of 1T,this % is:

= 1 x 0.33 ns / 15.6 μs = 0.2% (i.e. the penalty for DRAM refreshing is much moretolerable with modern, faster processors)

15.6 μs

0.8μs…15.6 μs

4 ms (Refresh whole memory chip)

Only 256 Refresh operations

Cover all the memory!

What happens in a refresh cycle?




What happens in a refresh cycle?• #RAS only refresh cycles

• #RAS strobes a row address indicating the row of bits to beaccessed simultaneously for refreshing

• This row address is not a full memory address and can begenerated by a small on-chip counter(e.g. 8-bits for the 256 rows in the 256K x 1 DRAM described)

• The row cells read are fed back for re-writing into the samelocations to refresh them

4 ms/256 = 15.6 μs

Advanced DRAM Technologies




Advanced DRAM Technologies

• EDO (Extended Data Output) Memory- All 256 bits of the row from the selected section are saved in latches on thememory chip. So this data will be ready for future access withoutexperiencing the slow memory access time again- Such locations are close to the already accessed data, and are likely to beaccessed soon (locality principle)- Improves system performance by 15-25%

• SDRAM (Synchronous Dynamic RAM) Memory- Memory runs synchronously to the system bus clock, e.g. at 100-133-200

MHz• Burst (block) Transfers

Burst transfers of say 4 x 64-bit numbers between the processor and thememory. First number experiences normal delays, but 2nd, 3rd, and 4th

transfers suffer much less delay, thus improving average access time.• DDR (Double Data Rate) Memory– Data Transferred at double the SDRAM rate by using the two edges of the clock– This does not exactly double the data transfer rate due to access time limitations

• Combinations exist, e.g. DDR SDRAM

DRAM Memory Modules




y• DRAMs are often mounted on

memory modules interfaced to

the PC

• SIMM: Single In-Line MemoryModule: Devices andconnection pins mounted onone side. Available in 2 types:– Older 30-Pin SIMMs

– Newer 72-Pin SIMMs

• DIMM: Dual In-Line Memory

Module: Devices and pinsmounted on both sides.168-Pin

Used for Pentium- Pentium 4processors with 64-bit data bus(8 Bytes of data for eachmemory address)

Card can have one EPROM

containing info on size andspeed of the devices for Plug-and-Play use

1

2

9

9 x (4 M x 1 bi t)

= 4M x (8 + 1 Parity)

= 4MB of data

30-Pin

SIMM

72-Pin SIMM8 x (4 M x 4 bits

= 4M x (4 bytes)

= 16 MB of data

1 Byte- wide

e.g. for 8088

4 Bytes-

wide

168-Pin DIMM8 x (4 M x Byte)

= 32 MB of data

in DRAM, EDO and SDRAM

8 Bytes

wide

- Larger address- Wider data bus

4 M x 8 bits

4 M x 1 bit

4 M x 4 bits

Only 11 address

lines

Why?

LSB3 bits2 bits

Interfacing Memory to the Microprocessor:MSB




23Locations

23Locations

23Locations

23Locations

Interfacing Memory to the Microprocessor:Address Decoding

00

01

10

11

Binary addresses of 32 locations

5 bits of address:3 bits of address on memory2 bits of address to decode for #CS

Interfacing Memory to the 8088/86




g y /Microprocessor: Address Decoding

• Memory devices interfaced are usually of smaller storage capacity than the fulladdress space of the processor

• For example, the 2716 is 2 K x 8 memory

device has 11 (= 1 + 10) address inputs(A0-A10)• When interfaced to a microprocessor

with 20 address lines there is a mismatch

• The extra 9 address pins (A11-A19) aredecoded using a decoder such that theyselect the memory device for a uniqueposition in the memory map of theprocessor

• Here the μP address space is29 times the size of the memory chip• Decoding A11-A19 and using them for

selecting the memory chip fixes theposition of the memory locations in theμP address map

19 11 10 0

LS (11 bits)MS (9 bits)

Memory chip

11 Address bits

A10-A0

9 to 1

Decoder Chip Select

Address from μP

29 =512 times

.

.

211 =

20480

510

1

19 11 10 0

511

00000H

FFFFFH

000000001xxxxxxxxxxxb

LS (11 bits)MS (9 bits)

μP Memory Map

00800H

00FFFH

9 Selector b its

Selector

bits

High

Memory

(ROM)

Low

Memory

(RAM)

StartAddress

EndAddress

111111111

Address Decoding Techniques

WK6




Address Decoding Techniques1. Using a NAND Gate (CS is active low)Memory locations:FF800H-FFFFFH (2KB @ Top of the memory map)

2716: 2K x 8 EPROM

1111111110000000000011111111111111111111

A0 A19

Start (all 0’s for address within device)

End (all 1’s for address within device)

Common part makes the9 selector bits (decoder I/Ps)

A11 A10

Problems with using a NAND:

- Small memory devices requirelarge NAND gates- Need one NAND gatefor each memory device

- Not ideal for a memoryBlock of severalcontagious memory ChipsÆ Use decoders

Address within memory device A0-A10

Device selector Address A0-A10

8088 Processor

•Another Example (NAND Gate): 8088 Processor




p ( )- 32 K x 8 memory device: 215 locationsÆ15 bit on-chip address:

- “Chip Selector”address: 20 – 15 = 5 bits- If we want the memory locations to start at10000H,

What is the selector address to decode?:

Start Address 00010000000000000000 =10000H

- Selector 5 bits: 00010 (Remain fixed)

- End address 00010111111111111111 =17FFFH

- Check: These are 7FFF+1 = 8000H = 215 locations

0To chip Select

#CS (Act ive low)

00010

MSB

5 Select bits

Note:

Should also include M/#IO

MSB

Start

End

LSB

2 Using an n-to-2n Decoder ICs (e g 3-to-8)




• The Decoder is used for demultiplexing(expanding) (few to many)

• An n-input decoder replaces 2n NANDgates

• Active low outputs also suit the #CSmemory inputs

• Two common decoders are the 74138

and the 74139– The ‘138 is a 3-to-8 decoder with

3 Enable inputs

2. Using an n-to-2 Decoder ICs (e.g. 3-to-8)

ÆProblem: all memory devices selected usingthe outputs of a given decoder mustoccupycontiguous locations in the memory map

Æ The ‘139 is a dual 2-to-4 decoder(2 separate halves) with 1 Enable input

for each half

(Advantage for the ‘139)

SelectionAddress bits

#CS signals to 8 identical

Memory devices occupyingContiguous address locations

3-to-8

2-to-4

2-to-4

Decoder

Enables

n

2n

2

22

2

22

138

139

LSB1….0

1…0

1…0

‘138 Truth Table




138 Truth Table

Outputs Disabled-No selection- all outputs areInactive high

Outputs Enabled-Selection activated

0

1

2

3

4

56

7

LSB

‘138 ApplicationAnalysis Vs Design




138 Application- Block of Eight2764

EPROM chips- Each is 64 K bit = 8 K B= 213 x 8- Selector address bits =

20 – 13 = 7 bits (A19-A13)

•Decoder selected when G2B = 0 & G1 = 1, i.e. when A19-A16 = 1111 = FH•So, first address inwhole block of 8 EPROMs =F0000H, Last is FFFFFH

?

0

1

2

3

4

5

6

7

•Address range for chip 5: For Line 5, Inputs CBA = 101, so 7 selector bits = 1111101•So, first address in chip 5 is 11111010000000000000 = FA000H

and last address is 11111011111111111111 = FBFFFH

13 bits

To all 8 devices

3 10

Bottom of

Whole block:8 x 8 KB =64 K B(16 addr lines)

LSB

Any problems from

Sharing the data bus?

8 bits

To all 8 devices

‘139 Truth Table




139 Truth Table

1

1 1

To #CS

on 4 Memory Chips

To #CS

on 4 Memory Chips

•Two independent halves,

each 2-to-4 decoder

Advantage:

The two memory blocks (eachup to 4 chips) do not have to beadjacent in the memory map,

e.g. one can be at high memory(ROM) and one at low memory(RAM)…

Truth TableFor each half

0

1

2

3

Disabled All O/P Disabled

Selection Enabled

128 K x 8 EPROM= 128 KB

1024 K bit




1/2

1/2128 K x 8 DRAM

17 Address bits

(LS)

Remaining

3 Address bits

(MS): A19-A17

IO/#M

= 1 for memory

accesses

G = 0 (Enabled)

For memory accesses & A19 = 1

1110→ E0000H1110→ E0000H1110→ E0000H

1111→ FFFFFH

Top

High

Memory

0000→ 00000H

0001→ 1FFFFH

G = 0 (Enabled)

For memory accesses

CE2 = 1 (Enabled)

For A19 = 0

A18A17 = 00

BottomLow

Memory00000H

FFFFFH

00

01

10

11

00

01

10

11

Inverter

On-Chip Address: 7+10 = 17 bit

MS 3-bit address

111

Inverter

Only

Read

Read

Write

MS 3-bit address

000

RAM

EPROM

#RD

#WR

1024 K bitsAnalysis Vs Design

3. PLD Decoders (Ultimate Flexibility)




( y)

• Many modern systems use programmable logic decoders in place of integrated decoders• They give total freedomin decoding different addresses for individual

memory devices• Programmable logic devices have may be called:

- PLDs: Programmable logic devices- PLAs: Programmable logic array- PALs: Programmable array logic- GALs: Gate Array Logic- SPLDs: Simple programmable logic devices- CPLDs: Complex programmable logic devices

• They are all programmable logic devices. Nowadays they can beprogrammed using VHDL (Verilog Hardware Definition Language)

• Some types are programmed only once (fused links), similar to PROMs• Some types are erasable like EPROMs• The next slide shows one of the most common low cost (49¢) devices:

the PAL16L8

7 input OR

Upto 16-input Wired AND The PAL16L8AA BB CC1




7-input OR

Inverter/buffer

AND-OR-INVERT(Inverted sum of Products)

10 Inputs(1 to 10)

Programmable O/Ps

Inverter

A

B

C

Y Y = (ABC)+(ABC)

Active low O/PsSuit #CS inputs

Chip comes

with all crosspoints linked.Programmingremoves allunwanted links,e.g. by blowingout fused links

O/P

O/P

10

I/O

I/O

I/O

I/O

I/O

I/O

-10 Fixed Inputs

- 2 Fixed Outputs- 6 programmable

as inputs/outputsFor pin 16 to beinput, set this bufferto have Hi-Z o/p

OE

No connection

D0-D7

D0 - D7

U i A PAL t t th l t i l f th EPROM d DRAM f th

128 K x 8 EPROM




D0 D7

#RD#WR

Using A PAL to generate the select signals for the EPROM and DRAM of the139 decoder example.

128 K x 8 DRAM

PLD OutputsEPROM #CE: ROMDRAM #CE1: RAMDRAM CE2: AX19

PLD Inputs:IO/#MA17A19

CE2: Enable = high

#CE1: Enable = low

#CE: Enable = low

VHDL Code




library ieee;use ieee.std_logic_1164.all;entity DECODER_10_17 isport (

A19, A18, A17, MIO: in STD_LOGIC; Input declaration

ROM, RAM, AX19: out STD_LOGIC; output declaration

);end;architecture V1 of DECODER_10_17 isbegin

ROM <= not A19 or not A18 or not A17 or MIO; ROM = #CE = 0 forA19A18A17MIO = 1110

RAM <= A18 or A17 or MIO; RAM: #CE1 = 0 for A18A17MIO = 000

AX19 <= not A19; CE2: AX19 = 1 for A19 = 0

end V1;

Caution: Possible errors in textbook

Consider a NAND alternative

Interfacing memory to the 8088/80188




• 8-bitμP data bus → Easily interfaced to 8-bit memory devices• Assume minimum mode:

Memory sees the μP as a device having:- Address bus: A19-A0

- Data bus: D7-D0- Control signals: IO/#M, #RD, #WR (use in generating CS andRead/Write signals to memory)

• In maximum mode: the 8088 bus controller combines twocontrol signals into one:- IO/#M with #WR ⇒ #MWTC (C= control)- IO/#M with #RD⇒ #MRDC

• Will discuss :- Interfacing EPROM- Interfacing SRAM

- Interfacing EEPROM (Flash)

3 x 32 KB of EPROM at top of memory map




Interfacing EPROM to the 8088(450 ns Access time - Requires a Wait state)

32 K x 8 32 K x 8 32 K x 8

15-bit

Address

8-bitData

StartEnd

A19 A18 A17 A16 A15

1 1 1 0 1

So start address is : E8000H

A19 A18 A17 A16 A15

1 1 1 1 1

So end address is: FFFFFH

Act ive low. To c ircuit generat ing a wait

state request for every memory access

having A19A18 = 11, i.e. addressesC0000H to FFFFFH

00000H

FFFFFH

E8000H

96 KB at upper memory

FFFF0H

JUMP to EFFF0H

(cold start after RESET)

E8000H

EFFFFH

F0000H

F7FFFH

F8000H

FFFFFH

1 1 0

End

1 1

MemoryLocation on device

Level 1 DecodingDevice level:

Which location in device

Address from the processor

LSB

Log2 m




Memory Address Decoding Hierarchy

…

…

Memory

Device

Of m locations

Block 0

(p Devices)

Location on device

Log2m

Address bits

…

Level 2 Decoding

Block Level:

Which device in block

(Log2 p) to pDecoder

q such blocks

Block 1

(p Devices)

…(Log2 p) to p

Decoder

Log2 pAddress bits

Level 3 Decoding

Top Level:

Which block in memory

system

Log2 mLog2 p

(Log2 q) to q

Decoder

…

Log2 q

q p m = total addressing spaceLog2 (q p m) = size of address bus, bits

= log2 q +log2 p + log2 m

ContiguousBlock

q blocks X (p devices X m locations)

Device in block

block

Select I/Ps

Enable I/P

•SRAMs are easier

To in terface than EPROM:

Faster Æ do not require Waits

Each address pin connected to 16 inputs-

So buffering is needed, particularly if expansion likely!

8088 address pins: A0-A14

20-bit Address

15 bit3 bit2 bit

LSB



© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7eInterfacing SRAM to the 8088

00000H

FFFFFH

q

•SRAMs occupy lower memory

Where interrupt vectors reside.

As these need to be changed

by software

•4 blocks, each of (8 x 32K x8)

for a total of 512 KB in lower

Memory (1/2 the memory space)

(only 2 blocks are shown)

•Which device in a block:

Selected by a 3-to-8 decoders

at level 2

•Which block: selected by a

2-to-4 decoder at level 3

7FFFFH

8 x (32 K x 8)

8 x (32 K x 8)

= 256 KB S R A M 6

5 2 5 6

S R A

M 6

5 2 5 6

Output Buffers: Address & Control

Bidirectional Buffer: Data

1 2-to-4 Decoder in level 3

1 = Memory Access

Always 1

Hi-Z when

not enabled,to allow others

to control the

data bus

To remaining 2

decoders for

memory blocks at

A19A18 = 10,11

1: Any addresses

Buffer directioncontro lled by #RD not DT/#R.

DT/#R is the standard way

Always Enabled!

Level 2

Decoders

A17A16A15:

Level 3

Decoder:

A19A18

00100000…0=20000H

00100111…1=27FFFH

5+10 = 15 bit

On-chip address

A15

A15

A19=0 for al l SRAMs

This device:

3-to-8Used as a

2-to-4!

On-chipAddress

Whichchip

In block?

15 bit3 bit2 bit

WhichBlock?

Two 3-to-8 Decoders in level 2

Level 1

Level 1

Decoding Hierarchy

Level 1Level 2Level 3

SRAM

ROM

1 MB = 4 x 256 KB

i.e. 4 blocks

Only the lower 2 blocks

(SRAMs) are shown

Block of 8

Only 1st 2 out of 4

Block decoders

shown

0: Any Mem

Address

Standard is

#DEN

Interfacing EEPROM (Flash) Memories




Interfacing EEPROM (Flash) Memories

Main Flash memory applications :

Used when contents need to be changed only infrequently, e.g.:

• Storing system BIOS

• USB pen drives• MP3 audio players

Similarities with SRAMs:

Both need the 3 basic memory control inputs: CE, OE, and WE

Differences with SRAMs:

1. EEPROM needs additional:Æ Programming controlsÆ Programming (erasing) power supply. Used to be 25 or 12 V,

now 5 or even 3.3 V.

2. EEPROM is much slower to write (erase) a byte: e.g. 0.4 s Versus 10 ns forSRAM

Interfacing EEPROM (Flash) to the 8088 Data bus for byteoperation




28F400

Flash

Memory

512K x 8(In the Byte

Mode)

The 3 main memory control inputs (as in SRAM):

- CE by decoder

- OE during memory read

- WE during memory write

Addi tional controls for Flash memory. Used for programming (erasing)

Enable Power down mode

E

Programming supply voltage

Select Byte (not Word) operation

In Byte operation,

DQ15 is an inputaccepting A0

address bit.

10

0

Address:Start: 10000000000000000000

End: 11111111111111111111

i.e. 80000H to FFFFFH

In the word mode:

256 K x 16

18-bit address starting with A11/2

00000H

FFFFFH

7FFFFH80000H

Flash occupies the top

Half of the memory ma

Topof map

unused

0001

0

Interfacing 16-bit Memory to




g ythe 8086, 80286, and 80386SX

• Main differences: 8086 from the 8088:- The M/#IO control signal replaces the IO/#M

- The data bus is now 16 bits (word) not 8 bits (byte)- But processor should also be able to write into any byteit chooses:

Remember… AX can be used as AL and AH!- A new control output, #BHE [Bus (byte) High Enable]

- A0 has a special use as #BLE [Bus (byte) Low Enable]

• Main differences between 8086/186 and80286/386SX:- 80286/386SX has 24-bit address bus (A23-A0)

- The M/#IO, #RD, #WR are replaced by #MRDC,#MWTC, #IORDC and #IOWTC- more specific signals

16-Bit Wide Memory




y• 16-bit wide memory is organized in two separate 8-bit wide

memory banks:- Low bank (even-numbered byte locations: 0, 2, 4, 6, …)Æ low 8 bits of the data bus (D0-D7): LS Byte

- High bank (odd-numbered byte locations: 1, 3, 5, 7, …)Æ high 8 bits of the data bus (D8-D15): MS Byte

• Processor must be able to access any 16 or 8 bit locations• This is achieved through bank selection (Bank Enable) signals

• On the 8086, these byte selection signals are- The #BLE (A0) signal active: selects low bank- The #BHE signal active: selects high bank- Both #BLE and #BHE signals active: select both bytes (word)

• Only with writes…. For Reads, the processor will take the byteit wants and no need to enforce any byte (bank) selection

= A0

Banks




Same address from μP

for Word or low byte….!

Æ Use #BHE to remove ambiguity

Word address:

A0 is ‘Don’t care’ with in a word

(takes 0,1).ÆWord count starts with A1

0001000001

00000

A19…A1

Select

Words

A0

1

0

Select BytesWord address:121086

420

High Byte Low Byte

Enable with #BHE

Enable with A0 (#BLE)

Low BankHigh Bank

1

0

10

same

Invalid word access-

Crossing word boundaries (A1 changes!)

(LS Byte)

(MS Byte)

D7-D0D15-D8

B l o c k s

Word’s full address isis the address of

its starting byte

All valid wordaddresses areeven

Implementing Write Bank Selection

WK 7




Two ways to do bank selection during writes:- 1. With the Chip Select #CS (Separate Decoders for the two banks):

Same write signals for both banks, but separate decoders:

• More costly circuit (uses duplicate decoders)• But power saving on memory: Only required bank is enabled

- 2. With the Write Control #WE: (Same decoder for the two banks)

Same decoder for both banks, but separate write signals:• Least circuit cost (No duplicate decoders)

• But a bank is enabled even if not needed(increases power consumption)

Address

Chip Select

W Control

Address

Chip Select

W Contro lMemory chip consumes less powerwhen not selected by the #CS

Decoder

Important:Common address

to both chips

selects a word.

It start with A1 not A0

Low BankHigh Bank

OR

High Byte of Block:8 x (64K x 8)

High bank data bits

Low bank data bits

First 16 bits of the

1. Using Separate DecodersWrites




- Same Read, WriteControls to both banks

- Separate bank decoders

with the 80386SX

Low Byte of Block:8 x (64K x 8)

16-bit

Address

μP Address, excluding A0

Total: 2 x 8 x 64 K bytes= 1 M bytes

(Or A0)

Start Byte Address: 000000H

End Byte Address: 0FFFFFH

0000

A16(on-chipaddress numbering)

WR, RD signals are

commonto both banks

(Not shown)

Note: Starting wi th A1

not A0

Low Bank

of Block

High Bank

of Block

015

16-bit Data

LowHigh

Modify to enable both decoders during reads

A0Enabled onlyFor high bytes

Enabled onlyFor low bytes

Block

Block

Top 64K words

Bank Selection with Separate Write SignalsA0 may be called #BLE signal (microprocessor dependent)




A0 may be called #BLE signal (microprocessor dependent)

• Why consider this only with write access (not Reads)?

Because the processor can choose only the byte(s)

it wants to read from the full 16-bit data placed onthe data bus by the 2 banks.

So we always enable both banks for READs

Write Enable for

High bank chips

Write Enable forLow bank chips

For 8086.

For 80286/386SXUse #MWTC

(Or #BLE)

#RD#HRD

#LRDCommon- No byteselection for reads

32K 832K 8

High bank data bits

Low bank data bits

Note: A1




Memory Interfacing with separate Write strobesFor the two banks (80286 Processor)

Decode memory as 16-bit wide memory:2 X 32K X 8 = 64K X 8 = 64 K Bytes

= 32K X 16 = 32K words This renders A0 a don’t care (the 2 bytes are

taken as one entity)Æ 15 bits of device address are taken fromA1-A15

32K x 832K x 8

No bank selection for READs

Common to both banks

Low Bank High Bank

If start byte address is 060000, last byte address is 06FFFFHSEL = A23 + A22 + A21 + A20 + A19 + #A18 + #A17 + A16(active low)

Processor is 80286/386SX (24 bit address)

Common CE for both bank

Active Low (one decoder)

For generating LWR and HWR

WriteEnable

for low

bank

Write

Enable

for high

bank

Note: A1

not A0

Just the way

Address

Inputs

Are numberedOn the chip-

But A0 is taken

From processor A1

80286 Process

All

ActiveLow




library ieee;use ieee.std_logic_1164.all;entity DECODER_10_28 is

port (A23, A22, A21, A20, A19, A18, A17, A16, A0, BHE, MWTC: in STD_LOGIC;SEL, LWR, HWR: out STD_LOGIC

);end;

architecture V1 of DECODER_10_28 isbegin

SEL <= A23 or A22 or A21 or A20 or A19 or (not A18) or (not A17) or A16;LWR <= A0 or MWTC;HWR <= BHE or MWTC;

end V1;

Example: SRAM & EEPROM for the 8086




128 KB (64 K words) of SRAM

• Byte address Range:E0000H to FFFFF (17 bits changed)

Æ217 = 128 K bytes

• 4 x 32 KB devicesin 2 rows

64 KB (32 K words) of EEPROM

• Byte address Range:

00000H to 0FFFF (16 bits changed)Æ216 = 64 K bytes

• 4 x 16 KB devicesin 2 rows

EEPROM EEPROM

High Byte (D15-D8) Low Byte (D7-D0)

E0002E0003

Note: Usually SRAM is in lowermemory and EPROM in uppermemory, not as shown in this

example

• Note several corrections for Fig. 10-29

Banks

R o w s ,

B l o c k s

Row of Devices

Block of

Devices

SRAM Address Ranges:

1110 E0000H t EFFFFH




32 K B 32 K B 32 K B 32 K BSRAM

64 KWord

16 K B 16 K B 16 K B 16 K BEEPROM

Low Low High High

Low Low High HighNo bankSelection for

The EEPROMs

(No Writes enabled, used as EPROM)

1110→ E0000H to EFFFFH

1111→ F0000H to FFFFFH

1 1

1 0

1 1

1 0

EEPROM Address Ranges:

00000→ 00000H to 07FFFH

00001→ 08000H to 0FFFFH

A15

A15

A14

A14

0

0 0 0 0

0

0

To Wait Gen

Inverting Buffer

Bottom

Top

BottomTop

Low, High

Top,Bottom

Example: SRAM & EEPROM for the 80386SX• 24-bit Addressing




Æ128 KB (64 K words) of SRAM:

4 x 32 KB devices (in 2 rows)


000000H to 01FFFFH(000000H to 00FFFFH) & (010000H to 01FFFF)

Blocks: Bottom SRAM Row Top SRAM Row

+Æ 256 KB (128 K words) of EEPROM:

4 x 64 KB devices ( in 2 rows)


FC0000H to FFFFFF

(FC0000H to FDFFFFH) & (FE0000H to FFFFFF)

Blocks: Bottom EEPROM Row Top EEPROM Row

g


FC = 11111100FD = 11111101

(FC0000H to FDFFFFH)

CE Input bits arethe address bits that do notchange over the full address range

of the memory device

(000000H to 00FFFF)

00 = 00000000

RB3 Bottom EEPROMs




32 K B

High Low

32 K B

32 K Word

(Bottom)

High Low

32 K Word

(Top)

High LowEEPROM

SRAM

64 K Word

(Top)

High Low

64 K Word

(Bottom)

High Low

RB0: Bottom SRAMs A23….A17A16 A15 …..…A1

00000000XXXXXXXXX

RB0=A23+A22+A21+A20+A19+A18+A17+A16

RB1: Top SRAMs A23….A17A16 A15 …..…A1

0000001XXXXXXXXX

RB1=A23+A22+A21+A20+A19+A18+A17+A16

RB3: Bottom EEPROMs

A23….A17 A16 A15 …..…A1

1111110XXXXXXXXXX

RB3=NOT(A23.A22.A21.A20.A19.A18.A17)

RB2: Top EEPROMs

A23….A17 A16 A15 …..…A1

1111111XXXXXXXXXX

RB2=NOT(A23.A22.A21.A20.A19.A18.A17)

No byte selection

For EEPROMs

(only READs used

128 K Words EEPROM

64 K Words SRAM

32




library ieee;use ieee.std_logic_1164.all;entity DECODER_10_30 isport (

A23, A22, A21, A20, A19, A18, A17, A16, A0, BHE, MWTC: in STD_LOGIC;LWR, HWR, RB0, RB1, RB2, RB3: out STD_LOGIC);end;architecture V1 of DECODER_10_30 is

beginLWR <= A0 or MWTC;HWR <= BHE or MWTC;RB0 <= A23 or A22 or A21 or A20 or A19 or A18 or A17 or A16;RB1 <= A23 or A22 or A21 or A20 or A19 or A18 or A17 or not(A16));

RB2 <= not(A23 and A22 and A21 and A20 and A19 and A18 and A17);RB3 <= not(A23 and A22 and A21 and A20 and A19 and A18 and not(A17));

end V1;

Interfacing Memory to the80386DX and 80486 32 bit (address) Processors




• Four banks of 8-bit wide memory arerequired to build a functioning 32-bitwide memory system

• 4 byte wide memory implies thatμPaddress bits A0 and A1 are don’tcare. The processor uses theminternally to generate four separate#BE signals: #BE0,1,2,3

• The 80486 does not provide addresspins A0 and A1 on the bus

• Connect processor address to

memory address starting with A2• Use the BEi signals for byteselection in writes

• With the large number of address

bits (32), Decoding employs PLDsrather than IC decoders or gates(large address → More decoding)

80386DX and 80486 32-bit (address) Processors

00000007H

00000006H

00000005H

00000004H

00000003H

00000002H

00000001H

00000000H

000000….000 A2 A31

000000….001 A2 A31

A0 & A1 take al l

Possible combinations

Within the double word

→Don’t Care in double

word accesses

Double Word

Invalid

WordInvalid

Double Word

Valid 2n -byte entity:

Only n bits of addressChange when movingWithin the entity




•With 32 bit addressing: 2+30 bits→ 4 G Bytes canbe addressed, i.e. 1 GB in each bank

•Processor provides 4 bit enable signals: #BE3,#BE2, #BE1, and #BE0 to allow 8, 16, and 32 bit-wide memory accesses

•Use separate Write strobe signals to implementthe required data write operation

Byte Write

SelectionProcessor O/Ps

Example:




p

Interfacing a block of 256 KB of SRAMto an 80486 using 32 KB devices

80486Æ 4 data bytesÆ 4 memory banksÆ 4 devices per row

How many Rows (R)In the block ??

Device

4 Banks

Number of double words in block = R x 32 K

How to determine the number of rows of devices (R) needed?




rows of devices (R) needed?

Express the required total memory size required M bytes as

M bytes = R X (Number of banks) x Size of device in Bytes

If R ≤ 1Æ Need only one rowIf R > 1Æ Need R rows

Example: M = 256 KB, 80486, Using 32 KB devices

R = 256 KB / (4 x 32 K) = 256 K / (128K) =2 rows of devices

2 : 80864 : 80486

8 : Pentium

Address Decoding Design

• 256 K B of SRAM: Top: 128KB Bottom:128KB




• 256 K B of SRAM:- Top: 128KB, Bottom:128KB

= 2 x (4 x 32) KB

= 2 rows (Top: 128KB, Bottom:128KB)

• A 32 K B device uses 15 address lines on-chip: A16-A2

• Byte Address Range (Given):

02000000H

0201FFFFH

02020000H

0203FFFFH


0000001000000000

0000001000000001

A31

Bottom

Row128 KB

Top

Row

128 KB

A17

Device Address A16-A2

RB0 = A31+A30+…..+ #A25+A24+….+A17

00000010000000100000001000000011

A31

Device Address A16-A2

A17

RB1 = A31+A30+…..+ #A25+A24+….+#A17

From

To

Active lowRow Enables

Enable row of devices byDecoding bits that do not changeOver block address range

A1 A0

00

11

A1 A0

0011

15 bits

A16

A16-A2

256 K bytes = 64 K x 4 banks

4 bytes (banks)R = 256 K/(4*32K) = 2




Interfacing 256 KBof SRAM to the80486 using 32 KBdevices

Bank 3Bank 2 Bank 1 Bank 0

32 KB

Write Bank

Enable Signals

RB1

Top

Row

Bottom

Row

RB0

15 Address Lines

: A16-A2

Y

No byte selection

For READs

Two PLDs needed

(large address bus)

Same valuefor both rows

Interfacing 64-bit Memory to thePentium 2 and Pentium 4 Processors




• More banks! Pentium: 64-bit wide memory isorganized as an 8-bank wide system.

• The Pentium provides 8 bank enable signals(#BE0 to #BE7)

• Address bits A2-A0 are don’t care (ignored if present)

• Pentium: 32-bit address ⇒ 4 GB Address space⇒/8 = ½GB per bank

• Pentium Pro to Pentium 4: 36 bit address⇒ 64 GB⇒/8 = 8 GB per bank

M/#IO

W/#R

#MWTC

#BEi

8 #bank write select signals




Pentium: 32-bit address ⇒ 4 GB Address space⇒ 4/8 = 512 MB per bank

• A valid entity starts at entity boundaries

Interfacing Memory to the PentiumValid 2n -byte entity:

Only n bits of addressChange when moving




y y

(does not start in another entity of the sametype)• An entity is referenced by its start byte

address

• A byte (1) can “start”at any address• A word address (2) should start with 0• A double word (4) should start with 00• A quad word (8) should start with 000

Questions (for a Pentium):

• Is 56BED7A6 a valid byte, w, dw, qw?• How is ambiguity resolved?• If a word:ÆWhich BEi signals are activated?

ÆWhich of the 8 memory banks areenabled for writes?

00000007H

00000006H

00000005H

00000004H

00000003H

00000002H

00000001H

00000000H

QWInvalidWord

Invalid

D Word

Within the entity

DW W B

0110

InvalidQ Word

Entity

Boundaries

Interfacing 512 KBof EPROM to aPentium using64KB devices

Data Bus

R = 512 KB / 8 x 64 KB = 1 (only one block)




64 KB

R = 512K/(8*64KB) = 1

64KB devices: Æ satisfy

Requirement with

only ONE row of devices vertically

Located at top of upper memory: Total 512 K bytes = 19 bit

Last Address: FFFFFFFFFirst address: FFF80000

#CS = NOT(A31.A30.A29.A28.A27.A26.A25.A24.A23.

No bank selection for Reads (EPROM)

16 on-chip

address lines(A18-A3)

Data Bus 13 +16+3

Interfacing 4 MB of EPROM




to the Pentium using ½MBdevices

½ MB

19 on-chip

AddressLines A21-A3

R = 4 MB / (8 x ½ MB) = 1

Require only ONE row of devices

vertically

No bank selection for Reads (EPROM)

Located at top of upper memory: Total 4 M bytes = 22 bits

10 + (19 + 3) = 32

Last Address: FFFFFFFF

First address: FFC00000

#CS = NOT(A31.A30.A29.A28.A27.A26.A25.A24.A23.

A22) (Start from left )




library ieee;use ieee.std_logic_1164.all;entity DECODER_10_36 is

port ( A31, A30, A29, A28, A27, A26, A25, A24, A23, A22: in STD_LOGIC;SEL: out STD_LOGIC

);end;

architecture V1 of DECODER_10_36 isbeginSEL <= not(A31 and A30 and A29 and A28 and A27 and A26 and A25 and A24

and A23 and A22);

end V1;

Overview




• Described various memory types

• Described memory pin connections

• Used decoders and PLDs (programmable logicdevices) to decode memory addresses

• Explained how to interface RAM and ROM to amicroprocessor

• Interfaced dynamic RAM to the microprocessor

• Explained operation of dynamic RAM controller• Interfaced memory to all Intel microprocessors

using 8-, 16-, 32-, and 64-bit data buses

microprocessor 1

Documents