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<ul><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Chapter 10</p><p>Memory Interface</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Objectives Describe various memory types Describe memory pin connections Use decoders and PLDs (programmable logic </p><p>devices) to decode memory addresses Explain how to interface RAM and ROM to a </p><p>microprocessor Interface dynamic RAM to the microprocessor Explain operation of dynamic RAM controller Interface memory to all Intel microprocessors using </p><p>8-, 16-, 32-, and 64-bit data buses</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Types of Memory DevicesTwo main types of memory:</p><p> ROM - Read Only Memory - Non Volatile data storage (remains valid after power off)- For permanent storage of system software and data- Can be PROM, EPROM or EEPROM (Flash) memory</p><p> RAM - Random Access Memory (a misnomer - better Read/Write)- Volatile data storage (data disappears after power off)- For temporary storage of application software and data- Can be SRAM (static) or DRAM (dynamic)</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p> Address Inputs:- Select the required location in memory. - Address lines are numbered from A0 to as many as required to address all memory locationse.g. 12-bit address: A0-A11 212 = 4K memory locations- Todays memory devices have capacities upto around 1G locations (30 address lines)- Example: 4K memory: 12 bits: 000H-FFFH. e.g. from 301000H to 301FFFH on an 80286 system</p><p>Memory Pin Connections Address Data Control</p><p>Chip Select</p><p>OutputEnable</p><p>OutputEnable</p><p>Chip Select</p><p>WriteEnable</p><p>M</p><p>-Select chip-Specify whether you want a READ or WRITE operation</p><p>ROMs have no WE control</p><p>Decodethis part for CS</p><p>Only forRAM</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p> Data Inputs/Outputs (RAM)Data Outputs (ROM)- Number of lines = width of data storage, usually a byte D0-D7 (M=7)- Processor with wider data buses use multiple of such byte-wide memory devices, e.g. 64-bit 8 x 8-bit devices- Sometimes the total memory capacity is expressed in bits, e.g. a 64K x 8-bit = 512 Kbit</p><p>Memory Pin Connections Address Data Control</p><p>OutputEnable</p><p>Chip Select</p><p>WriteEnable</p><p>M</p><p>Only forRAM</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p> Control Inputs- Chip Enable (#CE), or Chip Select (#CS), or simply Select (#S). Select the memory device for READ or WRITE operations. Could be multiple pins- In addition, Indicate whether you want to READ or Write: READ: Enable device output for READ operations (only operation on ROMs) using #OE or #G. If not enabled, output will be Hi-Z (floating), ORWRITE: (for RAM only) Enable device for writing using #WE input. Should not be active simultaneously with #OE- Some memory devices have one READ/WRITE control: R/#W</p><p>Memory Pin Connections Address Data Control</p><p>OutputEnable</p><p>Chip Select</p><p>WriteEnable</p><p>M</p><p>Only forRAM</p><p>Or #CE#S Or #G</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Memory Organization</p><p> Many memory device are 8-bits in width. A 4K x 8 memory chip contains 4,096 (4K) </p><p>memory locations, each containing 8-bits A 16M x 4 memory chip has 16 M memory </p><p>locations, each being 4-bits wide A 512M byte DDR* memory card for your PC </p><p>is organized as a 64M x 8 bytes. It contains eight 64M x 1-byte memory devices</p><p>___________________________________* Double Data Rate, SDRAM with data transfer at both clock edges</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Read Only Memory DevicesTypes of read only memory: (Programming getting easier)</p><p> ROM- Device permanently programmed in factory by manufacturer- Must be large number (10,000 pieces) to justify cost- Once manufactured, can not be erased or reprogrammed</p><p> PROM- Programmable ROM (Programmed once)- When number of devices required is too small to justify high factory programming cost- Programmed in a PROM programmer that burns fuse links (not in situ)- Once programmed, can not be erased for reprogramming- Changes? Throw device away and program another one! </p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Read Only Memory Devices EPROM </p><p>- Erasable Programmable ROM (Programmed many)- Used when: </p><p>* Contents need to be changed, e.g. during the development phase of a product</p><p>- Erased and reprogrammed in an EPROM programmer (i.e. not in situ) </p><p>- Erasing is by exposure to UV light for say 20 minutes</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Read Only Memory Devices, Contd. EEPROM </p><p>- Electrically Erasable Programmable ROM (Programmed many many and in situ)- Other names: RMM (Read mostly memory), NOVRAM (Non Volatile RAM), Flash memory- Erasing and reprogramming is made so easy (and in situ) that it can be thought of as writing (hence RAM, but with data not volatile)- Erasing/writing takes longer time than writing into a RAM, but this is OK since it is done less frequent- Applications: BIOS, Memory for digital cameras and MP3 audio players, USB storage devices, etc.</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Memory Example: The 2716 EPROM </p><p>2</p><p>7</p><p>1</p><p>6</p><p> 2K x 8 read only memory</p><p> 1 bit + 10 bits = 11 Address inputs</p><p> 8 Data outputs</p><p> Members of the 27XXXX family:- 2704 : 512 x 8- 2708 : 1K x 8- 2716 : 2K x 8- 2732 : 4K x 8- 2764 : 8K x 8- 27128 : 16K x 8- 27256 : 32K x 8- 27512 : 64K x 8- 271024: 128K x 8</p><p>= Memory capacity in K bits</p><p>All devices are 8-bit wide</p><p>Address</p><p>Data</p><p>Ctrl</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>= OE/PREAD/Program</p><p> #R/W</p><p>Vpp: ProgrammingSupply Voltage</p><p>= OE/P</p><p>2 Control Pins</p><p>8 Columns</p><p>256 Rows</p><p>Program: Apply Desired Data Content DIN to Outputs</p><p>ChipSelect</p><p>#OE/P</p><p>The 2K memory locations are organized as a matrix of 256 rows x 8 columns3-bit8-bit11-bit address</p><p>3-bit</p><p>8-bit</p><p>Byte</p><p>8 Bytes</p><p>SameEffect</p><p>Select aByte</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Memory Access Time = 450 ns Max</p><p>For the 8088/86: Max memory access time allowed was 420 nsSo, this EPROM needs 1 wait state inserted! </p><p>#RD from P</p><p>A0-A10 from PA11-A19 from P ? Decode for #CS</p><p>Note: Here #CS and PD/PGMare used interchangeably. We Prefer to have CS obtainedthrough address decoding</p><p>Device is being read</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p> Writing is needed more often than with EEPROMs should be easier, faster</p><p> Two main types of RAM:- Static RAM- Dynamic RAM</p><p>RAM Memory Devices</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Static RAMRAM Memory Devices</p><p> A memory device that retains data for as long as power is applied. A static RAM memory cell consists of a pair of inverters connected as a flip flop for each bit of storage</p><p>BistableMulti-vibrator</p><p>Has 2 stable states.(O/P=1 or O/P =0).It remains indefinitely in its current stateUntil changed by the inputs, or power is brought down</p><p>Flip Flopkeeps Input data savedafter it disappears from the input</p><p>1 00</p><p>Momentarily to 0 to write a Permanent 1 at output</p><p>Momentarily to 0 to write a Permanent 0 at output</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Static RAM (SRAM) A relatively complex cell circuit (several transistors </p><p>per bit storage) That is why static RAM devices are more </p><p>expensive and are typically smaller in capacitycompared to dynamic RAM(A given # of transistors available on a chip gives fewer memory locations)</p><p> Faster than dynamic RAMs, speeds down to 1 ns access time are now available</p><p> Used for high speed cache memories (small, fast) It is rarely the case that a large computer RAM </p><p>system uses only static memory type </p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Static RAM Example: the 4016 2K x 8 RAM (same size as the 2716) 11 bit address (A0-A10), </p><p>8-bit data (DQ1-DQ8): Data in/Data out Also produced with the numbers 2016 </p><p>and 4116 #CS is #S, #OE (#RD) is #G, </p><p>#WR is #W Range of speeds: access times in </p><p>the range 120 ns to 250 ns (various chip versions, e.g. TMS4016-25 has 250 ns access time)</p><p> All can be interfaced with the 8088/8086 without wait states (ta&lt; 420 ns)</p><p>Control</p><p>Address</p><p>Data</p><p>Control</p><p>D Q(I/P) (O/P)</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>4016 SRAM See Fig. 10-5 for notes and timing details</p><p>READ Cycleta(A) = Access time (from address)</p><p>= 250 ns for the TMS4016-25</p><p>#WR is inactive high throughout</p><p>WRITE Cycle</p><p>Note setup (su) and hold (h) time requirements for Address (A), data (D), and control (S) relative to #W</p><p>Same pin</p><p>Enable O/P</p><p>Disable O/P (makes O/P Hi-Z)</p><p>O/P goes Hi-Zto enable data in </p><p>Stored dataappears at O/P</p><p>Strobe data inby memory at #W edge </p><p>Min Cycle time</p><p>Generated by decoding A11-A19&amp; M/#IO</p><p>(#RD)</p><p>(#RD)</p><p>(#WR)</p><p>#RD isInactive Highthroughout Can be late</p><p>Hi-Z</p><p>Note #G is #OE:So, Output is disabled i.e. HiZ whenever #G is high</p><p>(not shown)</p><p>Generated by decoding A11-A19&amp; M/#IO</p><p>: Active Control</p><p>Strobe data inby P at start of T4 </p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>4016 SRAM: Data Tables1. Electrical Characteristics</p><p>2. Minimum Timing Requirements</p><p>3. Timing Characteristics</p><p>Delays, etc. that actually take place in the device. Guaranteed values, e.g.Max access time.</p><p>Specified as: (Max or Min)</p><p>Minimum timing requirements that must be satisfied for the device to work properly, e.g. on pulsewidths, setup times, hold times.</p><p>Specified as: Min</p><p>DC supply voltage and currents. Range of output voltages and currents recommended to ensure specified operating characteristics</p><p>Specified as: (Min or Max)</p><p>Several Models with different speeds</p><p>Figure 10-5</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Dynamic RAM (DRAM) Unlike static RAM, data is store as a voltage across a capacitor (charge) Charge of course leaks with time, and data needs to be refreshed </p><p>(re-written) every say 2-4 ms Recent devices usually organized as XX K x 1 bit, largest is say 2G x 1 Advantages:</p><p> Simpler cell circuit (1 Transistor/bit) Hence larger capacities allowed: </p><p>With Largest SRAM 8 Mbits, Largest DRAM 1024 Mbits</p><p> and lower cost than SRAM Disadvantages:</p><p> Slower access times (e.g. 20 ns Vs 1 ns) Needs refreshing: e.g. every 4 ms max (added complexity)</p><p>But not that bad!:Occurs also during normal reads and writes. Special hidden refresh cycles occurring simultaneously with other memory accesses (cycle stealing). Dedicated DRAM refresh controller chips available.</p><p> Large storage capacity large address inputs large number of chip pins required Need for chip pin multiplexing (added complexity)</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>DRAM Example: the 4464 64 K x 4 DRAM</p><p> 6 bits + 10 bits = 16 bits memory address But only 8 address lines on the chip! 16 address lines split into row and column </p><p>8-bit parts:</p><p> MS 8-bit row address is first latched in using the #RAS input (Row Address Select)</p><p> Then 8-bit column address is latched in using the #CAS input</p><p> This loads the 16-bit address into a latch on the chip</p><p> #CAS also acts as #CS #OE is #G, #WE is #W, #CS is #CAS Access time: Fastest version is 100 ns?</p><p>15 9 8 7 3 2 1 0Row Column</p><p>MSB</p><p>*</p><p>* and chip select</p><p>D Q(I/P) (O/P)</p><p>16-bit Address</p><p>Alsoa chipselect #S</p><p>(Read)</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Timing Diagram for Address Strobing</p><p>Setup Times</p><p>Hold Times</p><p>#CS</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>8-bit Muxed Address + Row StrobeTo 4464 DRAM chip</p><p>A0-A7: 8-bit Column Address (LS)</p><p>A8-A15: 8-bit Row Address (MS)</p><p>Multiplexing the Row/Column Address</p><p>S = 1 (Row)</p><p>74157 Data Multiplexers2 x (4 x 2-to-1 MUXs)</p><p>Select Input</p><p>MUX Delay</p><p>MUX delay &gt; Required Hold time for row address</p><p>So #RAS can be used as a selector I/P for the MUX and alsoas input to the DRAM to strobeRow address in,</p><p>i.e. #RAS signal select the row thenthe Col address &amp; its falling edge strobes in the row address</p><p>MUX O/P</p><p>Select RowAddress</p><p>S = 0 (Column))</p><p>Select ColumnAddress</p><p>16-bit Full Address From P</p><p>Muxing: The opposite of Demuxing</p><p>8 addressInputs to chipCarry row thenColumn address</p><p>RA Selector &amp; Strobe</p><p>Row Strobe</p><p>We still requireA #CAS Strobe</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>Internal Structure of a DRAM256 K x 1 bit DRAM = (256 x 256 x 4) x 1 bit (on the chip organization)</p><p>8 bits + 10 bits = 18 bit address</p><p>SelectSection</p><p>SelectColumn</p><p>8 ColumnSelectors</p><p>Muxed to the chip on 9 Row/Column Address Lines</p><p> 4 sections of 256 x 256 bits each Each section is addressed by 8 bits of rows and 8 bits for columns Remaining 2 address bits select the section addressed Row and column addresses are common to all 4 sections A whole row of 4 x 256 = 1024 bits is addressed simultaneously (Speeds up refreshing) The 4 data bits in the addressed column in the 4 sections are addressed simultaneously Only the bit from the required section is selected by the remaining 2 address bits using</p><p>MUX # 3</p><p>SelectRow</p><p>8 8 2</p><p>2 bits of address</p><p>4 data bits from the 4 sections</p><p>Same row enabled in all 4 sections</p><p>Same column enabled in all 4 sections</p><p>8</p><p>512</p><p>512</p><p>Row</p><p>Col</p><p>Refresh wholerows: Only 512refresh ops</p><p>A whole row can be refreshed at once</p></li><li><p> 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e</p><p>DRAM Memory Refreshing When a row is accessed in a refresh cycle, all memory cells on that row are </p><p>refreshed This means that we need only 256 refresh operations to refresh all the 256K x 1 </p><p>DRAM described in the previous slide To refresh the whole memory at the minimum rate of once every 4 ms, we need to do </p><p>a refresh cycle every 4 ms/256 = 15.6 s</p><p> If a refresh cycle needs a bus cycle (4T with the 8088/86), the % of bus cycles lost for refreshing an 8088/86 running at a clock speed of 5 MHz is:</p><p>= 4 x 0.2 s / 15.6 s = 5.1% (not bad for the cost saving we achieve using dynamic RAM)</p><p> For a Pentium 4 with a clock cycle o...</p></li></ul>

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