Micro and nano on insulator

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2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim p s scurrent topics in solid state physicscstatussolidiwww.pss-c.comphysicaphys. stat. sol. (c) 5, No. 12, 35883593 (2008) / DOI 10.1002/pssc.200780195 Micro and nano on insulator Sorin Cristoloveanu* Institute of Microelectronics, Electromagnetism and Photonics (IMEP, UMR 5130), INP Grenoble Minatec, 3 Parvis Louis Nel, BP 257, 38016 Grenoble Cedex 1, France Received 28 November 2007, revised 7 May 2008, accepted 12 May 2008 Published online 18 September 2008 PACS 73.40.Qv, 73.40.Ty, 85.30.Tv * e-mail sorin@enserg.fr, Phone: +33 456 529 499, Fax: +33 456 529 501 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim 1 Introduction While the microelectronics is per-fectly defined, the notion of nanoelectronics is still under debate. Does it apply exclusively to nanostructures beyond CMOS? This definition is restrictive and elitist. A broader, more reasonable meaning covers all nano-size devices in-cluding MOSFETs. According to this scenario, CMOS and non-CMOS technologies will develop together in perfect synergy. The further shrinking of MOS transistors requires very thin semiconductor films deposited on insulator [1-22]. SOI-like technologies are not only necessary for scaling but also convenient for the fabrication of a variety of inno-vative structures. Recent and important technological achievements include strained Si, SiGe, Ge, dual crystal orientations, etc. These materials are not competing with SOI because they must be On Insulator. Otherwise, a poor electrostatic behavior of the transistor, which is quali-tatively independent on the material nature, will erase all benefits. In parallel to strain and crystal orientation techniques, a direct and efficient method for engineering the mobility of both electrons and holes is to reduce device self-heating [23]; this implies replacing the SiO2 buried oxide (BOX) by a different dielectric with improved thermal conductiv-ity [24-26]. From a fundamental point of view, these vari-ous approaches are just embellishments of SOI [27-35]. Changing the meaning of SOI, from silicon-on-insulator to semiconductoron-insulator, clarifies the ambiguity and provides a more general view. Key aspects of micro and nano devices on SOI are prospectively addressed in this paper. The scaling strategy is briefly discussed in Section 2. Selected nano-size mechanisms are reviewed in Section 3. The following sec-tions will describe the merits of double-gate, triple-gate and four-gate transistors. Finally, several types of non-CMOS devices are exemplified. 2 Nano-CMOS scaling Gradually increasing the channel doping was a very safe and successful strategy so far for expanding CMOS scaling on bulk Si. The summit of this sophisticated art consists in decorating the transistor body with heavy concentrations of dopant (halos, pockets, etc), engineering very thin source-drain regions with vari-ous compositions, and adding appropriate types of strain [1-5]. Then SOI came into the picture [2-7]. Not only bcause the transistor body is isolated by the buried oxide (BOX), but mainly because the BOX can sustain a silicon film with adjustable thickness. Thinning down the silicon film ap-pears to be an easier and more attractive solution for scal-ing than increasing the body doping beyond unreasonable levels [1-14]. The major short-channel effect in thin SOI is due to the penetration of the electric field from the drain into the BOX and substrate. The fringing field rises the surface po-The nano-size MOS transistor is the ideal device for the smooth transition from micro- to nanoelectronics, the strin-gent condition being to be fabricated On Insulator. It is the SOI thickness effect which renders the scaling of MOS tran-sistors intrinsically easier than in bulk Si. In addition, SOI is a most suitable substrate for the implementation of non-classic or pure nanoelectronic components. The dimensions of state-of-the-art SOI MOSFETs are already measurable in nanome-ters. We illustrate, from experimental and theoretical view-points, a number of nano-size mechanisms and their implica-tions for multiple-gate MOSFETs and alternative nano-devices. phys. stat. sol. (c) 5, No. 12 (2008) 3589 www.pss-c.com 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim InvitedArticletential at the film-BOX interface: drain-induced virtual substrate biasing (DIVSB) [10-11]. Since the front and back interfaces are naturally coupled, the front-channel threshold voltage is lowered with increasing drain bias. The scaling strategy in SOI is based on film thinning. A difference in body doping of 3 orders of magnitude does not have any effect on the threshold voltage lowering if the film thickness is correctly scaled down [11]. In ultra-thin SOI MOSFETs (~ 10 nm), the doping is irrelevant and can be safely omitted for the benefit of increased carrier mobil-ity [10-11]. Additional recipes include an extremely thin BOX [34] and a ground plane underneath [10]. The plain control of the transistor electrostatics is the guarantee for acceptable short-channel effects. In SOI, it requires a film thickness just one fourth of the channel length. Instead of having to place and discipline one dopant atom every 10 silicon atoms, we may need a Si film thin enough to contain 10 stacked atoms or less. Of course, this is another sort of challenge. In order to relax the film thickness constraint, it is nec-essary to reinforce the electrostatic control. The obvious solution is to border the transistor body with additional gates [1-10]. For a transistor featuring NG gates and a channel length L, the smallest dimension of the body (i.e., film thickness for planar MOSFETs or fin width for Fin-FETs and vertical MOSFETs) is relaxed from L/4 to NGL/4. For example, a double-gate (DG) device can be twice as thick as a single-gate SOI transistor. This is extremely im-portant and more realistic in terms of current CMOS/SOI technology. It also alleviates the pressure on SOI material engineers: a 3 nm thick Si film with 510% uniformity on large wafers (30 cm diameter) is a nightmare. As a bonus of DG MOSFETs, the drain current and transconductance being increased by roughly a factor of two, the circuit designers are delighted. They can even play with the two gates, by keeping them interconnected or bi-asing them independently. The DG FinFET with two inde-pendent gates (MuGFET) is a 4 terminal device where the two separate gates can be taken advantage of. The result is beneficial for new devices and reconfigurable circuits with enhanced functionality. Expressions like `paradigm shift or revolutionary design summarize a quantitative ap-proach (reduced transistor count for a given circuit or logic function) or a qualitative breakthrough (novel types of memories, logic functions, etc). Triple-Gate FinFETs [15-21] and Gate-All-Around (GAA) MOSFETs [3] exhibit even better electrostatic be-havior while requiring less dramatic thinning: the body size and channel length become comparable. However, these devices are not really multiple-gate transistors be-cause one single gate covers most of the exposed sections of the body. They feature multiple interfaces and corre-sponding channels rather than multiple gates. 3 Size effects in single-gate transistors Conven-tional SOI transistors are categorized as partially depleted (PD) or fully depleted (FD). PD circuits are currently mak-ing the success of the SOI microprocessor industry, whereas FD devices have far more potential for future scal-ing. The distinction between PD and FD becomes a diffi-cult exercise in short-channel transistors which tend to mix operation mechanisms borrowed from both families [31-33]. For example, a long PD transistor becomes FD after shrinking; but, according to the junction engineering proc-ess, the opposite case can also occur. In sub-10 nm thick films, interesting effects take place which refresh the transistor physics. Vertical quantum con-finement [35] and sub-band splitting become significant, affecting the threshold voltage and the carrier mobility. The coupling of the channel to BOX defects or substrate biasing is amplified (supercoupling) [36-42]. At a practical level, the series resistance increases drastically and may offset the excellent transport properties in the transistor body. Additional dimensional effects occur as a result of the simultaneous shrinking of the other dimensions: narrow channel effects [43-45], gate-induced floating-body effects (GIFBE) due to tunnelling through nanometer thick gate dielectrics [46-48], etc. Strain is also size dependent, either if it is embedded in the original SOI wafer (by Smart Cut and bonding process) or generated by the CMOS process. 4 Double-gate transistors An ideal DG MOSFET is viewed as a perfectly symmetrical device. The two chan-nels facing each-other are activated simultaneously and feature identical charge and mobility. The subthreshold slope matches the minimum theoretical value (2.3 kT/q, i.e. ~ 60 mV/decade at room temperature). As the body thick-ness decreases, the centroid of the inversion charge moves from the interfaces into the volume. This effect is called volume inversion [49]. Combined with a zero electric field in the middle of the body, volume inversion enables the mobility enhancement [10, 50-54]. Monte-Carlo simula-tions predict a maximum value of the electron mobility in 35 nm thick films as a result of competing effects: pho-non confinement, subband splitting which lowers the effec-tive mass, and reduced inter-band scattering [50, 53]. Genetically modified DG MOSFETs may have dual gate stacks, where the difference in work functions is use-ful for threshold voltage control. They also may feature a longer back gate, partially over-lapping the source and drain. Such a non-ideal DG transistor can outperform the ideal symmetrical DG structure because the bottom-gate mission is two-fold: (i) it contributes to volume inversion in the body and (ii) tends to drive the source and drain ex-tension regions into strong accumulation, so that the series resistance is dynamically lowered [55-56]. The problem is that nobody knows how to fabricate re-alistic planar DG MOSFETs. Many processing ideas have been tested. They were successful in generating papers, but not enough convincing for mass production. It is interesting to note that a standard planar FD MOSFET stands as the simpler form of asymmetric DG transistor. Indeed, the Si substrate underneath the BOX can 3590 S. Cristoloveanu: Micro and nano on insulator 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim www.pss-c.com physicap s sstatus solidi cbe used as a second gate. The trend in FD devices is to use a very thin BOX, with a ground plane underneath [10], which renders the back-gate action very efficient. For bal-anced DG operation, the inversion charges in the front and back channels must be equated. This is achieved by select-ing the threshold voltages and gate biases such as to ac-count for the device asymmetry: in strong inversion VG1 VT1 = (tox1/tox2) ( VG2 VT2) [57]. On the other hand, when one channel is inverted and the opposite channel is forced into accumulation, interest-ing effects applicable to innovative capacitor-less DRAMs are observed [58]. The basic idea is that the supply of ma-jority carriers (by impact ionization and band-to-band tun-neling) is a relatively slow process, leading to hysteresis and related memory effects. However, in films thinner than 510 nm, it becomes difficult to maintain one channel in inversion while driving the opposite channel into accumulation. The front and back channels actually tend together to reach inversion or accu-mulation, depending on the dominating gate voltage. The interface coupling effects are exacerbated leading to super-coupling. The film behaves as a rigid quasi-rectangular well: if the front-gate voltage is swept, the potential of the entire film follows [42]. In this case, the notion of front and back channels becomes obsolete. An important conse-quence is that the carrier mobility must be viewed as an in-depth integral. FinFETs are pragmatic DG devices, easy to fabricate, more difficult to optimize [15, 16]. Since the gates are on the lateral sides, the edges of the transistor need to be smooth and the inter-gate distance should be in the 10 nm range. The basic mechanisms in planar DG and FinFETs are more or less the same, simply transformed by a rotation from horizontal to vertical direction. Separating the two gates (MuGFET) is very useful for signal mixing and threshold voltage adjustment. But, if the two gates are kept interconnected, a better solution is to fabricate Triple-Gate FinFETs. 5 Triple-gate transistors A FinFET with an active top gate is named Triple-Gate MOSFET [59-69]. One sin-gle gate controls three different sections of the channel: two vertical and one horizontal. The discrimination of the different channels is possible by using the back-gate action and the variable fin width [59]. The top channel prevails in wide bodies whereas the contribution of the lateral chan-nels is extrapolated at zero fin width. The advantages of Triple-Gate FinFETs in terms of in-tegration density and performance are well understood [66]. Several aspects have attracted recent attention: (i) In a very tiny transistor, all conductive regions col-lapse in a unique central channel. This is another form of volume inversion [18, 63, 68]. (ii) The corner effect is due to the coupling between the adjacent gates which induces a local lowering of the threshold voltage [70]. This parasitic channel may cause an increase of the off-state leakage current. Fortunately, the corner effect is negligible in undoped transistors where quantum repulsion of carriers from interfaces and corners counteracts the electrostatic attraction. In heavily doped bodies, the parasitic conduction can be suppressed by cor-ner rounding. (iii) The local threshold voltage varies along the ver-tical channel, from the BOX to the top gate. This non-uniformity is negligible in undoped fins and increases with the doping level but remains lower than 25 mV [17]. (iv) The top and lateral channels have different crystal orientations and interface quality. The carrier mobility can be lower on the sidewalls. The challenge is to achieve per-fectly vertical and defect-free sidewalls. In a very small body with sub-10 nm thickness, width and length, the number of Si atoms is 104 or even less. This generates another set of intriguing questions: What is the minimum silicon cluster size below which the concepts of effective mass and energy bands should be revisited? What are the meaning and impact of one single impu-rity in the body? Can we still address surface roughness in a statistical mode when only one imperfection (Si-Si bond in suboxide or oxygen protrusion in Si) may exist in a transistor [71]? The optimization of Triple-Gate FinFETs is a matter of trade-off between drive current (wide top channel) and electrostatic control (narrow fin). The coupling effects are truly 3D, with three components [17]: (i) lateral coupling between the side gates, (ii) vertical coupling between the top gate and the bottom gate (substrate), and (iii) longitu-dinal coupling between the drain and the body via the fringing fields penetrating in the BOX and substrate. Wide fins do behave as FD MOSFETs with strong ver-tical coupling and little impact of the lateral gates. By con-trast, in tall and narrow fins, the electrostatics is governed by the coupling of the lateral gates, which inherently tends to reduce or suppress the vertical coupling to the bottom gate [65,69]. The main point is that the surface potential at the fin-BOX interface can be totally controlled by the fringing field between the lateral gates [17]. As compared to the pure Triple-Gate FinFET (where NG = 3), the control of back-surface potential is reinforced by letting the lateral gates to extend vertically into the BOX (gate where NG 3+) and laterally underneath the film (gate where NG 4) [60-68]. As a result, the de-fects generated in the BOX by processing, radiations or hot carrier injection have no chance to impact the device performance [72]. In addition, the longitudinal drain-to-body coupling is screened by the lateral gates, reducing the short-channel effects [17]. Narrow Triple-Gate FinFETs are expected to have a considerable impact on the future nano CMOS because they are intrinsically radiation-hard [72] and tolerant to short-channel effects. The Gate-All-Around (GAA) MOSFET features 4 channel sections (or apparent gates, NG = 4), unless the body is cylindrical. A GAA combines channels coupling phys. stat. sol. (c) 5, No. 12 (2008) 3591 www.pss-c.com 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim InvitedArticleand quantum effects [3]. It is the ideal device in terms of electrostatic control as it perfects the qualities of FETs. Recent achievements include GAA nanowires which can even be superposed for more efficient integration [73,74]. The on/off current levels, transconductance and short-channel effects are very attractive in GAA MOSFETs and Triple-Gate FinFETs. Still these elegant and performing devices are conceptually poorer than a DG MOSFET with two independent gates. In this sense, their flexibility is even lower compared to a planar fully depleted single-gate (SG) transistor, where a back gate can be activated by bias-ing the substrate. It is a lot easier to apply two different signals to a SG MOSFET, by promoting the substrate as a back gate, than to apply 3 simultaneous signals to a unique gate even if this gate is named Triple-Gate. Ironically, in GAA and well optimized Triple-Gate MOSFETs, the back-gate effect is no longer an available option because the lat-eral gates control the potential everywhere and screen the substrate effect. 6 Four-gate transistor The G4FET is derived from a basic SOI MOSFET provided with two lateral body con-tacts [22]. The only difference is the current direction and the roles given to the various terminals. The current is driven by majority carriers flowing between the body con-tacts, which are redefined as source and drain. There are 4 independent gates: the usual front and back MOS gates govern the status of the Si-SiO2 interfaces (surface accu-mulation, inversion, or vertical depletion), whereas the two lateral junctions (JFET gates) control the effective width of the body through the extension of the horizontal depletion regions. The conduction path is modulated by mixed MOSJFET effects: from wire-like volume conduction to strongly accumulated front and/or back interface channels. Analyti-cal models are available for each mode [75]. In volume conduction, the device operates as a nanowire. The striking feature is that the diameter of the wire is not dependent on lithography sophistication, be-cause it is actually defined by the gate biases and measured by the current value. The volume conduction mode is also very efficient to suppress noise and radiation damage [76, 77]. This is because the channel is double shielded from the interfaces, first by the depletion region and second by the inversion layers. The G4FET is a surprisingly efficient tool to answer fundamental interrogations. Changing the biasing mode from volume to surface conduction made it possible to elu-cidate the origin of 1/f noise: mobility fluctuations in vol-ume mode, where trapping is absent, and carrier number fluctuations, via trapping, in surface conduction mode [76]. It is the first experimental demonstration of transition from Hooges mobility fluctuations model to McWhorters car-rier trapping model. On the practical side, the fact that each gate has the capability of switching the transistor on and off is an asset for novel applications. For example, the characteristics of an inverter can be shifted or adjusted by appropriately bias-ing the lateral gates. A simple inverter can thus be recon-figured in a NOR, NAND or majority voting gate without any hardware. Other preliminary examples include mixed-signal circuits, compact logic functions, negative-resistance devices, single-device memory, etc. 7 Non-conventional nano-devices Vertical 3D in-tegration aims at stacking successive SOI layers. For ex-ample, a 3D image-signal processor contains arithmetic units and memories in bulk-Si bottom level, fast A/D con-verters in an intermediate SOI layer, and photodiode arrays in an upper SOI layer [8]. The SOI family also includes optical devices: switches, waveguides, and modulators. 3D integration of nano-size devices attracts a large in-terest. For example, 3D arrays of nanowires have been fab-ricated using a combination of GAA and SON (silicon-on-nothing) processes. Four periods of Si and sacrificial SiGe layers have been epitaxially grown. After e-beam pattern-ing and plasma etching, the SiGe layers were removed leaving free-standing crystalline fins connected to the source and drain. Encapsulation with SiO2/Si3N4/W lead to stacked GAA nanowires with 30 nm diameter. They ex-hibit well behaved characteristics, reasonable mobility and clear current gain as compared to planar MOSFETs [74]. Tunnel N+/P+ Esaki diodes, either gated or not, were successfully demonstrated. The advantage of SOI is to of-fer very low leakage current, which magnifies the negative resistance region, and back gating for further conductance modulation [78]. The isolation capability of SOI was utilized to make single-electron transistors (SET) [79]. Silicon islands were patterned and sacrificially oxidized to achieve minimum volume Si clusters. When two such SETs are intercon-nected, an inverter with gain higher than unity was ob-tained. This approach opens the avenue of ultra-low power SET-based logic devices. SOI also serves as template for sensors and MEMS, ei-ther for processing ease or for ultrathin-film capability. This domain is vast and will not be developed here. How-ever, an interesting example is offered by the pseudo-MOSFET which takes advantage of the intrinsic upside-down MOS configuration of the SOI structure. The sub-strate is biased as a gate and the film plays the role of tran-sistor body. Two probes are used as source and drain. Per-fect transistor characteristics are obtained, normally serv-ing for material characterization [27-29]. In nanometer thin films, these characteristics are sensitive to whatever mate-rial is deposited on the top free surface. This principle has recently been used to monitor and detect DNA deposition [70]. It can be extended to other bio-sensing devices, for the benefit of cross-disciplinary research. 8 Conclusion The nano-size multiple-gate SOI MOS transistor is an ideal candidate for the future landscape of the microelectronics, including the transition from micro- to nano-devices and systems. The MOSFET scaling is in-3592 S. Cristoloveanu: Micro and nano on insulator 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim www.pss-c.com physicap s sstatus solidi ctrinsically easier in SOI than in bulk Si, where it is becom-ing a desperate issue. The key condition is to utilize ultra-thin bodies and to open the SOI family to any kind of semiconductor, strained or not, on any type of dielectric. On Insulator is a necessity because there is nothing else. Two, three or four gates can collaborate for improving scaling, performance, functionality, and flexibility. Since the device operation is governed by 3-D effects, there are complex coupling mechanisms along the longitudinal, lat-eral and vertical directions. A given size effect (length, width, or thickness) is modulated by the other dimensions. All device architectures (planar or vertical double gates, or topologies, gate-all-around and 4-gate transistors) have their merits and drawbacks. The winners will be se-lected with processing feasibility criteria. An amazing horizon is opened to circuit designers looking in the direction of multiple addressable gates. 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