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2180 Fortune Drive, San Jose CA95131, USA (408)944-0800 http://www.micrel.com
- Page 1 - 2013 Micrel Inc.
Micrel KSZ852HL Step-by-Step
Programmers Guide
Micrel KSZ8852HL
Step-by-Step
Programmers Guide
Version 1.1
October 31, 2013
Proprietary Information
2180 Fortune Drive, San Jose CA95131, USA (408)944-0800 http://www.micrel.com
- Page 2 - 2013 Micrel Inc.
Micrel KSZ852HL Step-by-Step
Programmers Guide
Revision History
Revision Date Summary of Changes 1.0 10/14/2013 First release.
1.1 10/31/2013 Correct section 2, step 9; section 4.1, step 9; section 4.2, step 10 and 17 to
address when device is in big-endian mode.
Add section 5.1.2 to describe register and QMU access when the device is in
big-endian mode.
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- Page 3 - 2013 Micrel Inc.
Micrel KSZ852HL Step-by-Step
Programmers Guide
Table of Contents
1 Overview ................................................................................................................................. 4 2 KSZ8852HL Initialization Steps............................................................................................. 5
2.1 KSZ8852HL Additional Receive Initialization Steps ...................................................... 7 3 KSZ8852HL Transmit Steps................................................................................................... 8
4 KSZ8852HL Receive Steps .................................................................................................. 10 4.1 Receive Single Frame per DMA .................................................................................... 10 4.2 Receive Multiple Frames per DMA ............................................................................... 13
5 KSZ8852HL Host Bus Interface (BIU) ................................................................................ 16 5.1 16-Bit Data Bus .............................................................................................................. 16
5.1.1 Little-Endian Mode ................................................................................................. 17
5.1.1.1 Register Access................................................................................................ 18 5.1.1.2 QMU Access.................................................................................................... 23
5.1.2 Big-Endian Mode .................................................................................................... 24
5.1.2.1 Register Access................................................................................................ 25 5.1.2.2 QMU Access.................................................................................................... 30
5.1.2.3 Special Notices for Big-Endian Mode ............................................................. 31 5.2 8-Bit Data Bus ................................................................................................................ 32
5.2.1 Register Access ....................................................................................................... 33
5.2.1.1 Read From Registers ................................................................................... 33 5.2.1.2 Write To Registers ........................................................................................ 36
5.2.2 QMU Access ........................................................................................................... 38
5.2.2.1 Read From RXQ ........................................................................................... 38 5.2.2.2 Write To TXQ ................................................................................................. 39
5.2.3 Special Notices for 8-Bit Data Bus ......................................................................... 39
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2180 Fortune Drive, San Jose CA95131, USA (408)944-0800 http://www.micrel.com
- Page 4 - 2013 Micrel Inc.
Micrel KSZ852HL Step-by-Step
Programmers Guide
1 Overview
This document covers KSZ8852HL-16Bit, and KSZ8852HL-8Bit.
Throughout this document, KSZ8852 refers to either KSZ8852HL-16Bit or KSZ8852HL-
8Bit.
This document only provides step-by-step procedures detailing the registers and values
need to be initialized, steps to transmit frame data to the device, to receive frame data from
the device for the KSZ8852 series Two-port Ethernet Switch.
Please refer to KSZ8852HL datasheet for detail register information.
In order to set a bit in a register, such as step 1 in Initialization, read the register first and
modify the target bit only and write it back.
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Micrel KSZ852HL Step-by-Step
Programmers Guide
2 KSZ8852HL Initialization Steps
Steps
Sequence
Read\write Register Name[bit] Value Description
1 Write GRR [0]
0ffset 0x126
bit 0
1
wait 10ms
0
Global Soft Reset by write 1 to reset, wait 100ms, write 0
to normal mode.
2 Read CIDER [15-0]
0ffset 0x0
0x8431 Read the device chip ID, make sure it is correct ID (0x843x
for KSZ8852HL); otherwise there are some errors on the host
bus interface.
3 Write SGCR1 [8]
0ffset 0x002
bit 8
1 Enable more aggressive back off algorithm in half-duplex
mode to enhance performance.
4 Write SGCR2 [3]
0ffset 0x004
bit 3
1 Enable Switch dont drop packets when 16 or more collisions
occur in half-duplex mode.
5 Write P1CR2 [12]
0ffset 0x6E
bit 12
0 Disable Force Flow Control. The flow control is enabled
based on auto-negotiation result.
6 Write P1CR4 [5]
0ffset 0x07E
bit 5
1 Force Port 1 in half duplex if auto-nego fails when link
partner doesnt support auto-nego (like HUB device).
7 Write P1CR4 [13]
0ffset 0x07E
bit 13
1 Restart Port 1 auto-Negotiation.
8 Write P2CR2 [12]
0ffset 0x86
bit 12
0 Disable Force Flow Control. The flow control is enabled
base on auto-nego result.
9 Write P2CR4 [5]
0ffset 0x096
bit 5
1 Force Port 2 in half duplex if auto-nego is fail when link
partner doesnt support auto-nego (like HUB device).
10 Write P2CR4 [13]
0ffset 0x096
bit 13
1 Restart Port 2 auto-Negotiation.
11 Write MARL[15-0]
0ffset 0x110
0x89AB Write QMU MAC address (low). MAC address is generally
expressed in the form of 01:23:45:67:89:AB. (we use this
MAC as an example).
12 Write MARM[15-0]
0ffset 0x112
0x4567 Write QMU MAC address (Medium). MAC address is
generally expressed in the form of 01:23:45:67:89:AB. (we
use this MAC as an example).
13 Write MARH[15-0]
0ffset 0x114
0x0123 Write QMU MAC address (High). MAC address is generally
expressed in the form of 01:23:45:67:89:AB. (we use this
MAC as an example).
14 Write MARL[15-0]
0ffset 0x10
0x89AB Write Switch MAC address (low) for sending PAUSE frame.
MAC address is generally expressed in the form of
01:23:45:67:89:AB. (we use this MAC as an example).
15 Write MARM[15-0]
0ffset 0x12
0x4567 Write Switch MAC address (Medium) for sending PAUSE
frame. MAC address is generally expressed in the form of
01:23:45:67:89:AB. (we use this MAC as an example).
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- Page 6 - 2013 Micrel Inc.
Micrel KSZ852HL Step-by-Step
Programmers Guide
16 Write MARH[15-0]
0ffset 0x14
0x0123 Write Switch MAC address (High) for sending PAUSE
frame. MAC address is generally expressed in the form of
01:23:45:67:89:AB. (we use this MAC as an example).
17 Write TXFDPR [14]
0ffset 0x184
1 Enable QMU Transmit Frame Data Pointer Auto
Increment.
18 Write TXCR [15-0]
0ffset 0x170
0x00EE Enable QMU Transmit flow control / Transmit padding /
Transmit CRC, and IP/TCP/UDP checksum generation.
19 Write RXFDPR[14]
0ffset 0x186
1 Enable QMU Receive Frame Data Pointer Auto
Increment.
20 Write RXFCTR[15-0]
0ffset 0x19C
0x0001 Configure Receive Frame Threshold for one frame.
21 Write RXCR1 [15-0]
0ffset 0x174
0x7CE0 Enable QMU Receive flow control / Receive all
broadcast frames /Receive unicast frames, and
IP/TCP/UDP checksum verification etc.
22 Write RXCR2 [15-0]
0ffset 0x176
0x0115 Enable QMU Receive UDP Lite frame checksum
verification/generation, IPv4/IPv6 UDP fragment
frame pass, drop the received frame if SA is same as
device MAC address, and QMU Flow Control Pause
Timer.
23 Write RXQCR[15-0]
0ffset 0x182
0x0230 Enable QMU Receive IP Header Two-Byte Offset
/Receive Frame Count Threshold/RXQ Auto-Dequeue
frame.
24 Write ISR [15-0]
0ffset 0x192,
0xFFFF Clear the interrupts status.
25 Write IER [15-0]
0ffset 0x190,
0xE000 Enab
