ANALYSIS OF FULL ADDER FOR POWER EFFICIENT CIRCUIT DESIGN

A Thesis Submitted in Partial Fulfilment of the Requirements

for the Degree of

MASTER OF TECHNOLOGY in

VLSI DESIGN

By

TRAPTI MITTAL (Roll No. 1202708515)

Under the Supervision of Asst. Prof. UMA SHARMA

AJAY KUMAR GARG ENGINEERING COLLEGE

to

Department of Electronics & Communication Engineering

DR. A.P.J. ABDUL KALAM TECHNICAL UNIVERSITY

LUCKNOW, INDIA

December, 2015

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CERTIFICATE

Certified that Trapti Mittal (1202708515) has carried out the research work presented in this thesis entitled ANALYSIS OF FULL ADDER FOR POWER EFFICIENT CIRCUIT DESIGN for the award of Master of Technology from Uttar Pradesh Technical University, Lucknow under my supervision. The thesis embodies results of original work, and studies as are carried out by student herself and the

contents of the thesis do not form the basis for the award of any other degree to the candidate or to anybody else from this or any other University/Institution.

Signature

Asst. Prof. Uma Sharma Deptt. of Electronics & Comm.Engg.

Ajay Kumar Garg Engineering College

Date- ..

Place: Ghaziabad

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ANALYSIS OF THE FULL ADDER FOR THE POWER EFFICIENT CIRCUIT DESIGN

Trapti Mittal

ABSTRACT MOS Current Mode Logic (MCML) has surfaced as a logic style that is

capable of achieving high speeds while consuming a lesser amount of power than the typical CMOS circuits. In this project, an active class of dynamic differential logic family that specifies a self-timing operations and low output logic swing behaviors are monitored and investigated. In return, it reduces total power supplied to it. The basic block is fast enough and consuming low power supply and working on TSMC 180 nm technology that it can lead to the improved and fast results. If it is properly designed, MCML circuits can achieve significant power reduction compared to their CMOS counterparts at lower frequencies.

. An important aspect to be reduced is the power along with Power Delay Product (PDP) for any synchronous or in-tune design. In order to reduce the total Power Delay Product (PDP), delay and power should be simultaneously reduced. In the most of digital circuits, delay is reduced at the cost of increased power and low switching frequency.

This full adder design will not only be compact in terms of transistor units but also be fast enough for the large adders to provide the faster switching within its blocks. This full adder design will speed up the carry part of the circuit so that the next block proceeds faster. To decrease the delay further, the switching frequency must be changed.

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ACKNOWLEDGMENTS

I place on record and warmly acknowledge the continuous encouragement, invaluable supervision, timely suggestions and inspired guidance offered by my guide Asst. Prof. Uma Sharma, Department of Electronics and Communication Engineering, Ajay Kumar Garg Engineering College, Ghaziabad, in bringing this report to a successful completion. Without her wise counsel and able guidance, it would have been impossible for me to complete the thesis in this manner.

I am grateful to Dr. P.K. Chopra, Prof. & Head of the Department of Electronics and Communication Engineering, for permitting us to make use of the facilities available in the department to carry out the thesis successfully.

I also would like to extend my gratitude to Dr R. K. Agarwal, Director of Ajay Kumar Garg engineering College, who provides all the facilities needed for completing the project and with his encouraging words, he motivated us a lot for completing the project. Last but not the least sincere thanks is expressed to all of our friends who have patiently extended all sorts of help for accomplishing this undertaking. Also all those who are directly or indirectly involved in the successful completion of this thesis work.

Trapti Mittal

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TABLE OF CONTENTS

Page No.

Certificate ii

Abstract iii

Acknowledgements iv

List of Tables vii

List of Figures viii

List of Abbreviations x CHAPTER 1. INTRODUCTION 1-14

1.1 1.2 1.3 1.4

INTRODUCTION LITERATURE REVIEW OBJECTIVE REPORT ORGANIZATION

1 5 14 14

CHAPTER 2. DESIGN OF ADDER STRUCTURE 15-21 2.1 2.2 2.3

BACKGROUND ADDER DESIGN RIPPLE CARRY ADDER

15 17 18

2.3.1 Ripple Carry Addition 19 CHAPTER 3. POWER REDUCTION TECHNIQUES 22-32

3.1 3.2

POWER POWER CONSUMPTION COMPONENTS

22 22

3.2.1 Static Power Consumption 23 3.2.2 Dynamic Power Dissipation 25

3.3 DIODE LEAKAGE CURRENT 27 3.4 BIASING CURRENT 27 3.5 SUB THRESHOLD LEAKAGE CURRENT 28 3.6 SHORT CIRCUIT POWER DISSIPATION 29 3.7 INTERNAL POWER 29 3.8 LOW LEAKAGE POWER CIRCUIT TECHNIQUES 29

3.8.1 Leakage Control by Body Biasing 29 3.8.2 Leakage Control by MTCMOS Technique 30 3.8.3 Leakage Control by MVCMOS Technique 31

CHAPTER 4. MOS CURRENT MODE LOGIC 33-41

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4.1 OUTLINE 33 4.2 MCML BASIC OPERATION 34 4.3 MCML ADVANTAGES 35 4.4 MCML DISADVANTAGES 36 4.5 MOSFET MODELS 37

4.5.1 Threshold Voltage 37 4.5.2 DC Power Supply 37

4.6 PERFORMANCE PARAMETER 38 4.6.1 Power Supply Switching Noise 38 4.6.2 Voltage Swing Ratio 38 4.6.3 PMOS Load Transistor Sizes (WRFP, LRFP) 39 4.6.4 NMOS Load Transistor Sizes (WRFN, LRFN) 39

4.7 DYNAMIC MCML 39 CHAPTER 5. SIMULATION RESULTS 42-60

5.1 TOOL USED 42 5.2 INPUT PARAMETERS 42 5.3 RESULTS 43

CHAPTER 6. CONCLUSION & FUTURE WORK 61-62 6.1 6.2

CONCLUSION FUTURE WORK

61 62

REFERENCES 63-65 APPENDICES 66-90 LIST OF PUBLICATION 91 CARRICULAM VITAE 92

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LIST OF TABLES

Page No. Table 1.1 Truth table for the 1 bit full adder 2 Table 5.1 Input parameters for the design 42 Table 5.2 Comparison of various full adder designs at 5 V 51 Table 5.3 Comparison of various full adder designs at 1 V 52 Table 5.4 Comparison of delay of sum bits of ripple carry adder

designs (for 5 V) 59

Table 5.5 Comparison of delay of sum bits of ripple carry adder designs (for 1V)

60

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LIST OF FIGURES

Fig No. Page No. Fig 1.1 Generalized block diagram of full adder 1 Fig 1.2 Schematic Design of Generalized Full Adder 4 Fig 2.1 An example of ripple carry addition 19 Fig 2.2 4-bit Ripple Carry Adder 20 Fig 3.1 Static Power Consumption for The Inverter 24 Fig 3.2 Leakage current in the logic gate 28 Fig 3.3 Generalized schematic of MTCMOS technique 30 Fig 3.4 MVCMOS Technique 32 Fig 4.1 Basic MCML operation 34 Fig 4.2 Dynamic CML style 40 Fig 5.1 Schematic of the Mirror CMOS Full Adder 43 Fig 5.2 Input Voltage Waveform for Mirror CMOS Full Adder 44 Fig 5.3 Output Voltage Waveform for Mirror CMOS Full Adder 45 Fig 5.4 Schematic of the Proposed Full Adder 46 Fig 5.5 Input Voltage Waveform for proposed Full Adder for 5V 47 Fig 5.6 Output Voltage Waveform for proposed Full Adder for 5 V 47 Fig 5.7 Input Voltage Waveform for proposed Full Adder for 1V 48 Fig 5.8 Output Voltage Waveform for proposed Full Adder for 1V 48 Fig 5.9 Circuit Testing Arrangement of Full Adder 50 Fig 5.10 Generalized setup for 4-bit RCA Adder 53 Fig.5.11 Waveform for the Mirror CMOS RCA Circuit for S0, S1, S2 Bits 54 Fig.5.12 Waveform for the Mirror CMOS RCA Circuit for S3, Cout Bits for

5V 54

Fig.5.13 Waveform for the Proposed CMOS RCA Circuit for S0, S1, S2 Bits for 5V

55

Fig.5.14 Waveform for the Proposed CMOS RCA Circuit for S3, Cout Bits for 1V

56

Fig.5.15 Waveform for the Proposed CMOS RCA Circuit for S0, S1, S2 Bits for 1V

57

Fig.5.16 Waveform for the Proposed CMOS RCA Circuit for S3, Cout Bits for 1V

58

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LIST OF ABBRIVIATIONS

CLRCL Complementary and Level Restoring Carry Logic CPL Complimentary Pass Transistor Logic DCVSL Differential Current Voltage Source Logic DDCVSL Dynamic Differential Current Voltage Source Logic EDP Energy Delay Product GDI Gate Diffusion Input HS-Domino High Speed Domino LSCML Low Swing Current Mode Logic MCML MOS Current Mode Logic MOSCAP Metal Oxide Semiconductor Capacitor NTC Near Threshold Circuit PDP Power Delay Product PG Power Gating SERF Sense Energy Recovery Full Adder SRMCML Single-Rail MOS Current Mode Logic SRPL-BBL Swing Restored Pass Transistor Logic and Branch Based

Logic SOI Silicon on Insulator ULPD Ultra Low Power Diode

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CHAPTER 1

INTRODUCTION

1.1 INTRODUCTION

Addition is the most frequently and extensively used operation in the arithmetic procession for any number of digitalized signal processing units and microprocessors and embedded systems and other such systems. It often works as a speed limiting element for the larger and complicated blocks where the pace of the operation serves as a constraint. The full adders are an arithmetic unit which adds three 1-bits at a time and gives unit-bit result and generates the result as sum and carry output. These low power designs affect the performance in requisites of speed of operation, time taken in completing the operation and also the complete power delay product (PDP) of the logical circuit structure [1].

Fig 1.1: Generalized block diagram of full adder

Here, Fig 1.1 shows the generalized block diagram of the 1-bit full adder. Here A, B, C is the inputs of the block called full adder in the left hand side and SUM and CARRY are the output produced out of the block in the right hand side. Generally a block is given in the figure is designed and implemented in number of ways and according to the application and requirement of operation speed.

FULL ADDER A

B

C

SUM

CARRY

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Table 1.1 Truth table for the 1 bit full adder

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Table 1.1 above shows the truth table for the 1-bit full adder operation. Here we can see that by adding three 1-bits at a time, we get the result in terms of sum and carry at 000, the sum and carry output shows 0 and at 111, the sum and carry shows 1 output.

For various logic units and multiplier designs, it is regarded as a prime element for the arithmetic operations for various logic units and multiplier designs. In todays time, there is a requirement of the circuit design that can work with low power. These circuits consume less power and generate the desired result with the less power dissipation. These low power designs affect the performance in terms of speed of operation, time taken in completing the operation and also the complete power delay product (PDP) of the circuit. Low power designs are beneficial in terms of delay, speed and power delay product, as the power consumption is low. These are needed for speeding up the arithmetic logic units (ALU) and other like applications. It oftenly works as a speed limiting element for the large blocks or the complicated blocks where the speed of the operation serves as a constraint. Todays power management process of advanced CMOS technology process drives the need to consider the satisfactory scale driven fundamental material limitations with almost same applications and other

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products and designs for the evaluation requirements in the low power VLSI design industry [2].

Suitable power design approach of VLSI circuits has always been considered as a careful identification of a critical technological need of present day and also the advanced years from now on. During the last few years, the demand of portable electronics products has been increased up to the sky heights and increasing day by day for its low power benefit by the consumers. So, the need of designing such products has also increased. And in regarding to this factor, many innovative designs has been produced and is producing for fundamental logic designs using the approaches such as pass transistors and transmission gates. They are discussed and approached in the literature recently and is using now and then [3].

For all the portable information systems and other system applications, power dissipation is a constricting factor and a top priority issue of discussion for VLSI circuit design. Power dissipation vastly affects the weight, size of the system, effective cost of design and the battery life as the portable systems rum over a battery so the weight, size and cost should be such as which can be bearded. To have such a cost effective design, the VLSI engineer faces a lot of challenge to find and apply the circuit techniques effectively in order to corporate the primary requirements for the easy carrying devices. The circuit designing method should be chosen that can balance the need for performance critical unit with those of power dissipation.

.

Due to the less power consumption factor, ultra low power circuit designs become the appropriate candidates for portable units. With the intention of realizing these circuit designs, various techniques already have been introduced and invented that provides all the required features. The technique should be selected very carefully as the portable devices are more power sensitive. Therefore, for designing and drawing any complex structure or system, its fundamental building block should be fast enough to generate their results in the mean time. These features affect the overall performance and output of the proposed design and following the large complex design [4].

The very low power design of any circuit consumes less energy which means we can input a very low voltage suggestively less then 1V these days, but at the cost of increment in the leakage currents such as dynamic current, sub-threshold leakage current, gate induced bulk leakage current and drain induced bulk leakage current etc. Due to the low input voltage, power dissipation can also be increased. Various designing methods to reduce the standby leakage currents of the chip have become a boon for the VLSI designers. It enables the designer to reduce the leakage current, heat generation

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and power dissipation. These techniques also enable the continued transistor scaling by relaxing the gate and sub threshold leakage current and planer device structural limitations.

The working design of any circuit relies upon the various factors and could be designed using various aspects. They are implemented at various levels such as, architectural level, logic level, transistor level and switching level. Each and every level of design has own advantages and their own challenges too [5].

Fig 1.2: Schematic Design of Generalized Full Adder

Fig 1.2 illustrates the schematic of the full adder structure one of the simplest kind. This transistor level full adder device has been realized using 28 MOS transistors. The above full adder realization has been altered to have the more improved design as per the needs and features. These alterations and modifications are based upon transistor size, speed, time to process the operation, technology used, W/L ratio, power supply reduction, delay reduction, leakage current magnitude, area requirement and different categories of power dissipation, scaling of transistor [6].

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During the designing of an adder we have to compose two choices in regard to different design abstraction levels. One is responsible for the adders architecture implemented with the one-bit full adder as a building block. The other choice defines the unambiguous design style at transistor level to execute the one-bit full adder [7].

While deciding on the circuit technique for designing, one has to make sure of the number of transistor used in the proposed designing. In this thesis project, a new design is built by reducing the transistor count from the original design of the referred paper. In the referred paper, the design consists of 36 transistors. So, in order to increase the efficiency, we reduced the transistor count in between 20-25 transistors. The new design, proposed here will be based upon the MOS Current Mode Logic (MCML) style which is a power efficient concept. In the design approach, a current source will be used as the power supply option rather than a voltage source and the current mirrors for each and every stage that will be connected to each other in successive procession further, so that delay and power can be further reduced. Based upon the given power supply using the current source in any digital circuit helps in reducing the power dissipate, delay and power delay product. It helps in reducing the noise level and stabilizes the voltage swing. With the static CMOS the only real parameter that could be changed is the size of the design has advantages, it also has few drawbacks that will have to overcome such as, the supply current of a CML gate is independent of the working frequency; there will be stationary power dissipation that generates during the condition when both of the transistors are in ON state. But at the upper operating frequencies, less energy is dispersed away that the static CMOS design approach. This condition however leads to a reduction in power delivery and current. Scaling down the following parameters will lead to a far worse problem of leakage current, which damages the circuit [23].

1.2 LITERATURE REVIEW

With the aim of understanding, the designing and approaches of full adder, we have to study and elaborate the various methods to design the new one. By review the various papers and thesis and other work by the author, we can understand the problem of power, delay and power delay product (PDP). Under this subdivision, we will have the literature (prose) review of different papers.

R. Zimmermann et.al, 1997 [1] compared between CPL and CMOS logic style to show their advantages. The comparison had been drawn in between these two of the logic styles with respect to speed efficiency, area utilization, power dissipated and power delay product. Different full adder circuit designs, based on these two logic styles were compared and elaborated. CMOS style had shown the robustness with respect to voltage scaling, ease of use, switching capacitance reduction, supply voltage reduction,

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switching activity reduction, short circuit current reduction. Here, the CPL logic style worked 20% faster than the CMOS logic style, as the former drew low power while operating the full adder circuit designs. The comparison had been carried out on HSPICE, 3.3V & 1.5V, 20 MHz.

H. Lee et.al, 1997 [2] had realized a full adder by combining XOR gates and Double Pass Transistor Logic. The objective to design such type of full adder was to achieve the features such as low power dissipation, low supply voltage, and full voltage swing. This 18 Transistors design which eliminated the problem of threshold voltage drop and higher rate of power consumption, also reduced the problem of static short circuit current. To eliminate this problem another high performance 23-T full adder that uses a level restoration technique was proposed. The simulation was carried out on HSPICE 0.4 m CMOS process at Vdd=2V.

Ahmed M. Shams et.al, 2000 [3] proposed a 16-T full adder using 4-T XOR & XNOR gates using pass transistor logic. It has offered high speed & lower power consumption, reduction in transistor count and delay capacitances. The previous 14-T full adder had shown the glitch problem due to which inverter connected to it, so in new design XNOR circuit was connected to eliminate the problem. The new design balanced the delay of generating intermediate stages which led glitches. It eliminated the short circuit power component.

D. Radhakrishnan et.al, 2001 [4] realized a new 14 transistors 1-bit full adder cell that could be operated on low voltage power supply. A new combined XOR and XNOR circuit was constructed using 6 transistors that generate the output simultaneously. This XOR and XNOR circuit was fully compensated for threshold voltage drop. This XOR-XNOR would work properly if its supply voltage was scaled down and not to allow to fall below 2Vtp. This circuit had been provided the full voltage swing and non-zero static current components. The new 14T full adder had few following advantages. For this design, the width to length ratio was very important, as they would ensure the role of driving capability of the transistors. To serve the purpose, several simulations were run and evaluated to fix width to length ratio. For NMOS, W/L ratio was 0.8 m/0.35 m and for PMOS, 3.5 m/0.35 m, except for the feedback NMOS and PMOS. They were set to 0.5 m/0.35 m and 1.8 m/0.35 m, respectively.

A. T. Schwarzbacher et.al, 2002 [5] had compared seven types of adder structures. As every adder structures was designed at different level and had different implementation techniques and technologies. All structures were implemented using the VHDL hardware description language. Designs were synthesized and carried out into

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ES2 ECDP 0.7 m CMOS technology using Synopsys Design Controller. The parameters that evaluated were area requirement, active capacitance, operating frequency. The area requirement for Carry Look Adder was growing faster with respect to its bit size. Active capacitance was directly proportional to power dissipated and depended upon physical node capacitance and switching activity. For being the first fastest operational adder, maximum operating frequency was required by CCA-2.

Hung Tien Bui, et.al, 2002 [6] proposed an approach and method of designing a large sum of 41 new full adder cells consisted of 10 transistors for each. These full adder cells were built using the new kind of XOR and XNOR gates, consisting of 4 transistors for each module. The authors of the following paper had run the exhaustive simulation for all the 41 full adder cells for different input patterns, different operating frequencies and load capacitances. This paper had the drawback of threshold voltage loss due to the consumption of less power supply. Here each input pattern was simulated using the operating frequencies ranging from 50 KHz to 200 MHz and with that load capacitance of 0.3 pF, 0.5 pF and 0.02 pF was taken. The transistors were scaled with length of 0.6 m and a width of 2.4 m, having a power supply of 3.3V. The netlist of the adder was extracted and simulated using HSPICE over an Ultra SPARC 2 machine.

Massimo Alioto et.al, 2002 [7] analyzed and compared the different type of topologies of one-bit full adders. These full adders would be elaborated on the basis of power, delay and the power delay product (PDP). The comparison had been executed with two classes of circuits, the former one was achieved by using the minimum size transistor to minimize the power consumption, and the latter one was carried out with the optimized dimensions of transistors in order to reduce the power delay product. They were not only simulated for its schematic but to evaluate the area requirement, its layout was also designed. The simulations were carried out using the specific Cadence environment with 0.35 m process, Vdd = 3.3V, and W/L=1 m/0.3 m.

Yingtao Jiang et.al, 2004 [8] had realized low power multiplexer based 12T full adder called as MBA-12T. For building the following adder, six indistinguishable multiplexers circuits were used, each multiplexer circuit is realized using two transistors. This new full adder was designed with the objective of maximum speed, attenuation in short current power consumption. The full adder was compared with conventional CMOS transistor and four other low power full adder designs. Simulation had been run at different frequencies ranging from 10 MHz to 200 MHz and capacitances ranging from 500 fF to 0.97 fF. The MBA 12-T consumed less power than the conventional one and saves 23% more power over 10-T transistors and also 64% faster than them. The simulation was carried out using HSPICE with TSMC 0.35 m CMOS technology process with V=3.3V.

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C. H. Chang et.al, 2005 [9] had presented the hybrid low adder design that can be operated at lower power supplies, had less area requirements and time to perform the operation. It could easily be used for pre dictate the tree structured arithmetic circuits. The new XOR and XNOR circuit was formed to reduce the problem of switching delay problem. The hybrid full adder segregates in 3 modules. The first module was made of 6-T XOR-XNOR gates, using a level restoration technique. The middle part was responsible of generating the sum part and the last part generated the carry part, each consisted of 6 and 10 transistors. The simulation was carried out using HSPICE TSMC 0.18 m CMOS technology process with the supply voltage ranging from (0.8V to 2.4V).

S. Goel et.al, 2006 [10] has designed a 1-bit full adder hybrid CMOS design using a hybrid logic style. The objective of such design was to attain a good driving capability, noise robustness and low energy operations for deep sub micrometer region. It was built using XOR and XNOR structure that generated full swing output simultaneously and registered the improvement of 5% to 37% in terms of PDP. The output stage had shown good driving capability in cascading structure and showed 40% reduction. The 4 bits and 8 bits carry save adders were also built, using the same design and evaluated for its area requirements. The simulation was carried out using 0.18 m TSMC HSPICE, MAGIC layout editor 7.1, Fr = 50 Hz, Vdd=1.8V.

D. Levacq et.al, 2007 [11] proposed a 7-T SRAM storage cell based on the permutation of two reverse biased CMOS based diodes. This new storage cell showed ultra low leakage current and a negative impedance characteristic in reverse bias mode. The diodes that were used here, called as ultra low power diodes (ULPD) in the SOI (Silicon on Insulator) technology. In the forward biasing, ULPD worked as the conventional standard diode. In the reverse biasing, ULPD showed the low leakage current process. This new cell was used to form a 2561 bit SRAM column to show the ultra low leakage current. The simulation was carried out using ELDO simulator 0.13 m SOI technology using ST BSIM3SOI models.

Jin Fa Lin et.al, 2007 [12] has proposed a 10-T 1-bit full adder design called as CLRCL (Complementary and Level Restoring Carry Logic). This design was energy efficient uses less transistor count and gave high performance and consumed less power The design was constructed using 2-XNOR gates (consists of 2- 2:1MUX and 2-INV) and a MUX. The XOR gate constructed here was inverter buffered design which was used to eliminate the problem of threshold voltage drop of pass transistor. The simulation was accomplished by HSPICE platform based on TSMC 2P4M 0.35 m process models. It ensured that the suggestive design has lowest acting Vdd and highest

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working operating frequency. And as the word length kept increasing, the efficiency of adder had also been increased.

Flavio Carbognani et.al, 2008 [13] presented a Wallace tree multiplier architecture by combining TG (Transmission Gate) and CMOS called as TG-MULT. It has shown better leakage reduction, process variation & voltage scaling. It has suppressed the glitches via R-C low pass filtering, while preserving unaltered driving capabilities. As it showed less glitch, took less power and occupied less area. The proposed design illustrated 30% more power saving in comparison to other two multiplier designs. The simulation process was carried out on Spectre by Cadence in 0.18 m CMOS technology at Vdd=0.75V.

Walid Ibrahim et.al, 2008 [14] analyzed the three different full adder design, approaches the different majority gate methods. The reliability of these three different majority gates design, was compared with the standard XOR-based full adder. The simulation was carried using PTM modules and monte-carlo simulation for minority functions.

Farshad Moradi et.al, 2008 [15] proposed a new full adder (FA) circuit synthesized and minimized for the ultra low power operation. The circuit was designed using modified XOR-XNOR circuit which required total of 16 transistors for the operation. As the count of transistors were increased so the area requirement also increased in the same amount, the simulations were achieved by using 65 nm bulk CMOS process for the voltage ranging from 0.1V to 0.25V and the operating frequencies were ranging from 1 KHz to 20 MHz.

Mi Chang Chang et.al, 2008 [16] evaluated the matters associated with transistor scaling or resizing of dimensions and co-optimization for power management circuit-design methods for active and leakage power control modes. Circuit techniques to contain system standby leakage and active power have become the fundamental enabler of continued CMOS transistor scaling by conciliating scaling driven fundamental material limitations with product and application evolution requirements.

Farshad Moradi et.al, 2009 [17] designed low power full adder topologies based on SERF (sense energy recovery full adder) and GDI (gate diffusion input) technique. SERF had the advantage of using less number of transistor count. The GDI based full adder worked better then the SERF based adders but with some limitations. For operating voltage 0.5V, the SERF full adder showed the satisfactory output results.

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The simulation was carried out using 65 nm technology, operating frequencies varies from 100 KHz to 10 MHz.

Yi WEI et.al, 2011 [18] proposed an 8-T 1-bit full adder cell, which combined three MUX and an inverter. The objective was to reduce the transistor count and power consumption. This full adder design had realized the boolean expression. Here the inverter had shown few advantages such as it sped up the carry propagation as a buffer along the carry chain, provides complementary signals needed for the generation of sum. The inverter has improved the output voltage swing as a level restorer circuit. For the simulation process, various frequency ranges from 100 MHz to 500 MHz were taken and load capacitance of 100 fF was taken. Simulation was done using TSMC 180 nm HSPICE, at Vdd=1.8V.

V. V. Shubin et.al, 2011 [19] proposed a new mirror CMOS circuit implementation. It demonstrated zero static power consumption and less voltage variations at internal nodes which mean no voltage recovery was required. This proposed adder provided the better speed operation at the carry part. It provided a suitable transition for building multi bit adders. It also reduced the maximum delay through n-bit RCA. This full adder design worked better for the RCA, where the bits n was more than 3. The creation of delay for each and every logic gate fluctuated with its own output parasitic capacitances and total channel resistance between each output node and the power or ground line in pull up/pull down network. The simulation was carried out with PSPICE software from ORCAD 9.2 (Cadence Design System) on 3rd level model, 3 m CMOS process, Vdd=5V.

Sohan Purohit et.al, 2012 [20] suggested the 3 new 1-bit full adder designs and analyzed their design and characterization. These all full adders were synthesized and evaluated by IBM 90 nm process technology. These adder circuits were examined with the power supply of 1.2V and operating frequency of 1 GHz. Using these full adders, 32-bit ripple carry adder and 84 multiplier were also built to observe the effect of sum and carry propagation bit delays on the overall functionality consumed power. The Monte Carlo analysis was repeated with varied supply voltages ranging from 1.2V down to 0.9V to estimate changeability under scaled voltage operating conditions.

D. V. Morozov et.al, 2013 [21] proposed a single bit CMOS full adder cell to increase the performance and reliability of the circuit. This proposed design had been consisted of total of 24 transistors. The proposed circuit for better evaluation is considered. Here, first 12 transistors consisted of 6 PMOS and 6 NMOS used for generating the carry part stage. The formation circuit of the sum signal was to be implemented based on transistors T13T24. The simulation was carried on Virtuoso

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IC5.1.41 platform by Cadence Design Systems 0.18 m CMOS technology, with the power supply of 1.8V.

Hamid Reza Naghizadeh et.al, 2013 [22] proposed two 1-bit full adder cells using hybrid design techniques. The first full adder was designed by adjoining the Swing Restored Pass-transistor Logic and Branch-Based Logic, called as SRPL-BBL cell and the second full adder had been realized by merging the Gate Diffusion Input technique and Majority function which was also called as GDI-Majority cell. Simulation results were executed by HSPICE in TSMC 0.13 m CMOS process with the power supply of 1.2V and operating frequency of 12.5 MHz, at the room temperature of 25C.

Yavuz Delican et.al, 2011 [23] presented a high performance 8x8 bit multiplexer based multiplier using MOS Current Mode Logic (MCML). In this paper, logic gates based on MCML method was designed, which consisted of 2:1 MUX, NAND/AND logics and full adder were planned and optimized further for evaluation of low power and high speed operation and then examined for two different supply currents. An 8-bit multiplier had been formed using the library which was tested further with two different current magnitudes. Here the transistor sizes of NMOS and PMOS should be chosen such as that the dc gain was of the magnitude of 2. This MCML full adder consisted of 24 transistors and sum of 76 full adders were used in the 8-bit multiplier design. The simulation had been run on HSPICE, with UMC 0.18 m CMOS process technology and the power supply ranging from 1V to 8V.

Subodh Wairya et.al, 2011 [24] proposed a high speed 1-bit full adder circuit based on hybrid mode logic family. The goal of this was to design a 1-bit adder circuit using the current mode logic. Here, in this paper, the authors had also evaluated a high speed hybrid majority based full adder, which used MOS capacitors (MOSCAP) in its design. Dynamic CMOS approach had more advantages than the static in terms of delay, area required and testability of the circuit. The design was simulated and run by Virtuoso Schematic Composer on UMC 0.18 m bulk CMOS process models at 1.8V. Simulation had been run on Spectre S.

Hong Li et.al, 2012 [25] proposed a single rail model of MCML circuits. The design approach of the fundamental single rail MOS Current Mode Logic (SRMCML) circuits was exhibited. All circuits were simulated with HSPICE model with the SMIC 130 nm CMOS process model technology. The power dissipations of the vital SRMCML cells were compared with the conventional dual rail MCML circuit designs. The power dissipation of the proposed SDMCML circuits was nearly the same

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as the conventional dual rail logic design. The operating frequency of this experiment varied from 100 MHz to 1 GHz.

Yangbo Wu et.al, 2013 [26] proposed a 1-bit full adder based on the power gating technique in order to decrease the standby power of the near threshold region MCML. In near threshold MCML designs, the transistor pulled down the bias voltage of the current source to zero reduce the static power. The drawback of MCML circuit was its standby power. A 10 bit counter was also formed using the MCML technique and both showed the standby power of 1 nW and 3 nW. The simulation was run on HSPICE with 45 nm CMOS process technology using the NCSU PTM models with the supply voltage of 0.7V and bias current of 10 A.

Zhenguo Vincent Chia et.al, 2013 [27] designed a high speed analog to digital converter based upon the CMOS current mode logic (MCML). The MCML circuit did not need a voltage swing from rail to rail lines as for the typical CMOS was required against its CMOS version. The MCML showed the benefit of propagation delay from one stage to another stage. The CML circuits were frequency independent. For achieving high resolution, a high speed coder-decoder was also used in forming an analog to digital converter. Here the simulation results were observed and showed that MCML could operate within the voltage range of 1.08V to 1.3V with the working temperature varies from -40C to +120C.

Alexander Shapiro et.al, 2014 [28] presented a work on the basis of the combination of the NTC (Near Threshold Circuit) technology with MOS current mode logic (MCML), here a circuit was formed by adjoining MCML with NTC. Due to this implementation constant power consumption of MCML was reduced to some level, which can tolerate the leakage power levels in some of the applications. The simulation was carried out with 14 nm FinFET process. With this full adder, a 32-bit Kogge Stone full adder was chosen to form the feasibility analysis. The following circuit also showed the lower noise levels compared to typical CMOS. This circuit combination provided a balanced circuit methodology. The outcome of the above analysis and design showed that coupling of near threshold circuit and MCML was efficient for higher operating frequencies and activity factors.

Osman Bakri Musa Abdulkarim et.al, 2006 [29] presented a simple analysis of propagation delay models based upon the MCML circuits. This thesis work showed the mathematical analysis for MCML based circuit library for their delay model. It had also evaluated the condition for the circuit to work in DC and AC operational modes. The expressions were developed for the delay models and verified using various parameters. A 4-bit ripple carry adder and an 8-bit decoder were also designed which

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was optimized using the less complex MCML circuit. The proposed model here reduced the complexity of the MCML delay model effectively.

Ilham Hassoune et.al, 2006 [30] analyzed a novel category of active differential logic family. It featured a low output voltage swing and self timing operation. Even the discrepancy and active nature of low swing current mode logic (LSCML) style brought the benefits in reduction of power consumption deviation, which in return proves the LSCML logic style a potential implementation option against the power analysis of other. This technique was the secure way of building the encryption devices. Here a new hybrid full adder structure had performed which was built using pass transistors. Also an 8-bit ripple carry adder was also implemented using the hybrid adder and compared with the static version and shows the reduction and better power delay product.

E. Pattanaik et.al, 2013 [31] proposed an 8-bit multiplier circuit, designed using the MCML logic. Here multiplier architecture was drawn and analyzed with respect to high speed applications, the 88 bit multiplier consisted of inverter, AND gates, XOR gate, half adder and a full adder MCML circuits. This multiplier was then simulated using Cadence design tool on Virtuoso platform, on 0.6 m standard CMOS double metal double poly process. These circuits had been operated with the working frequency of 1.31 GHz and had the power consumption values vary from 4.3 mW to 18.6 mW.

Mohamad W. Alam et.al, 2000 [32] showed the study of five categories of logic family. These logic families were analyzed for their scalability feature and their potential for creating the future technology more effective and reliable. The technology scaling effected the performance of any circuit design based upon the power, speed and power delay product. Here also a new logic family was created, called as High speed Domino (HS-Domino) and combined the features of low power supply speed and noise resistance of CML circuits with the design simplicity and lower standby current. The new logic family showed the improvement in delay by 73% and in power by 7% against the typical CMOS style. A typical 16-bit Carry Look Full Adder was also designed and simulated and fabricated using 0.6 m CMOS technology.

Uma Sharma et.al, 2014 [33] showed the analysis of the various full adder topologies. These topologies were discussed and tested by the authors. The following paper shows the review of the given topologies. By reviewing the 4 topologies, the best full adder was ULPFA which is simulated and fabricated using 0.13 m PD-SOI CMOS

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technology with the power supply of 1.2V. It gave the drastic reduction the power consumption and time to perform the operation and power delay product.

Trapti Mittal et.al, 2015 [34] showed the new full adder design based on MCML method, which gives more reliable results than CMOS technology. The proposed adder design is the compared with other design approaches also a 4-bit RCA is also designed using the same full adder circuit. On comparing the results of sum part, it is concluded that MCML based design shows more efficient results. The simulation is carried out using Tanner EDA Tool V 14.0.

1.3 OBJECTIVE

The full adder design is crucial for the complex and large operations as it serves as a basic building block. After having review the literature of several journals, thesis and books, for setting the parameter and drawing technique, three main parameters are decided to achieve through this review that shows the affect on the performance of the digital design, is power, speed and power delay product (PDP). Here, in this thesis, for creating a full adder, MOS Current Mode Logic (MCML) technique will be used [8, 9]. The objectives that are need to be achieved:

(a) To design a 1-bit full adder. (b) To improve the power consumption of the overall circuit. (c) To reduce the delay of the circuit. (d) To reduce the PDP. (e) To implement the proposed full adder in the application such as Ripple Carry Adder (RCA).

1.4 REPORT ORGANIZATION

In chapter 1, literature survey of various papers and research work has been reviewed and objectives are identified. In chapter 2, adder structures are defined, where, ripple carry adder is discussed. The discussion starts from its background to its working. The chapter 3 explains the power techniques and different type of power induced in the design. The chapter 4 gives the review of the technique used, MOS Current Mode Logic (MCML). While chapter 5 shows all the results that are extracted from simulations on various full adder design. And last but not the least chapter 6, discusses the conclusion and future work.

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CHAPTER 2

DESIGN OF ADDER STRUCTURE

2.1 BACKGROUND

For evaluating any digital circuit and to know about the circuit proficiency, three factors are very important such as power, delay and power delay product (PDP). These factors show the proper working evaluation for any digital circuit and helps in deciding the usefulness. The other deciding factors are transistor count, technique used for designing the circuit, logical expression, gain and robustness [11].

The objective of achieving efficiently powered full adder can be acquired by lowering the supply voltage. Since, we not only desire a low power feature but also the high speed recognition as property, so we work on higher operating frequencies. To carry out the work on higher frequencies, not only low power property but high speed is also desirable. It helps in achieving the efficient speed operation which helps in speedy and timely delivery of the results. So the lesser delay will also be achieved. This in turn helps in retrieving a power delay product, shows the efficiency of any electronic circuit.

For designing a proposed full adder, the studies of the previous full adder designs are needed to be understood and find out about their advantages and disadvantages. Since the full adder is developed, various kind of full adder design has come in light. There are number of authors exists that worked on several design and is working on them continuously. This is a topic of vast discussion, as there are so many experiments have taken place already [10].

The full adders are designed in terms of power, speed, power speed product and number of transistors used. In order to achieve this goal, transistor size can be scaled down. The channel length and width should be selected in such a way that helps in reducing the leakage current, dynamic current and gate leakage current. The selection of transistor size affects the channel density, power density, and process variation. The

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transistor sizing can be done to the boundary limit after which the leakage current and drastic changes in the circuit behavior can occur.

CMOS VLSI technology has recognized as the major breakthrough in technology in the VLSI industry. Almost of all the circuit and devices are built and designed using the CMOS design style. The VLSI designers have invented so many categories and types of logic styles, all using the CMOS technology. The logic style such as pass transistor logic family, dynamic logic family, and current mode logic based family clan etc. The bulk CMOS technology has the various advantage of working at very low power inputs and higher speed operations and shows the greater reduction in energy speed product, but it also has few non desiring disadvantages such as these CMOS logic styles do not work properly for the low operating frequencies. Due to the strict and constant demands of higher speed operation for portable devices and other application has pushed the working in deep sub micron region, where low supply voltage can be utilized. As the supplied is getting lesser, the risk of introduction of leakage current is also increased

In the present time, design with handful of transistors and power supply lesser than the 1V makes it more and more difficult to keep the full voltage swing in limits and even updated. Complementary and level restoring carry logic (CLRCL) full adder is designed to reduce the complexity of the circuit and the cascading operation. This adder shows a speedy operation at the carry part, which serves better for the n-bit operations. Level restoring is needed in order to avoid the multiple threshold loss problems [13].

As the full adder happens to be a basic building block, it can be used in building the complex and large circuits and systems applications, through which a multiplier or an n-bit adder can be constructed. In the base paper, a 4-bit RCA is constructed. This full adder works best for the 4-bit or large adders. With the use of same full adder, other high operation adders can also be constructed as in application.

MCML architectures provide higher invulnerability to supply noise due to their differential structure, lower cross talk due to the reduced output voltage swing and lower noise generated due to the constant current flowing through the supply rails. The constant current used in MCML is the reason for constant power consumption, which is independent of the frequency of operation or gate activity. MCML is the best alternative when the frequency is the issue in the circuit designing. The power consumption is independent from the frequency because the two branches are driven symmetrically and in opposition of phase.

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It is seen that the sum and carry delays for a one bit adder cell differ from each other, making it difficult to draw conclusions regarding the performance of the resultant n bit adder, all the more so since it depends on n as well. In fact, our simulations of four bit adders made up of each version of a one bit adder cell revealed that the proposed implementation should provide faster n bit adders for n = 4, not to mention the larger capacities, as compared with the transmission gate implementation.

A full adder is a digital circuit that performs addition of numbers which gives the sum and carry as an output. The objective of this design is to create a high speed multi bit adders. This full adder designs concerned more on the carry part of the circuit then the sum part, in order to make the transition faster. It deals with the n-bit ripple carry adders. The results are simulated using Cadence ORCAD 9.2 tool with the operating frequency of 50 MHz.

With above considerations in mind, a feasible way can be found to reduce the capacitive load involved in passing a carry from input to output, at the cost of increased transistor count involved in sum generation. This solution should enable the designer to construct n-bit ripple carry full adders that would be superior in speed to the alternative implementations if n > 3, as supported by computer simulations [12].

2.2 ADDER DESIGN

In this proposed work, along with the designing of full adder, a ripple carry adder is also designed using the same one and compared with the other realizations. Ripple carry adder is the most basic and easy adder design to implement and to carry out on the mathematical level. In another way, there are many large adders used in practice such as carry select adder (CSA). Conditional carry adder (CCA), carry look-ahead adder (CLA), carry skip adder (CSA) and there are many other adder that are used to add n-bit full adder rail.

However, Ripple carry adders are slow in functioning i.e., takes comparatively more time in propagating the carry output from one stage to the next stage. It takes typically more area as D (n) and delay of D (n). While the carry select adder and carry skip adder has same area of D (n) but shows the delay of D (n(l+2/l+l) and calculates the output faster. Carry look-ahead adder occupies the area of D (nlog(n)) and delay is D(log n), but it has suffered from the problem of irregular layout problem, due to this it does not prove to be good adder at the physical implementation level. As there is no restriction on the number of fan in/fan out condition, but the implementation has to be done using only two gate level stages. On the other hand, carry select adders

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(CSA) reduces the total output calculation time by calculating the sum of all possible carry bits 0 and 1. When the carry is decided then according to the carry values, sum of the bits is computed using the multiplexer.

Presently carry select adders are the fastest adders available, but they face the restriction of numbers of fan outs can be accommodated since the required quantity of multiplexers is also increased exponentially. For a worst case scenario, a carry signals can select total of n/2 multiplexers for the particular n-bit adder. When three or more of the bits are to be added simultaneously using two operand bit adders than the carry propagation will be repeated many times, which is really time consuming [14].

2.3 RIPPLE CARRY ADDER

Ripple carry adder is the basest and simplest design among the family of the long chain adder. The following adder can be designed by cascading the n number of full adder cells. For generating a carry for the next stage, one bit adder generates the sum along with the ripple result for next stage. Here the result of one stage, i.e. carry_out is fed to the next stage carry_in. However, being the simplest one, the ripple carry adder could not be used for the long chain of adder as it will not be sufficient. The main drawback has shown by the following adder that its delay increases as the adder chain extends. Ripple carry adder shows the case of worst delay scenario when carry line goes through all the participated stages of adder block rail from least significant bit right to the most significant bit [15].

t = n 1t + t

Where t is the total time taken by the ripple carry adder, t be the delay to calculate the sum of last stage and t is the delay through the carry stage. The benefits of ripple carry adder are its simple design, lower power consumption and take less area on the layout. The time to perform operation in ripple carry adder is linearly proportional to n, the total number of bits used. Hence, the performance of ripple carry adder is bordered when number of bits n, nurtures larger.

In the ripple carry adder, one get the sum output of the most significant bit, while generating the carry by the previous stage. Here the result would be known, after the carry generated from the previous stage. This is why; the sum of most significant is generated after the carry wave signal is flow through the adder to the most significant bit

(2.1)

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from the least significant bit. As a consequence, the final result of sum and carry are generated with the sizeable delays.

2.3.1 Ripple Carry Addition

This is the simplest form of addition that used to perform in former electronic computers. Adding the binary numbers is same as adding the decimal, only in binary numbers there all only two digits, 0 and 1. Several numbers can be added at a time by propagating the carry from one set of digits to another nearby. Ripple carry addition are used in the application where the complexity is the constraint and time can be adjusted [16].

An example can be taken for binary addition, two binary numbers such as (100111)2 and (1011)2 for ripple carry adder.

Fig. 2.1: Example of ripple carry addition

As shown in Fig 2.1, example of ripple carry addition, the carry generated by the first to bits in the right hand side, i.e. ith bit is propagated to the next stage of

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(i+1)th bits as an operand for the addition operation. This process keeps repeated until all the digits added and left the sum with carry. Here, the sum is acquired from the sequence of least significant t0 to most significant bit t5, i.e. the output of the example is 110010 with carry 0. The performance of the ripple carry adder can be limited when number of bits n becomes larger and flow goes from least significant bit (LSB) to most significant bit (MSB), while generating the carry from previous stage [17].

The fundamental unit i.e. Arithmetic logic unit (ALU) in a digital computer carries the addition by using full adder. The output expression for the sum (Si) and carry (Ci+1) th at the ith bit can be established by equation (2.2) and equation (2.3).

S = A B C+ A B C + A B C+ A B C

C =A B +B C +C A

Where and are the operands of the ith bit and is the carry into the ith stage for the long chain addition.

Fig. 2.2: 4-bit Ripple Carry Adder

(2.3)

(2.2)

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The circuit implementation for the n-bit adder is shown in Fig 2.2. The adder is constructed by cascading the n full adders in the long chain. Fig 2.1 describes the addition pattern and the sums are acquired at the rail sequence of time from Si-2th bit at t0 to Si+1th at t3. The time taken by adder chain to complete the operation of the given design is equal to the (2n+1)tp.

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CHAPTER 3

POWER REDUCTION TECHNIQUES

3.1 POWER

For any digitalized circuit, power can be characterized as the key element for boosting the performance. Any changes in terms of power consumption make a device more reliable and competent. The need for devices that consume a minimum quantity of power is the most important driving force behind the expansion of CMOS technologies. These devices are best known for their suitable power consumption feature. However, by simply having the theoretical knowledge that CMOS technology requires less power than the equivalent devices and logic families does not prove of much use when it comes to the power obligations of a board or system. It is also very important to know not only how to calculate total power consumption, but it is also needed to understand how factors such as input voltage level, input rise time, fall time, power-dissipation, input voltage swing, internal capacitances, and output loading affect the power consumption of any device. The MCML technique also requires lesser power supply and can work on high operating frequencies. The power consumed by devices is divided into the different categories. This function statement addresses the different nature of power consumption in a MCML logic circuit, and, finally, the purpose of entire power consumption in a MCML appliance [18].

3.2 POWER CONSUMPTION COMPONENTS

Due to the requirement of working on suitable operating frequencies compel a stringent limit on power consumption for all the digital circuits and in computer systems as a whole. Consequently, the power expenditure of each and every device on the board and system should be minimized. The consumption of power also leads to the leakage current problem, which happens due to the power supplied to the device. The power computations create the transistor sizing, power supply, current requirements, sizing and criteria for device selection. Power calculations can also be used to determine the maximum reliable operating frequencies [19].

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Two components determine the power consumption in digital circuits:

(a) Static power consumption (b) Dynamic power consumption

Digital devices show very low static power consumption due to which leakage current forms and flows through the circuits and devices. Static power consumption occurs when there is no power supply given to the circuit, but after that current leak through it causing a device to run. This kind of power consumption happens when all inputs are seized at some valid logic level and the circuit is not in charging states. On the other hand, when the circuit is switched at higher frequencies, dynamic power consumption is capable to contribute considerably to the overall power consumption.

Dynamic power consumption can vary severely at a very higher rate. The switching activity causes the charging and discharging of the capacitive load in the circuits, causing a further increment in the given dynamic power consumption. The functional report shows the power consumption in CMOS logic families, operating at 5 volts. These reports elaborate the new and existing methods according to the circuit for estimating the dynamic and static power consumption. Additional information is also required to present the help in clarifying the sources of power consumption of any category, and presents the possible resolutions to diminish the power utilization in a CMOS circuits and systems.

3.2.1 Static Power Consumption

The working of the static power gears become a matter of importance when the devices are at rest. It means the device shows no activity and all are biased to a particular state. The working of the static power gears become a matter of importance when the devices are at rest. It means the device shows no activity and all are biased to a particular state. Due to the occurrence of the static power dissipation, leakage current, the static power dissipation includes sub threshold and reversed biased diode leakage currents.

Due to the necessary but harmful (in a leakage power sense) down scaling of threshold voltages, the sub threshold leakage has become more and more essential. When threshold voltage is in weak inversion, the transistors have not been completely off. The sub threshold current has strong dependence on threshold voltage [20].

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The working of the static power gears become a matter of importance when the devices are at rest. It means the device shows no activity and all are biased to a particular state. Due to the occurrence of the static power dissipation, reversed biased diode leakage current. The static power dissipation includes sub threshold and reversed biased diode leakage currents the sub threshold leakage current flows through it. Due to the necessary but harmful (in a leakage power sense) down-scaling of threshold voltages, the sub threshold leakage is becoming more and more pronounced. Below the threshold voltage, in weak inversion, the transistors are not completely off. The sub threshold current has a strong dependence on the threshold voltage

Fig 3.1: Static Power Consumption for the inverter

In general, all of the low-voltage devices have a CMOS inverter circuit design in their input and output stages and also used in test bench circuit. Therefore, for a obvious understanding of static power consumption in inverter circuit, the CMOS inverter modes is referred as shown in Fig 3.1. It is built with the connection of a pair of PMOS and NMOS transistors.

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As shown in Fig 3.1, if the input is at logic 0, the n-MOS device is OFF, and the p-MOS device is ON (Case 1). The output voltage is VCC or logic 1. Similarly, when the input is at logic 1, the associated NMOS device is biased ON and the PMOS device is OFF. The output voltage is on GND terminal, or logic 0, it is to be noted that one of the transistors is always in OFF stage when the gate is in either of these logic states. Since no current are flowing into the gate terminal, and there is no dc current conducting path from VCC to GND, the resultant steady-state (quiescent) current is at zero stage, therefore, static power consumption is zero. There are three main sources of static power dissipation, diode leakage current, sub threshold current and bias current.

3.2.2 Dynamic Power Dissipation

Dynamic power dissipation is defined as the power consumed while all or few of the inputs are active. When the inputs are active and capacitors are charging and discharging, as a result dissipated power varies through it. It can be divided into two mechanisms such as: switched power dissipation and short circuit power dissipation. The value of each and every of its component is a function of the topology used for circuit and the logic style adopted [21].

(a). Switched power dissipation, (b) Short-circuit power dissipation, (c) Glitch power dissipation.

All of these categories of power dissipation depend more or less on the switching activities, operation timing, output node capacitances and equipped voltage of the circuit. The process of discharging and charging of the circuit of the output node capacitance is repeatedly needed for transmitting the information in CMOS and MCML circuits. The MCML based circuit causes the low leakage currents flows through them. On the other hand, repeated charging and discharging of the output capacitance is necessary to transmit information in CMOS circuits. The switching power dissipation occurs due to the charging and discharging of the internal capacitances. The power consumed in any digital circuit can be represented by equation (3.1).

P = f.C.Vdd2 + f.Ishort.Vdd + Ileak.Vdd

Where

(3.1)

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f is the clock frequency, C is the average switched Capacitance per clock cycle, Vdd is the supply voltage,

Ishort is the short circuit current, Ileak is the leakage current.

Here equation (3.1) gives the mathematical expression for the power consumed due to the switching activity of the digital circuit and system. This expression shows that the dissipated power is dependent upon the operating frequency, output node capacitance, supply voltage, short circuit current and leakage current flow through the circuit.

In a thoroughly optimized efficient power VLSI circuits, the first term of equation (3.1) is by far the governing factor. The standby power redution is accounted for by the third and the last term. Since by increasing the power supply leakage current will also be increased by far, so power supply to the device is kept low. Regarding the first term, in order to reduce the dynamic power consumption, power supply is chosen to be lower valued, since the dissipated power is the square of the supplied power. It is an effective way of reducing the dynamic power dissipation. The above power dissipation expression also shows that the short circuit power and leakage power consumption are also robustly dependent upon the power supplied to the circuit, even when using the lower value of power supply degrades the performance.

The dissipated power for any digital circuit and device is dependent upon the operating frequency, output node capacitance, supply voltage, short circuit current and leakage current flow through them.

(a) Output node capacitance of the logic gate: This capacitance occurred due to the drain diffusion region.

(b) Total interconnects capacitance: The interconnect capacitance effects vastly as technology node shrinks.

(c) Input node capacitance of the driven gate: Due to the induced gate oxide capacitance. Input node capacitance occurs.

For calculating the estimation of average power required to charge up the output node to power supply Vdd and to charge down the output capacitance to the ground level is incorporated. This estimated average power is independent of its characteristics.

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Dynamic power consumption can also be reduced by lower the supply voltage Vdd, lowering the voltage swing at all nodes, reducing the transition factor (switching probability) and reducing the output load capacitance.

3.3 DIODE LEAKAGE CURRENT

When the transistor is turned OFF and some other transistor charges up or down with respect to former bulk latent voltage, then this situation causes the diode leakage current. For example in case of CMOS inverter, when high voltage is applied, PMOS turned OFF, creating an open path from power supply to the output as drain to body potential is equal to (- VDD)and NMOS transistor is ON, creating a short circuit path from output to ground, and it gives the output 0. The final diode leakage current can be established as equation (3.2).

I = A J

Where, is the leakage current density can be fixed by standard technology models and is the drain diffusion area. Since for reflectably small reverse bias potential, diode can be reached to the highest limit of reverse bias current, the leakage current is dependent on supply voltage partially. The leakage current is directly proportional to the diffusion area and the perimeter of the drain terminal. Thus it is understandable to minimize the diffusion are and perimeter in the layout design. The leakage current density also increases at the higher temperatures abruptly, so it can conclude that leakage current density is exponentially proportional to the temperature.

3.4 BIASING CURRENT

MOS current mode logic (MCML) circuit utilizes the biasing current in speeding up the estimation of the logic function by avoiding the process in the cut-off region. Although CMOS circuits do not show the static power dissipation, but few of the logic families that are used in speed up operation such as MCML and pseudo NMOS circuit use it to replace the total pull up PMOS network to a single PMOS transistor. The above power dissipation expression also shows that the short circuit power and leakage power consumption are also robustly dependent upon the power supplied to the circuit. This helps in reducing the total number of transistors which in turn reduces the capacitance, hence lowers the power dissipation. However, the transistor sizes can be varied according to the requirement of generating a valid logic at the output level.

(3.2)

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3.5 SUB THRESHOLD LEAKAGE CURRENT

The causes for sub threshold leakage current are same as the diode current. In the inverter, for high power supply, PMOS is turned OFF. When the transistor is idle that is VGS = 0, there is still some current flowing through it because of the negative value of VDD. The ID vs. VDS shows an exponential relation in the sub threshold region (VGS < VTH) [22].

Fig 3.2 shows the sub threshold current magnitude at gate to source voltage VGS = 0V. The sub threshold current magnitude is shown as the function of device size, supply voltage and process variation. The reduction in threshold voltage exponentially increases the sub threshold current, as it principally affects the magnitude of the given current. Even the threshold current is directly proportional to the transistor size W/L, also an exponential function of the power supply.

Fig 3.2: Leakage current in the logic gate

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3.6 SHORT CIRCUIT POWER DISSIPATION

In actual circuits and systems, signals have non-zero rising times for P net and N net and in the same way have non-zero fall times for P net and N net which causes both of the nets of the CMOS gate to conduct current at the same time. This leads to the flow of a short circuit current for a short period of time. The input and output slopes of the gate should be equal to minimize the overall short circuit dissipation in devices. Also large load capacitance can significantly reduce the short circuit dissipation of the driving part [23].

3.7 INTERNAL POWER

The internal power consumption occurs when the inputs are changing but the circuit is not changing the values at the output in the end. Logic circuits do not necessarily keep changing the values and conducts the current through it. They do not escort a change in the output node at every change in the input value. The full voltage swing of power supply Vdd which leads to the partial voltage swing happens to be greater than the internal node voltage swing [24].

3.8 LOW LEAKAGE POWER CIRCUIT TECHNIQUES

Although with the continuous technology scaling, dynamic power dissipation is keep reducing, but the leakage power dissipation tends to increase every now and then and is looking forward to become a large active component in the total power dissipation in the coming future technology generations. A high leakage power heat up condition can therefore be dangerous for portable electronic devices and circuits. Over the last decade, a plenty of leakage power management techniques and approaches have been developed and addressed in the open literature. In the following section, most common amongst of these methods are discussed [25].

3.8.1 Leakage Control by Body Biasing

The body biasing approach consists of increasing the threshold voltage (Vt) of NMOS devices and PMOS devices during the standby (preservation) mode by diverging the values of body bias voltage (VB), this in turn helps in reducing the leakage current through devices. In order to obtain the threshold voltage Vth higher than the

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threshold voltage at source and body point i.e., Vth0, the body terminal of the NMOS device is kept to bias at the lower point than the ground (threshold voltage for a source-to-body voltage (VSB = 0). In the similar fashion, in order to keep the increment going in Vth, the body terminal of the PMOS device is made to bias to a voltage higher than the supply voltage Vdd.

In the active mode, the NMOS transistors body nodule is biased to ground, Vss in the meanwhile the body nodule of the PMOS transistor is biased to the power supply Vdd, in order to obtain the normal lower value of threshold voltage Vth and obtain the normal speed. Dynamic threshold CMOS (DTCMOS) is an alternative of the leakage control by body biasing since the body is tied up to the gate terminal and a changeable threshold voltage is realized in accordance to the device condition.

3.8.2 Leakage Control by MTCMOS Technique

MTCMOS based schematic diagram is shown in Fig. 3.3.

Fig 3.3: Generalized schematic of MTCMOS technique

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In multi-threshold CMOS (MTCMOS) technique, high threshold voltage Vt switch transistors are used to control leakage. In order to turn off the gates when they are in idle state, the given logic family technique uses low leakage transistors as illustrated in Fig 3.3.

To increase the gate delay time, the gate transistor uses low threshold voltage. But if we lower the threshold voltage, the leakage current increases in turn sources to induce the sleep transistor. This sleep transistor has high threshold voltage to diminish the leakage current. During the reserve mode, the switch transistors are turned OFF and bounds the leakage current credit to their high threshold voltage Vt. In the active mode, the switch transistors are turned ON and act as a virtual Vdd and ground.

To control these transistors, a signal SLEEP" is asserted by the sleep transistor in order to turn ON or OFF the switch transistors to manage the power supply, and this gated power supply is termed as virtual VDD. During the reserve mode, the switch transistors are turned OFF and bound the leakage current magnitude to their high threshold voltage Vt. In the active mode, the switch transistors are turned ON and act as a virtual VDD and ground. If we lower the threshold voltage, the leakage current flows one by one through sources to induce the sleep transistor. This sleep transistor has high threshold voltage to diminish the leakage current. During the reserve mode, the switch transistors are turned OFF and bound the leakage current to their high threshold voltage Vt [26].

3.8.3 Leakage Control by MVCMOS Technique

Multi-voltage CMOS (MVCMOS) is depicted in Fig 3.4. Unlike in MTCMOS where the SLEEP" transistors have high Vt, the MVCMOS technique uses SLEEP" transistors with low Vt whose gates are controlled by a voltage which is larger than VDD for the PMOS transistor and lower than ground for the NMOS transistor during the standby mode. This results in negative Vgs values for both NMOS and PMOS and subsequently in smaller leakage. The magnitude of threshold voltage Vt is dependent upon the supply voltage.

The power consumption depends on the switching activity, the number of transistors and on parasitic capacitances. The die area is influenced by the number of transistors, their sizes and the routing complexity. The choice of the macro-cells schematics is therefore the first important step to design low power circuits. The circuit performances are strongly influenced by the preference of the logic style exploited in designing the fundamental gates.

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Fig 3.4: MVCMOS Technique

The Fig 3.4 above here consists of low Vt logic, which comprised of particular logical boolean expression. This logic network is set to the lower threshold voltage value. Doing this will help in switching off the circuit, while the sleep transistor is set on high threshold will be responsible for the working of total circuit [27].

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CHAPTER 4

MOSFET CURRENT MODE LOGIC (MCML)

4.1 INTRODUCTION TO MCML

MOS current mode logic (MCML) is a new alternative for the traditional CMOS logic style for mixed signal analog applications. It is stated that as the operating frequency and integration density increases for the digital circuit, it will become difficult to protect noise perceptive analog circuitry from noisy digital circuit. It will difficult the integration of analog and digital circuits which is very important. The MCML library shows the less power dissipation at the operating frequency of higher values and more in comparison to the conventional CMOS style. It is nearly impossible to create robust, power efficient and cost effective design and time to market product. To reduce this problem there are many MCLML techniques are used and found the success.

Many efforts have been taken to realize the importance of MCML style. The circuits constructed by using MCML logic style face the problem of complexity and robustness. To reduce this problem, there are many MCML techniques are used and found the success. The MCML universal gate, the popular topology due to the relatively small size and versatility has an asymmetric topology and has considerable robustness. The irregularity at the gate terminal of MCML logic style degrades the overall circuit functionality. It increases the complexity of any prospective MCML model of any gate for simulation [28].

MCML architectures provide higher invulnerability to supply noise due to their differential structure and lower cross talk due to the reduced output voltage swing and lower noise generated due to the constant current flowing through the supply rails. This method enables the designer to explore different execution options For many of applications the prime objective for the design to be efficient is power consumption, speed and power delay product. And these can be explained in the simple terms of process parameters and transistor dimensions. However in the case of MCML technology, it is hard to achieve since the gate terminal of it is supplied with the analog

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signal so the robustness is hard to accomplish since the signal will always be fluctuating, this is why it imposes tight restraint over the MCML design to get less error. [29].

4.2 MCML BASIC OPERATION

Basically MOS current mode logic (MCML) is a digital realization of the differential amplifier. As displayed in Fig 4.1, by transferring the current form one stage to another stage, the given logic can be realized [30].

Fig 4.1: Basic MCML operation

Compare to the nature of analog amplifier, the MCML logic is happened to work in non linear region.

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The following circuit consists of logic realization network, its input blocks in the both side consist of logic implementation. They generally consist of differential pair or set of differential pair organized in certain fashion to regulate the current in one branch and then share it to the other and simultaneously switching off the other input combination applied to it. The output voltage levels are set as shown in equation (4.1), and equation (4.2), where high voltage value is equal to supply voltage and low voltage is equal to the consumed voltage value.

VH = VDD, for logic high

VL = VDD V, for logic low

Where V = ISS R is the voltage swing.

Here, the load resistance R can be replaced by an active load such as PMOS transistor operating in the linear region whereas the tail current ISS is replaced and controlled by the active transistor in the saturation type [32].

4.3 MCML ADVANTAGES

All advantages of MCML are credited to its differential part character. Firstly, a differential topology has high resistance to common mode noise. Secondly, the effective voltage swing can be doubled by the differential signaling which shows the direct proportionality relationship with the noise margin. The proof of improvement in noise margin and noise invulnerability enables designers to accommodate extra noise margin for the voltage swing. As delay is directly proportional to the voltage swing, when voltage swing improves, its delay is also improved. The delay is improved in accordance to the equation (4.3).

D = "$%&&

Where, C is the capacitance at the output node. The major reason for switching noise is the abrupt and extreme current change in the supply rail lines causing effects such as charge injection and ground bounce into the substrate. The current drop in MCML gates provides a steady current regardless of the switching activity. Converse

(4.1)

(4.2)

(4.3)

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to the CMOS approach, the current drop in MCML gates provides a highly steady current regardless of the switching activity making MCML a mixed signal environment friendly alternative [33].

4.4 MCML DISADVANTAGES

The static DC current, which happens to be responsible for the smooth operation of MCML circuits cause the gate terminal to leak excess power even when the gate is in inactive state. Incongruously, it shows mainly imperative advantage of the MCML logic style proves to be its most awful disadvantages. However, the MCML technique is still a beneficial method.

In the CMOS circuit, the power is dissipated in the form of static power and dynamic power. Static power dissipates due to the charge leakage problem and dynamic power dissipates due to the switching activity at the internal nodes. The static leakage power proves to be a bigger problem, as transistor sizes are getting smaller. The smaller the transistor size, more the leakage power will flow. The dynamic power dissipation is due to the discharging and charging of the output node capacitance. The dynamic power dissipation can be stated as equation (4.4).

P"() = fCV-

Where the switching activity, f is the operating clocking frequency and CL is the capacitance hanging at the output node. The power dissipated through the CMOS circuit is directly proportional to the operating frequency.

Whereas on the other hand, the prime source of power dissipation in MCML circuit is static power and is expressed in equation (4.5).

P("( = I V

The expression gives the power in MCML circuit by multiplying the source current to the power supply. The equation above gives the direct relationship in between the power consumed in the process to the current flown in the circuit multiplied by the

(4.4)

(4.5)

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total supply voltage. The MCML circuit shows the effective improvement work for the lower power devices.

4.5 MOSFET MODELS

The MOSFET working depends on various model parameters design using which the efficiency and its operation is defined. The MOSFET operates in the saturation region. The few related models parameters are discussed here [31].

4.5.1 Threshold Voltage

The threshold voltage for any device can be defined as a minimum voltage at which the transistor works and causes the current to flow through it. Threshold voltage creates the spot at which the sturdy inversion process occurs in the MOSFET channel part. Threshold voltage can also be set differently for different transistor in the single circuit. MTCMOS circuit is the example of such concept, where low and high threshold levels are required for conduction. Threshold voltage is defined as the function of the potential across the device terminal and several other material related parameters. The threshold voltage can be articulated by equation (4.6).

V. = V./ + 1|2|5 + V6 |25|

Where VT0 is the threshold voltage at VSB = 0, VSB is source to body voltage, 5 is the Fermi potential and is the parameter that shows the effect of the change of the VSB on VT.

4.5.2 DC Power Supply

The power consumption of any logical circuitry is directly proportional to the power supply VDD so it should be reduced as much as feasible. In order to achieve the lower power consumption, the lower supply voltage is required. NMOS current source imposes the lower limit on the power supply VDD. In MCML method when bias Vb starts working for that period of time, the load transistor P1 and P2 cuts off the power supply and leave the circuit dependent upon the bias voltage. In this way, power supply cannot be able to corrupt the circuit operation.

(4.6)

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The reduction in the power supply VDD drives the circuit design out of the saturation region the output impedance of the current source in the tail end does not harm. Due to this, the voltage gain AV is reduced in consequence. The other outcome of this degradation is that the current in gate is reduced and Current Matching Ratio (CMR) is begun to decrease. Due to the scaling down of the size, voltage is also scaled down, thus the problem of current leakage is increased.

4.6 PERFORMANCE PARAMETER

Under this title, performance factors are explained. There are three performance parameters that are affecting the MCML circuit, working efficiency such as power, delay and power delay product. In chapter 3, power techniques have already been described. Here we will describe the gate delay parameter only [32].

4.6.1 Power Supply Switching Noise

This parameter metric is used to evaluate the capability of MCML circuit to incorporate with analog circuitry. The following metric used can be expressed as the percentage variation of the supply current from its DC average.

4.6.2 Voltage Swing Ratio

Preferably, MCML NMOS transistors act as perfect switches awakening all the DC current from one stage to the other. However, practically, only a fractional part of the tail current is switched from side to side leaving some current behind in the OFF part or stage. The Voltage Swing Ratio (VSR) is defined as the ratio of the current in ON branch to the tail current ISS. Large transition width is required to execute, if one needs to achieve the aim of 100% VSR ratio. Due to this, it witnesses the generous drop in speed. The higher VSR helps in attaining the low leakage current. A small amount of VSR degrades the dc gain of gate and causes the signal to weaken as it processed through the stages.

A reasonable circuit speed can be achieved using with 95% Voltage Swing Ratio which guarantees the assured and smooth operation. For achieving the 100 % VSR device , one needs to have large transition width. If the square law model is used to calculate approximately the transistor DC current saturation, then

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89: =;?@A>BCD>E@

F@@ (4.12)

Where 8 is the drain to source voltage of the differential pair.

4.6.3 PMOS Load Transistor Sizes (WRFP, LRFP)

One of the most complicated tasks is to boost the size of PMOS load transistors, a non linear work to create the efficient MCML circuit. The affect of sizing these transistors imposed on various parameters such as Signal Swing Ratio (SSR), propagation delay, RFP control voltage limit, voltage mismatch and the voltage gain, also this affects the area transactions. To increase the voltage gain of the device, length of PMOS load transistor can be increased. This factor strongly effects when we increase the length of PMOS from minimum to higher.

4.6.4 NMOS Load Transistor Sizes (WRFN, LRFN)

The tradeoffs between area and robustness are important in selecting the transistor sizes of the tail current source. The use of non-minimum length devices for the current source is desirable as it helps in both to decrease the mismatch effects and increase the output impedance. It is required to decrease the VDSAT voltage which further allows the decrement in supply voltage VDD by having a large width to length ratio (W/L). Here we have to impose a restriction over the width to length ratio as the area of the device starts to grow dramatically.

4.7 DYNAMIC MCML

Dynamic current mode logic (DyCML) has been designed to overcome the problem of static power dissipation problem in standard MCML. It is an active logical implementation of MCML. This MCML style has limited voltage swing, reduces the number of gates and interconnects power dissipation. It combines the advantage of MOS current mode logic (MCML) circuits with that of dynamic logic families to achieve the higher performance at lower power supply, dissipates low power. The main advantage of DyCML is that they do not have any static current source. This quality makes it a suitable alternative for battery powered systems and portable devices. Fig 4.2, on the next page, shows the Dynamic CML logic style gate. The operation of the Dynamic

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CML can be performed in two phases such as formely precharge pcycle and later one is evaluation cycle.

Fig4.2: Dynamic CML style

In the precharge phase, when the low clock frquency is applied, M2, M3 and M4 are turned ON. Therefore causing the outputs to rise upto VDD and capacitor C1 is

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discharged to ground. While, in the evaluation phase, when the clock is at high level and M2, M3 and M4 are turned OFF. And therefore, closing the path from CL to ground. Depending on the arrangement of input combination, charges will be start flowing from one of the output terminals to the capacitor CL which acts as a current drop. And transistors M5, M6 of PMOS type are acting as a latch to preserve any of he logic value. The Dynamic CML logic style can shows the considerable power reduction in comparison to Standard MCML. There are disadvantages too with Dynamic MCML style such as increased switching noise and design complexity [38].

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CHAPTER 5

SIMULATION RESULTS

5.1 TOOL USED

For designing and simulating schematic and creating its output waveform TANNER EDA 14.1 Tool