MEMS Pedometer with Digital OutputPresented By:

Zeinab Ramshani

Billy Guerrero

Morteza Rezaei

Ashwin Bharath

What does a pedometer do?

Counting the sharp peak when feet hit the ground

Human acceleration for walking or running: 0.5g to 5g

Why MEMS Pedometer? Small structures Low power consumption Compatible with wireless systems Easy to implement

Nike + Ipod : place Nike+sensor under your shoe pedometer, GPS, pace & time & distance tracker.

Layout Overview

Design Calculations• Spring Constant () = n (Result for one set of springs)

• Total Spring Constant () = K x 4 = 4 (Four springs in parallel)

• Mechanical Sensitivity () = (Max & Min for accelerations of 8 and 0.5 g.)

• Prove-mass Natural Freq () =

• Initial Capacitance () =

• Increment in Capacitance ( = (For of 8 g & 0.5 g)

• Sensitivity () =

Design Calculations

Differential Varying-Overlap Area Capacitive Sensing

Layout Details Proof-mass Volume =

Mass =

434 Fingers

Fingers Length =

Fingers Gap =

Fingers Overlap =

Fingers Thickness =

Varying overlap capacitance

4 Sets of springs

x

3-D Model• Mesh Type: Manhatan bricks

• Element Order: Parabolic

• X Direction Element Size: 50.0

• Y Direction Element Size: 50.0

• Z Direction Element Size: 40.0

Simulations

SimulationsDisplacement (m) with 0 g

PROOF-MASS FIXED-FINGERS

SimulationsDisplacement (m) with 0.5 g

PROOF-MASS FIXED-FINGERS

SimulationsDisplacement (m) with 8 g

PROOF-MASS FIXED-FINGERS

Operating Principle8 g Capacitance Values:

C1 = 1.0947 pFC2 = 0.1782 pFC1 – C2 = 0.9165 pF

0.5 g Capacitance Values:

C1 = 0.6651 pFC2 = 0.6078 pFC1 – C2 = 0.0573 pF

Overall System

MEMS Structure E/D NMOS

Accelerometer ESD Comparator

BufferD flip flops

OR Gates Buffer

OUTPUT

• We apply two voltage supplies

• They have same amplitude and 180 degree phase shift

• When there is no capacitance change, the output voltage will be zero

• The step motion will cause capacitance change, and as a result we have different voltage between the two capacitances

Accelerometer Simulation:

ESD Protection

ESD protection for mixed voltage I/O Using NMOS transistor Stacked in a Cascode configuration, Warrren R. Anderson and David B. krakauer

• To protect our gates from high voltage and current.

• Under an ESD event, the protection device acts as though both gates are grounded since the de-coupling capacitance

on Vdd causes it to float near Vss.

Comparator

“NMOS Analog voltage comparator”, Edward G Pumphrey, Patent umber: 4812681

Buffer• It consists of two NOT gates.

• We use a common source mode for our invertor.

• A depletion NMOS is used as resistor.

• It transforms sinusoidal signals into a uniform step signal

•It is the smallest device that we can use for storing the values

•It is relatively fast

D Flip-Flops Design

D flip flop circuit

• We use a 4 input OR gate

• It consists of one resistor and 4 transistors as a driver

• If any of transistors drive, the output will be logic one

• We use D-NMOS as a resistor, and E-NMOS as a driver

OR Gate

COMPARATOR

BUFFER

D FLIP FLOP D FLIP FLOP

D FLIP FLOPOR OUTPUT BUFFER

Final Circuit Design:

•LTSpice circuit design

•Mentor Graphics

•Coventorware

•LayoutEditor

Circuit Layout Design Steps

LayoutEditor

COMPARATORBUFFER

ESDD FLIP FLOP

OUTPUT BUFFER OR BUFFER

D FLIP FLOP D FLIP FLOPBUFFER

VDD

VSS

OUTPUT

INPUT

REFERENCE

CLOCKTEST POINT

TEST POINT

TEST POINT

VSSTEST POINTTEST POINT

ESD

VDD

Circuit Layout with test points

Questions ??

Thank you !!