memory arrangement

8/7/2019 Memory Arrangement

1/21

Memory ArrangementThere are two memory blocks in the PIC16F8X:

y The program memory (14bits Bus)y The data memory. (8bits Bus)

Each block has its own bus, so that access to each block can occur during the same clock cycle.

The data memory can further be broken down into: y The General Purpose Registers (GPR)

andy The Special Function Registers (SFRs)

The data memory area also contains the data EEPROM memory. This section of memory isindirectly mapped. That is, an indirect address pointer specifies the address of the data EEPROMmemory to read/write. The 64 bytes of data EEPROM memory have the address range 0h-3Fh.

Program Memory Arrangement The unit of the program memory is 14bits rather than 8bit (1byte). That is to say, each location ofthe program memory consists of 14bits to allow each instruction to execute in one clock cycle.

The PIC16FXX has a 13-bit program counter capable of addressing an 8K x 14 program memoryspace. For the PIC16F84 and PIC16CR84, the first 1K x 14 (0000h-03FFh) are physicallyimplemented. Accessing a location above the physically implemented address will cause a wrap-around. For example, for the PIC16F84 locations 20h,420h, 820h, C20h, 1020h, 1420h, 1820h,and 1C20h will be the same instruction. The reset vector is at 0000h and the interrupt vector is at0004h.


2/21

PIC16x84 Program Memory Arrangement

Data Memory ArrangementThe data memory is partitioned into two areas.

y The first is the Special Function Registers (SFR) area.y The second is the General Purpose Registers (GPR)

area.The SFRs control the operation of the device. Portions of

data memory are banked. This is for both the SFRarea and the GPR area. The GPR area is banked to allow greater than 116 bytes of general

purpose RAM. The banked areas of the SFR are for the registers that control the peripheralfunctions. Banking requires the use of control bits for bank selection.These control bits are


3/21

located in the STATUS Register. The figure below shows the data memory map organization.InstructionsMOVWF and MOVF can move values from the W register to any location in the

register file (F), and vice-versa.The entire data memory can be accessed either directly usingthe absolute address of each register file or indirectly through the File Select Register (FSR).Indirect addressing uses the present value of the RP1:RP0 bits for access into the banked areas ofdata memory.Data memory is partitioned into two banks which contain the general purposeregisters and the special function registers. Bank 0 is selected by clearing the RP0 bit(STATUS). Setting the RP0 bit selects Bank1. Each Bank extends up to 7Fh (128 bytes).The first twelve locations of each Bank are reserved for the Special Function Registers. Theremainder are General Purpose Registers implemented as static RAM.


4/21


5/21

PIC16x84 Data Memory Arrangement

General Purpose Register File (GPR)Each GPR is 8 bits wide and is accessed either directly or indirectly through the FSR. The GPRaddresses in bank 1 are mapped to addresses in bank 0. As an example, addressing location 0Chor 8Ch will access the same GPR.

Special Function Registers (SFR)

The Special Function Registers are used by the CPU and Peripheral functions to control thedevice operation. These registers are static RAM. The special function registers can be classifiedinto two sets:

y coreand

y peripheral.

What is Bank 0 and Bank 1 and why PIC needs to use them?

One of the things that puzzled me when I started learning to use PIC microcontroller is what ismemory bank0 and Bank1 and why we need to use them?. To explain this we need to look at thegeneral format of the PIC instruction. This is explained thoroughly later in the PIC instruction setsection but for this section I will use only some basics.The instruction set of the PIC16f84 consists of 14bits divided into sections :OPCodeDirection of result value (d)File registers address.

General Instruction Format For Byte-oriented file register operations

The space allocated for the file registers address is 7bits wide which gives a range of addresses0x0 - 0x7F (0000000b - 1111111b). Now to addresses locations above 0x7F we need an extrabit. This bit comes from the STATUS register (bit 5 RP0). This bit controls what is known asmemory banks and is responsible for switching between two memory banks. When RP=0 Bank0is selected and addresses range from 0x0 - 0x7F and when RP=1 Bank 1 is selected andaddresses range from 0x80 - 0xFF. You can think of the Bank selection bit as the extra eighth bitin the File registers address space in the PIC instruction.


6/21

Special function registersAn area of data memory is dedicated to registers that are required for configuration and dataflowcontrol. This dedicated memory area is divided into a number of special function registers whichcan not be used as general purpose registers by the programmer. The special function registersare TMR0, OPTION, PCL, STATUS, FSR, PORTA, PORTB, TRISA, TRISB, EEDATA,EECON1, EEADR, EECON2, PCLATHand INTCON and are situated in the data memorylocations shown in Figure below

File

Addres

s

Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit2 Bit 1Bit 0

Value

on

Power

-On

Reset

Value

on

Other

Reset

s

Bank 0

0x00 INDFUses contents of FSR to address data memory (not a physical

register)---- ---

----- ---

-

0x01 TMR0 8-bit real-time clock/counterxxxxxxxx

uuuuuuuu

0x02 PCLLeast Significant 8 bits of the Program Counter (PC) 0000

000000000000b7 b6 b5 b4 b3 b2 b1 b0

0x03 STATUS IRP RP1 RP0 TO PD Z DC C00011xxx

000qquuu

0x04 FSR Indirect data memory address pointer 0 xxxxxxxx

uuuuuuuu

0x05 PORTA - - -RA4/

T0CKI

RA3 RA2 RA1 RA0 ---xxxxx

---uuuuu

0x06 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0xxxxxxxx

uuuuuuuu

0x07Unimplemente

dUnimplemented location, read as '0 ---- ----

---- ----

0x08 EEDATA EEPROM data registerxxxxxxxx

uuuuuuuu

0x09 EEADR EEPROM address registerxxxxxxxx

uuuuuuuu

0x0A PCLATH - - -Most Significant 5 Bits of the PC ---0

0000---0

0000b12 b11 b10 b9 b8

0x0B INTCON GIE EEIE T0IE INT E RBIE T0IFINT

F

RBI

F

0000

000x

0000

000u

Bank 10x80 INDF Uses contents of FSR to address data memory (not a physical ---- -------- ---


7/21

register) -

0x81 OPTION RBP

UINTED

GT0C

ST0SE PSA PS2 PS1 PS0

11111111

11111111

0x82 PCL Least Significant 8 bits of the Program Counter (PC)00000000

00000000

0x83 STATUS IRP RP1 RP0 TO PD Z DC C00011xxx

000qquuu

0x84 FSR Indirect data memory address pointer 0 xxxxxxxx

uuuuuuuu

0x85 TRISA - - -PORTA data direction register ---1

1111---1

1111b4 b3 b2 b1 b0

0x86 TRISBPORTB data direction register 1111

111111111111b7 b6 b5 b4 b3 b2 b1 b0

0x87 Unimplemented

Unimplemented location, read as '0 ---- -------- ----

0x88 EECON1 - - - EEIFWRER

RWRE

NWR RD

---0x000

---0q000

0x89 EECON2 EEPROM control register 2 (not a physical register) ---- -------- ---

-

0x8A PCLATH - - -Most Significant 5 Bits of the PC ---0

0000---0

0000b12 b11 b10 b9 b8

0x8b INTCON GIE EEIE T0IE INT E RBIE T0IFINT

FRBI

F0000000x

0000000u

Legend: x = unknown, u = unchanged. - = unimplemented read as 0, q = value depends on condition. SpecialFunction Registers (SFR)

0x stands for hexadecimal

The Status RegisterBit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

IRP RP1 RP0 TO PD Z DC C

The STATUS register is of most importance to programming the PIC, it contains the arithmeticstatus of the ALU (Arithmetic Logic Unit), the RESET status and the bank select bit for datamemory. As with any register, the STATUS register can be the destination for any instruction. Ifthe STATUS register is the destination for an instruction that affects the Z, DC or C bits, then thewrite to these three bits is disabled. These bits are set or cleared according to device logic.Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with theSTATUS register as destination may be different than intended. For example, CLRF

STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as000u u1uu (where u = unchanged).


8/21

The first three bits (STATUS to STATUS) are the carry (C), digit carry (DC) and zero(Z) flags of the ALU respectively. The values of these bits change depending on the results ofarithmetic or logical operations performed during program execution. Bits 3 and 4 are the powerdown PD and watchdog timer timeout TO bits respectively and bits 5and6(RP0 and RP1) are thebank selection bits.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R = Readable bitW= Writable bitU = Unimplemented bit, read as 0 -n= Value at PORreset

bit 7:IRP: Register Bank Select bit (used for indirect addressing)0 = Bank 0, 1 (00h - FFh)

1 = Bank 2, 3 (100h - 1FFh)The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.

bit 6-5:RP1:RP0: Register Bank Select bits (used for direct addressing)00 = Bank 0 (00h - 7Fh)01 = Bank 1 (80h - FFh)10 = Bank 2 (100h - 17Fh)11 = Bank 3 (180h - 1FFh)Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear.

bit 4:TO: Time-out bit

1 = After power-up, CLRWDT instruction, orSLEEP instruction

0 = A WDT time-out occurred

bit 3:

PD: Power-down bit1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2:Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zero

bit (forADDWF and ADDLW instructions) (For borrow the polarity is reversed)

bit 1:DC: Digit carry/borrow1 = A carry-out from the 4th low order bit of the result occurred0 = No carry-out from the 4th low order bit of the result

bit (forADDWF and ADDLW instructions)


9/21

bit 0:

C: Carry/borrow1 = A carry-out from the most significant bit of the result occurred0 = No carry-out from the most significant bit of the result occurredNote: For borrow the second operand the polarity is reversed. A subtraction is executed by

adding the twos complement of. For rotate (RRF, RLF) instructions, this bit is loaded with eitherthe high or low order bit of the source register.

The Option RegisterBit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

RBPUINTEDGT0CST0SE PSA PS2 PS1 PS0

The OPTION register in the PIC 16f84 microcontroller is a readable and writable register whichcontains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt,TMR0, and the weak pull-ups on PORTB.

Bits 0, 1 and 2 are the three prescaler division ratio bits for either the timer/counter module orthe watchdog timer WDT, depending on which of these have been allocated for use.

Bit 3 selects the assignment of the prescaler/postscaler to either the timer/counter, or thewatchdog timer.Bit 4 selects whether the timer/counter increments on the falling edge or the rising edge of theexternal square wave signal on pin TOCKI when external timer clocking is selected; otherwise,the waveform is ignored.

Bit 5 is used to choose between external timer clocking via the TOCKI pin, or via the internalinstruction cycle clock.

Bit 6 selects between interrupt triggering on either a rising or falling edge.

Bit 7 enables or disables the weak internal pull-ups on the pins of PORTB when the port isconfigured as an input. The pull-ups are disabled when the port is in output mode.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0


R = Readable bitW= Writable bitU = Unimplemented bit, read as 0-n= Value at PORreset

bit 7:

RBPU: PORTB Pull-up Enable bit

0 = PORTB pull-ups are disabled1 = PORTB pull-ups are enabled (by individual port latch values).

bit 6


10/21

INTEDG: Interrupt Edge Select bit1 = Interrupt on rising edge of RB0/INT pin0 = Interrupt on falling edge of RB0/INT pin

bit 5T0CS: TMR0 Clock Source Select bit1 = Transition on RA4/T0CKI pin0 = Internal instruction cycle clock (CLKOUT)

bit 4:T0SE: TMR0 Source Edge Select bit1 = Increment on high-to-low transition on RA4/T0CKI pin0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3:PSA: Prescaler Assignment bit1 = Prescaler assigned to the WDT0 = Prescaler assigned to TMR0

bit 2,1,0:PS2:PS0: Prescaler Rate Select bits

BitValue

TMR0Rate

WDTRate

000 1 : 2 1 : 1

001 1 : 4 1 : 2

010 1 : 8 1 : 4

011 1 : 16 1 : 8

100 1 : 32 1 : 16

101 1 : 64 1 : 32

110 1 : 128 1 : 64

111 1 : 256 1 : 128

The INTCON RegisterBit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

GIE EEIET0IEINTERBIET0IF INTFRBIF

The INTCON register is a readable and writable register which contains the various enable bitsfor all interrupt sources.

The meaning of INTCON might be (though this is only me thinking)INTurrpt

CONtrol register.I have serached the net for the source of this acronym with no avail; if you find it please e-mail

me.


11/21

Anyway, interrupt flag bits get set when an interrupt condition occurs regardless of the state ofits corresponding enable bit or the global enable bit, GIE (INTCON).

This register is used to configure the interrupt control logic circuitry. Bits 0 to 6 are used toconfigure the interrupt enable/disable statuses and the interrupt flags for the four interruptsources. No interrupt to the CPU will result unless the GIE bit is set. The GIE bit is the bitINTCON and when set, enables all un-masked interrupts.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE EEIE T0IE INTE RBIE T0IF INTF RBIF


R = Readable bitW= Writable bitU = Unimplemented bit, read as 0-n= Value at PORreset

bit 7:GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts0 = Disables all interruptsbit 6EEIE: EE Write Complete Interrupt Enable bit1 = Enables the EE write complete interrupt0 = Disables the EE write complete interrupt

bit 5T0IE: TMR0 Overflow Interrupt Enable bit1 = Enables the TMR0 interrupt0 = Disables the TMR0 interrupt

bit 4:

INTE: RB0/INT Interrupt Enable bit

1 = Enables the RB0/INT interrupt0 = Disables the RB0/INT interrupt

bit 3:RBIE: RB Port Change Interrupt Enable bit1 = Enables the RB port change interrupt0 = Disables the RB port change interrupt

bit 2:T0IF: TMR0 overflow interrupt flag bit1 = TMR0 has overflowed (must be cleared in software)0 = TMR0 did not overflow

bit 1:INTF: RB0/INT Interrupt Flag bit

1 = The RB0/INT interrupt occurred0 = The RB0/INT interrupt did not occur


12/21

BIT 0:RBIF: RB Port Change Interrupt Flag bit1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)0 = None of the RB7:RB4 pins have changed state

PIC16F87XA Data Memory Organization

The data memory is partitioned into multiple banks which contain the General Purpose Registersand the Special Function Registers. Number of banks may vary depending on themicrocontroller; for example, micro PIC16F84 has only two banks.

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for theSpecial Function Registers. Above the Special Function Registers are General Purpose Registers,implemented as static RAM. While program is being executed, it is working with the particularbank. The default bank is BANK0.

To access a register that is located in another bank, one should access it inside the program.There are special registers which can be accessed from any bank, such as STATUS register.


13/21

PIC16F876A/877A register file map

In order to start programming and build automated system, there is no need to study all theregisters of the memory map, but only a few most important ones:

y STATUS register changes/moves from/between the banks

y PORT registers assigns logic values (0/1) to the ports

y TRIS registers - data direction register (input/output)

You can learn about other registers at a later stage or as needed.

STATUS register

Field Code Changed

Field Code Changed

Field Code Changed


14/21

In most cases, this register is used to switch between the banks (Register Bank Select), but alsohas other capabilities.

PIC STATUS register

With the help of three left bits (IRP, RP1, and RP0) one can control the transition between thebanks:

y IRP - Register Bank Select bit, used for indirect addressing method.

y RP1:RP0: - Register Bank Select bits, used for direct addressing method.

To distinguish between the two methods, at this point, the will use the definition of fundamentalconcepts. Later on, the two methods will be studied in detail.When the IRP Equal to 0, the program will work with banks 0, 1.When the IRP Equal to 1, the program will work with banks 2, 3.

The following table demonstrates, which of the Banks the program is working with, based on theselection of the RP0 and RP1 bits:

RP1:RP0 BANK

00 0

01 1

10 2

11 3

An example of using STATUS register and Register Bank Select bit :

1. bsf STATUS, 5 ; Change to Bank 1

2. clrf TRISB ; Set PORTB as output

3. bcf STATUS, 5 ; Change to Bank 0

In the first line, we are in changing/setting the 5th bit, RP0, in the STATUS register to 1, andthus, base on the table we are switching/selecting Bank 1. After PortB was set as output in the


15/21

second line, we switched back to Bank 0 by in changing/setting the 5th bit, RP0, in the STATUSregister to 0, in the third line.

C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

An example of using STATUS register and Carry/borrow bit:

1. Movlw 200

2. Addwf 100,0

In this example, we are assigning value of 200 to the W (working) register. Then, we are adding

the value of 100 and the W register together. The result is stored in W register and should be 300(200+100).However, the maximum value is 256, resulting in carry out. The C (bit 0) of the STATUSregister becomes 1 (C = 1). Register W will contain the reminder: 44.

DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow,the polarity is reversed)1 = A carry-out from the 4th low order bit of the result occurred0 = No carry-out from the 4th low order bit of the result

Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zero

The bits 3 and 4 are used with WDT - Watchdog Timer.

PD: Power-down bit1 = After power-up or by the CLRWDT instruction0 = By execution of the SLEEP instruction

TO: Time-out bit1 = After power-up, CLRWDT instruction or SLEEP instruction0 = A WDT time-out occurred

PORT register

The role of the PORT register is to receive the information from an external source (e.g. sensor)or to send information to the external elements (e.g. LCD). The 28-pin devices have 3 I/O ports,while the 40/44-pin devices, like PIC16F877, have 5 I/O ports located in the BANK 0.

1. PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA.

Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input. Clearing a TRISA bit (=

0) will make the corresponding PORTA pin an output.


16/21

2. PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB.Setting a TRISB bit (= 1) will make the correspondingPORTB pin an input. Clearing a TRISB bit (=

0) will make the corresponding PORTB pin an output.

3. PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC.

Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input. Clearing a TRISC bit (=

0) will make the corresponding PORTC pin an output.

4. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as

an input or output.

5. PORTE has three pins (RE0/RD/AN5,RE1/WR/AN6 andRE2/CS/AN7) which are individually

configurable as inputs or outputs. These pins have Schmitt Trigger input buffers.

Pin diagram of PIC16F877A

We can control each port by using an assigned address of specific port, but there is much easierway to control the port. We are allowed to use the names of the ports without considering theiraddresses.

For example:# define SWITCH PORTA, 0


17/21

We define a variable named SWITCH, which received a value of bit number 0 of the PORTA.Usually we define the ports at the beginning of the program, and then we use only the givennames.

TRIS register

The TRIS register is data direction register which defines if the specific bit or whole port will bean input or an output. Each PORT has its own TRIS register. Here's a map of the locations:

BANK0 BANK1

PORTA TRISA

PORTB TRISB

PORTC TRISC

PORTD TRISD

PORTE TRISE

The default mode of each TRIS is input. If you want to set a specific port as exit you mustchange the state of the TRIS to 0.

Keep in mind: to change a specific port to an output, one should first move to the BANK1, makethe change, and then return to BANK0. The default state of the banks is BANK0.

The running program is working only with one bank at all time. If not set otherwise, then asstated, the default bank is BANK0. Part of the registers located inside BANK0, and some are not.When we need to access a register that is not located inside BANK0, we are required to switchbetween the banks.

For example, the access to PORT registers is done inside BANK0. However, to change port froman input to an output and vice versa, we need to access TRIS register that is located insideBANK1. From the moment we moved to the BANK1, the program will always work withBANK1; at this time, to access registers inside BANK0, we will have to return to the situation inwhich our program will work with BANK0.

CLICK HERE to access PIC16F877A data sheet for more in formation on PIC memoryorganization

Direct and Indirect addressing

Field Code Changed


18/21

Direct Addressing: Using this method we are accessing the registers directly by detectinglocation inside Data Memory from Opcode and by selecting the bank using bits RP1 and RP0 ofthe STATUS register.

Indirect Addressing: To implement indirect addressing, a File Select Register (FSR) and indirectregister (INDF) are used. In addition, when using this method we choose bank using bit IRP ofthe STATUS register. Indirect addressing treated like a stack pointer, allowing much moreefficient work with a number of variables. INDF register is not an actual register (it is a virtualregister that is not found in any bank).

Dont be confused! There is SFR (Special Function Register) - special registers of RAM, andthere is FSR (File Select Register).

The following figure shows the two addressing methods:

Pin diagram of PIC16F877A

To the left you can see the direct addressing method, where the bank selection is made by RPbits and the referencing is made directly from memory Opcode by using the variable name.

To the right you can see the indirect addressing method, where the bank selection is made by IRPbit and accessing the variable by pointer FSR.

Lets explore the differences between the 2 methods :

We want to assign number 5 to the variable TEMP located at address 0X030. In the first row ofeach example, we will define the variable TEMP at the address 0X030 .

Example of direct addressing:


19/21

1. TEMP Equ 0x030

2. Movlw 5

3. Movwf TEMP

It's easy to understand, that direct addressing method means working directly with the variables.In the second line we put the number 5 into the working register W, and in the line 3, the contentof the W passes to the TEMP variable .

Example of indirect addressing:

1. TEMP Equ 0x030

2. Movlw 0x030

3. Movwf FSR

4. Movlw 5

5. MovwfINDF

In the second line, we put a value into the W register. In the third line, the value passes to theFSR register, and from this moment FSR points to the address of the TEMP variable. In thefourth line, the number 5 passes to the W register, and in the fifth line, we move the contents ofW register (which is 5) to the INDF. In fact INDF performs the following: it takes the number 5and puts it in the address indicated by FSR register.

PIC16F87XA Data EEPROM

The data EEPROM and Flash program memory is readable and writable during normal operation(over the full VDD range). This memory is not directly mapped in the register file space. Instead,it is indirectly addressed through the Special Function Registers.

There are six SFRs used to read and write to this memory:

1. EECON1

2. EECON2

3. EEDATA

4. EEDATH

5. EEADR

6. EEADRH


20/21

When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write andEEADR holds the address of the EEPROM location being accessed. These devices have 128 or256 bytes of data EEPROM (depending on the device), with an address range from 00h to FFh.On devices with 128 bytes, addresses from 80h to FFh are unimplemented.

A few important points about Data EEPROM memory:

y It lets you save data DURING programming

y The data is saved during the burning process

y You can read the data memory during the programming and use it

y The use is made possible with the help of SFR

At this point there is no need to learn how to use this memory with special registers, becausethere are functions (writing and reading) that are ready.

Write to DATA EEPROM

To write to an EEPROM data location, the user must first write the address to the EEADRregister and the data to the EEDATA register. Then the user must follow a specific writesequence to initiate the write for each byte.

BSF STATUS, RP1 ;BSF STATUS, RP0 ; Bank 3BTFSC EECON1, WR ;Wait for writeGOTO $-1 ;to completeBCF STATUS, RP0 ;Bank 2

MOVF DATA_EE_ADDR, W ;Data MemoryMOVWF EEADR ;Address to writeMOVF DATA_EE_DATA, W ;Data Memory ValueMOVWF EEDATA ;to writeBSF STATUS, RP0 ;Bank 3BCF EECON1, EEPGD ;Point to DATA memoryBSF EECON1, WREN ;Enable writesBCF INTCON, GIE ;Disable INTs.MOVLW 55h ;MOVWF EECON2 ;Write 55hMOVLW AAh ;MOVWF EECON2 ;Write AAhBSF EECON1, WR ;Set WR bit to begin writeBSF INTCON, GIE ;Enable INTsBCF EECON1, WREN ;Disable writes

Read DATA EEPROM


21/21

To read a data memory location, the user must write the address to the EEADR register, clear theEEPGD control bit (EECON1) and then set control bit RD (EECON1). The data isavailable in the very next cycle in the EEDATA register; therefore, it can be read in the nextinstruction. EEDATA will hold this value until another read or until it is written to by the user(during a write operation).

BSF STATUS, RP1 ;BCF STATUS, RP0 ; Bank 2MOVF DATA_EE_ADDR, W ; Data MemoryMOVWF EEADR ; Address to readBSF STATUS, RP0 ; Bank 3BCF EECON1, EEPGD ; Point to Data memoryBSF EECON1, RD ; EE ReadBCF STATUS, RP0 ; Bank 2

MOVF EEDATA, W ; W = EEDATA

Both of these functions are provided by the manufacturer. There is a required sequence in orderto write/read to/from the memory; that process can be performed independently, but it is better touse ready functions of Microchip.

memory arrangement

Documents