MECHANISMS AND MODELING OF SINGLE-EVENT UPSET

Paul E. Dodd Sandia National Laboratories, MS-1083, Albuquerque, NM 87 185-1083

Abstract The basic mechanisms of single-event upset are reviewed, including charge collection in silicon junctions and transistors, and properties of single-event upset in CMOS static random access memory (SRAM) cells. The mechanisms are illustrated through the use of three-dimensional device and circuit simulations. Technology trends and implications for commercial devices are discussed.

1. Introduction Single-event effects in microelectronics are caused when highly energetic particles

present in the natural space environment (e.g., protons, neutrons, alpha particles, or other heavy ions) strike sensitive regions of an integrated circuit. As it passes through the device, the particle directly liberates charge along its path. In some cases the incident particle may undergo a nuclear spallation reaction and create additional charge through ionization by secondary particles. If this charge is collected at a sensitive node of the circuit, the resulting current transient may lead to a change in the memory state of the circuit (known as a single-event upset (SEU), or equivalently, a soft error). In this paper we use three-dimensional physics-based simulations to illustrate the mechanisms responsible for single-event upset. The impact of technology trends on SEU are discussed, including some implications for commercial and terrestrial devices.

2. Physics-Based Modeling of SEU Simulation of SEU has traditionally been performed with either circuit simulators such as

SPICE [ 13, or drift-diffusion finite-element device simulators [2]. Circuit simulators have the advantage of being computationally efficient and are commonly used by the radiation-hardened circuit designer. This method is less physically rigorous than device simulation, because the single-event is simply emulated by inserting a semi-arbitrarily defined transient current source at the struck circuit node. Still, this method is very useful for determining the relative SEU sensitivity of different circuit designs. Drift-diffusion device simulators solve the Poisson and current continuity equations to give the evolution of charge transport following a single-event

, strike [3]. To properly account for charge generation and transport, these calculations must be performed in three dimensions, and are therefore very computationally intensive. Because SEU in static circuits such as SRAMs is really a circuit-level effect initiated at the device level, simulations of a single device in these cases can only give insight into charge collection, and do not directly address the circuit-level occurrence of SEU [3]. In the last several years, a combined simulation approach that treats both the device and circuit response to a particle strike has become widely used. This mixed-level approach relies on enhanced device simulators with the ability to simultaneously solve the multidimensional device equations in the struck device and the circuit equations of SPICE compact elements attached to the struck device [4-61. Very recently, the ability to model entire SRAM cells in three dimensions has been demonstrated [7];

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this approach may prove to be necessary in small-geometry devices as coupling effects between transistors become more pronounced.

Using the mixed-level approach, one can predict the upset threshold of an SRAM cell to particle strikes at a particular location and angle of incidence [3]. Because this method is still computationally intensive, it is not possible, in general, to predict the entire upset cross-section curve as a function of linear energy transfer (LET, a measure of the charge deposited by the particle per unit pathlength through the semiconductor). This information is needed to make predictions of the error rate for a given environment of interest. Using ultrapowerful computers, it may be possible to perform simulations for many strike locations and compute the upset cross- section from first principles. Sandia is porting a commercial 3D mixed-level device code (DAVINCI) to its Teraflop computer in order to enable this enhanced level of SEU simulation capability [SI.

3. Charge-Collection Mechanisms The basic properties of charge collection following a particle strike have been studied

using a variety of experimental and theoretical methods. Broadbeam charge collection spectroscopy measurements have been used to determine SEU-sensitive volumes in SRAMs [9], and ion microbeams and lasers have been used with high-speed sampling oscilloscopes to measure charge-collection transients in Si and GaAs devices [ 10,111. Ion microbeams and lasers have also been used to map charge collection as a function of position in ICs [12,13], and more recently as a function of both time and position [14].

Immediately following the discovery of SEU, device simulators were applied to compute the response of reverse-biased pln junctions to alpha-particle strikes [2,15]. An important insight gained from these early charge-collection simulations was the existence of a transient disturbance in the junction electrostatic potential, which was termed the “field funnel,” as shown in Fig. 1. Charge generated along the particle track can locally collapse the junction electric field due to the highly conductive nature of the induced charge plasma. This funneling effect can increase charge

/”* Region

Fig. 1. Illustration of the funnel effect in an n+/p junction following a 5-MeV alpha-particle strike [ 151. Contours of electrostatic potential are shown in (a); ion-induced electron density is shown in (b). Funneling is indicated by the extension of the equipotential lines along the strike path in (a).

collection at the struck node by extending the junction electric field away from the junction and deep into the substrate, such that charge deposited some distance from the junction can be collected through the efficient drift process. The funnel effect has been studied in further detail by later researchers [16,17], including the influence of epitaxial substrates on the transient charge-collection characteristics [ 18,191. While undoubtedly important to charge collection in isolated pln junctions with constant applied bias, the role of the funnel is less significant in the more realistic case of a reverse-biased transistor junction connected to external circuitry. In this scenario, the applied voltage at the struck junction is not constant, and in fact very often the struck node may switch from being reverse-biased to zero-biased (see Section 4). This loss of bias at the struck node tends to lessen the importance of drift collection (and hence the funnel) as the single-event transient proceeds because of reduced electric fields [20].

4. Single-Event Upset in SRAMs Single-event charge collection in charge-storage devices such as dynamic random access

memories (DRAMs) causes upset by directly altering the stored charge at the information node [21]. In memory circuits with active feedback such as SRAMs, single-event charge collection can also produce upsets, but both the timing and the magnitude of the charge-collection signal play an important role in determining whether upset will occur (timing is important for upsets in DRAMs, too, but mainly from the standpoint of sensitive timing windows [21]).

4. I The SEU Mechanism in SRAMs When an energetic particle strikes a sensitive location in a SRAM (typically the reverse-

biased drain junction of a transistor biased in the “off” state, see Fig. 2), charge collected by the junction results in a transient current in the struck transistor. As this current flows through the struck transistor, the restoring transistor (“on” p-channel transistor in Fig. 2) sources current in an attempt to balance the particle-induced current. Unfortunately, the restoring transistor has a finite amount of current drive, and equally importantly, a finite channel conductance. Current flow therefore induces a voltage drop at the drain of the restoring transistor. This voltage transient in response to the single-event current transient is actually the mechanism that can cause upset in SRAM cells. The voltage transient is essentially similar to a write pulse, and can cause the wrong memory state to be locked into the memory cell. Interestingly, incident particles far below the upset threshold are often sufficiently ionizing to induce a momentary voltage “flip” at the struck node. Whether an observable SEU occurs depends on which happens faster: the feedback of the voltage transient, or recovery of the struck node voltage as the single-event current dies out. Note that in terms of the fundamental charge-collection characteristics discussed in Section 3, drift (including funneling effects) is responsible for the rapid initial flip of the cell, while long-term charge collection by diffusion prolongs the recovery process; both mechanisms are critical to the upset process.

The recovery time depends on many factors, such as the particle LET, the strike location, etc. From a technology standpoint, the recovery time depends on the restoring transistor current drive and minority carrier lifetimes in the substrate [22]. A higher restoring current leads to a faster recovery time, as do decreased minority carrier lifetimes. The cell feedback time is simply the time required for the disturbed node voltage to feed back through the cross-coupled inverters and latch the struck device in its disturbed state. This time is related to the cell write time and in its simplest form can be thought of as the RC delay in the inverter pair. This RC time constant is

Hardened Memory Cell

(struck transistor)

Fig. 2. In SRAM cells, the recovery and feedback processes compete. If feedback occurs first, the cell upsets. If recovery occurs before feedback is completed, the cell returns to its initial state.

thus a critical parameter for determining SEU sensitivity- the smaller the RC delay, the faster the cell can respond to voltage transients (including write pulses) and the more susceptible the SRAM is to SEU.

4.2 SRAM SEU Hardening Strategies With an understanding of the upset mechanism in SRAMs, we can immediately

understand the typical techniques used to harden SRAMs against SEU. The feedback process can be slowed by adding either resistance or capacitance to the feedback loop, at the obvious price of decreasing the write speed of the memory cell at the same time [23]. Cross-coupled feedback resistors (see Fig. 2) are the classical method of increasing the cell feedback time, but a variation on this method is the use of gated resistors (transistors) as a feedback element [24]. An advantage of the latter approach is that during a write pulse the feedback resistance can be lowered to reduce the impact of the feedback element on operating speed. One method to decrease the cell recovery time is to use oversized (wider) restoring transistors, since they provide a higher restoring current drive (and at the same time typically add capacitance to the feedback loop). An alternative to slowing down the feedback path is to directly lower charge collection by reducing the collection volume. The use of silicon-on-insulator (SOI) technologies is an example of such an approach, and may be necessary to maintain both high-speed performance and good SEU immunity [25].

5. Technology Trends For many years it has been known that as device feature sizes scale, sensitivity to SEU

increases [26,27]. This is due to several factors, including a direct dependence on gate length, as well as other technology changes that tend to accompany smaller feature sizes, such as reduced power supply voltages. Interestingly, as device and cell areas are reduced there is a tradeoff between increased SEU susceptibility per cell and the decreased probability that an individual cell will be struck by a particle [21].

5. I Contributing Technology Parameters Technology parameters that influence the SEU sensitivity include gate length, gate oxide

thickness, and power supply voltage. Increased SEU susceptibility as gate length is decreased has been well documented, and may be due to direct channel conduction [28], bipolar coupling mechanisms between the source and drain [29], or decreased gate capacitance as the gate area is reduced [30]. Fig. 3a shows an example of the decreased threshold for SEU for two strike locations as gate length is decreased and all other parameters are held constant. The results shown were obtained using 3D mixed-level simulations of a model p-substrate technology with 150 kQ feedback resistors. As the power supply is decreased and all other parameters are held constant (Fig. 3b), the SEU threshold also decreases due to reduced current drive in the restoring transistor and less stored charge. However, reductions in power supply voltage are usually accompanied by reduced gate oxide thickness. Thinner gate oxides result in higher gate capacitance and higher current drives, so SEU thresholds increase with decreasing gate oxide thickness if all other parameters are constant (Fig. 3c). If all parameters are taken into account, the overall trend is still a general increase in SEU susceptibility with each technology generation (Fig. 3d). From a radiation-hardening standpoint, standard resistive hardening becomes less feasible as feature sizes drop because the method fundamentally relies on slowing the cell response, negating a key advantage of advanced technologies.

h . 150 kR Feedback Resistors

0 Outside the well OFF

Inside the well OFF --/ -5 i? 6 2 E

N

100 W -J 9 0

2 !-

f - r

lo I I 0.0 1 .o 2.0

Gate Length (pm) Fig. 3a. Simulated threshold LET scaling with gate

length in a model p-substrate technology.

50 100 150 200 250 Oxide Thickness (Angstroms)

Fig. 3c. Simulated threshold LET scaling with gate oxide thickness for outside the well strikes.

2.5 3.0 3.5 4.0 4.5 5.0

'00 0 Fig. 3b. Simulated threshold LET scaling with power

supply voltage for outside the well strikes.

1 ' I I

0.0 1 .o 2.0 Feature Size (pm)

Fig. 3d. Simulated threshold LET scaling for outside the well strikes with all parameters included.

5.2 Terrestrial Soft Errors The occurrence of soft errors in terrestrial systems (DRAMs and SRAMs) has been

known almost since the first observations of SEU in space [31]. The primary cause of soft errors at the ground level was quickly diagnosed as alpha-particle contaminants in packaging materials. After considerable early activity, the terrestrial soft error problem was mostly alleviated by using low-activity materials and on-chip shielding coatings [32]. The march toward higher integration densities has made soft-error concerns a continual design consideration for advanced DRAM and SRAM development in the last decade. A particular area of recent concern is flip-chip packaging technologies that place a source of alpha particles (Pb-Sn solder bumps) right on the die itself, where they are not shielded by coating layers [33]. Recent studies have proved that in addition to on-chip sources of radiation, terrestrial cosmic rays (primarily neutrons) are a significant source of soft errors in both DRAMs and SRAMs [34-361. Neutron-induced ground-level upset rates have been estimated to be 1-2~10-l~ upsetshit-hr across a range of commercial DRAMs and SRAMs [36]. This revelation has significant implications for terrestrial applications, because systems can’t realistically be shielded against incident neutrons. It has been suggested that because manufacturers of commercial microelectronics for terrestrial applications have to deal with alpha particle-induced upsets, commercial parts will by design remain hard to at least the alpha-particle threshold, as illustrated in Fig. 4 [37]. Indeed, there is historical evidence supporting this view as data from more than 10 years of microprocessor evolution show a constant upset threshold just above the threshold for alpha particle upset. However, it is also known that many manufacturers have specific soft-error driven design rules for placement of devices relative to on-chip solder bumps [33]. This clearly implies that at least some devices being manufactured are in fact already below the alpha-particle threshold for upset.

F

Fig. 4.

4 I-------- ix 0.01

Critical charge to SEU as a function of feature size in multiple technologies. Some data indicate the trendline may saturate above the alpha-particle upset threshold (After Johnston [37]).

6. Conclusion In this paper we have briefly reviewed some of the fundamental mechanisms of single-

event upset in modern microelectronic devices. Mixed-level simulations have proven to be very useful for studying the characteristics of charge collection and SEU in many situations. Charge collection may be by drift, funnel-enhanced drift, or diffusion- each is important to the upset process. Upset in SRAM cells is caused by a voltage transient induced by charge collection at the struck node. Technology trends are increasing the SEU susceptibility of advanced devices, and the penalties of traditional hardening techniques are becoming more difficult to accept. As commercial manufacturers become increasingly concerned about soft errors in terrestrial applications, it is probable that additional resources from outside the space radiation effects community will be focused on discovering new and creative solutions to single-event upset.

7. Acknowledgements The author wishes to thank Fred Sexton, Dan Fleetwood, and Peter Winokur for helpful

reviews of this manuscript. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy under Contract DE- AC04-94AL85000.

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