mapping algorithm for large-scale field programmable analog array (fpaa)

ISPD’2005, San Francisco April 5, 2005

Mapping Algorithm for Large-scale Field Programmable Analog Array (FPAA)

Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson Hall, and David Anderson

School of Electrical and Computer Engineering

Georgia Institute of Technology

Atlanta, GA 30332

{baskaya, sreddy, limsk, tyson, dva}@ece.gatech.edu


2Motivation: Gene’s law*

Signal processing systems require low power Analog devices are preferred for low power operation

* Gene Frantz, “Digital Signal Processor Trends”, IEEE Micro, Nov 2000

1980 1990 2000 2010 2020 2030Year

Pow

er /

MM

AC

ProgrammableAnalog Power

Savings

>20 Year Leap

in Technology

0.1mW

10mW

100W

1W

Gene's LawDSP PowerCADSP Power

Gene's LawDSP PowerCADSP Power

10nW

1W

Power consumption trends

in DSP microprocessors

Contribution of analog design


3Field Programmable Analog Arrays (FPAA)

Array of Computational Analog Blocks (CAB)

Discrete time and continuous time versions

Not LUT based => heterogeneous resources

Interconnect lines not segmented => less routing options

Device/interconnect constraints different from FPGA => existing methods do not easily apply!


4Previous Work

Discrete Time (switched capacitor based) FPAA Former IMP EPAC: 150 kHz Former Motorola MPAA *: 200 kHz

Continuous Time CMOS/Bipolar FPAA Lee-Gulak’1995: 125 kHz Fast Analog Solutions TRAC: 4 MHz Floating-gate based RASP: 11 MHz

CAD tools Ganesan-Vemuri: DAC’2001 Wang-Vrudhula: Mixed Design of Integrated Circuits and Systems,

2001

*Now distributed by Anadigm


5Floating gate based FPAA

Vfg

Vtun

Floating gate

PFET switch

Computational Analog Block

(CAB) components

2D array of CABs


6Interconnect Analysis

Three types of interconnects: type1: intra-CAB type2: inter-CAB, intra-column type3: inter-CAB, inter-column

Clustering determines type1 vs. types 2&3

Clustering maximizes type1 use

Vertical/horizontal wires are not segmented (unlike FPGA)

R ~ 10 k (switch on resistance)

Cx = (all switch C’s on a line)


7Layout of a single CAB in FPAA

components

switch

matrix


8Advantages of floating-gate based FPAA

Larger scale

More components per CAB More CABs per chip More component variety

Floating gate PFET switch technology

Non-volatile memory unit Programmable on resistance Linear Voltage-Current characteristics


9Analog Circuit Modeling

*netlist description.device fpaa1.devvcc 1 0in1 2 0in2 3 0out1 4 0out2 5 0op1 2 6 7cg1 6 0nf1 3 10 0cf1 10 11mm2 11 12 13vm1 8 9 12 13 x x x x 4 5 x x.l2constraints op1 ca1 cg1….end

-

+In1 max

min

In2

max

min

C4 (SOS)

In Out

4*4 Vector

Multiplier

Out2Out1

op1

mm1

cf1

nf1mm2vm1

pf1cg1

ca1

In2

Out1

Out2

In1

gnd

vccps1

ps2

ps3

ps4

ps5

ps6

Extracting a directed graph from an analog circuit


10FPAA device modeling

8*8 FPAA and its graph based representation Small circles => routing switches Large circles => CABs


11Problem Formulation

Objective Minimum number of CABs Minimum number of inter-CAB connections

Constraints User constraints: certain components have to be in the

same CAB Device constraints: each CAB can accommodate certain

number of components of each type Net constraints: each CAB can have a maximum

number of nets for intra-CAB and inter-CAB connections


12Overview of FPAA Clustering

Simple (but effective) greedy heuristic1. Pre-cluster user-defined components

2. Order circuit components

3. For each component in order

1. Find the best CAB

2. Merge the component & CAB

3. If no CAB available

1. allow constraint violation

2. fix it by adding more neighbors

4. Compute utilization


13FPAA Clustering Algorithm

1. Determine constrained groups 2. Modified Hyper Edge Coarsening (MHEC)

ordering 3. Assign groups/components to the best

available CABs i. High priority (scarce) components ii. User defined groups iii. Remaining components in MHEC ascending order

pf1

cf1

nf1

mm1

CAB1 CAB2

CAB3 CAB4

ps6ps5vm1

op1cg1

ca1

mm2

CAB1 CAB2

CAB3 CAB4

ps6ps5vm1

CAB1 CAB2

CAB3 CAB4

ps6ps5vm1

op1

cg1

ca1


14How to select the best CAB?

Check availability of the CAB Device constrains Net constraints

If available, rank the CAB in favor of: Resulting CAB occupancy Net increase in intra-CAB connections Net decrease in inter-CAB connections

Select CAB with highest rank


15Inter-CAB Interconnect Reduction

If a component has too many connections to fit in “ANY” CAB: Select CAB with smallest violation Look for components to reduce inter-CAB interconnects

pkey: number of nets NOT between component and CAB skey: number of nets between component and CAB

Pick the lowest pkey & break ties with higher skey

cutsize:

before => 6 nets

after => 5 nets


16Recent Progress

FPAA clustering has been improved to include net-driven, path-driven and a hybrid of net/path-driven approaches

Net-driven minimizes inter-CAB connections

Path-driven considers path length balance

FPAA Placement has been implemented


17Experimental Setup

architecture fpaa1 fpaa2 fpaa3dimension 4*4 8*8 12*12local wires 16*10 64*10 144*10vertical global wires 4*6 8*15 12*33horizontal global wires 4*8 8*8 12*8

FPAA Architectures

benchmarks

ckt arch #cells #nets cabs_opt ckt arch #cells #nets cabs_optc1 fpaa1 10 16 2 c11 fpaa2 217 245 32c2 fpaa1 21 27 3 c12 fpaa2 199 226 23c3 fpaa1 20 27 3 c13 fpaa2 326 356 37c4 fpaa2 32 45 5 c14 fpaa2 328 366 39c5 fpaa2 44 55 7 c15 fpaa3 395 482 57c6 fpaa1 42 48 8 c16 fpaa3 440 471 50c7 fpaa2 110 147 17 c17 fpaa3 438 484 52c8 fpaa2 112 122 14 c18 fpaa3 444 487 52c9 fpaa2 118 143 19 c19 fpaa3 534 602 72c10 fpaa2 220 242 27 c20 fpaa3 525 564 60

We cluster each circuit w/ four different cell ordering methods:

random, net-driven, net-path driven & path-driven


18Results

number of cabs/optimum number of cabs

1.091.1

1.111.121.131.141.151.161.171.181.19

random net-driven net/path-driven

path-driven

% cab utilization

6464.5

6565.5

66

66.567

67.568


path-driven

%intra-CAB interconnect utilization

05

101520

25303540


path-driven

%inter-CAB interconnect utilization

0

10

20

30

40

50

60


path-driven


19Conclusion

We require low power reconfigurable analog devices for signal processing applications

Floating gate based FPAA provides a large-scale solution

We developed an algorithm for clustering targeting floating gate based FPAA


20Future Work

Complete FPAA Physical Synthesis Tool including: Clustering Placement Routing

Synthesize circuits => measurements

Elaborate FPAA switch vs wire analysis

Optimal FPAA Architecture Selection


21

Thank you

mapping algorithm for large-scale field programmable analog array (fpaa)

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