lp trend08 godwin

Predictable Success

Low Power Trends and

Methodology

Godwin Maben

© 2008 Synopsys, Inc. (2)

Predictable Success

• Introduction

• Summary of Low Power Techniques

Designer’s Arsenal

• Details on each Technique

Technology Highlights

Advantages/Trade-Offs

Challenges

• Synopsys Low Power Flow Summary

Agenda


Predictable Success

Reasons for Low Power Demand

It’s all about

battery life

250nm180nm130nm 90nm 65nm 45nm

Leakage Power

Dynamic Power

Sourc

e: In

tel


Predictable Success

Reasons for Low Power Demand

13%

22%

41%

48%

0%

25%

50%

75%

Consumer Communications Computer/

Peripherals

Other

2004 2006 2007

1% 1%

30%

10%

1%

10%

26%

21%

0%

20%

40%

60%

>250nm 250nm 180nm 130nm 90nm 65nm 45nm 32nm

Last Current Next

Application Driven Technology Driven

Source: SNUG 2007


Predictable Success

Summary of Low Power Techniques

(Designer’s Arsenal)


Predictable Success

Factors Governing Power

Minimize Ileak by:

Reducing operating voltage

Fewer leaking transistors

Minimize Iswitch by:

Reducing operating voltage

Less switching cap

Less switching activity

Total Power

Dissipation

Dynamic PowerDissipation

Static PowerDissipation

Ileak

Iswitch

dtfCVIVE cDDleakDD

t

)( 2

0

t

leakDD dtIV0

Total Power

Dissipation

Dynamic Power

Dissipation

Static Power

Dissipation t

cDD dtfCV0

2

Ileak

Iswitch


Predictable Success

Basic Low Power Techniques

Summary

f

d

b

b

a

c

a

c

c

d

b

16 bit 64 bit

Ripple 90 366

CLA 100 405

Carry

Skip108 437

Carry

Select161 711

Carry

Save218 1323

FF

Q

EN

CLK

D

FF

Q

EN

LT

ICG

LT

ICG

LT

ICGCLK

D

Clock Gating

-

Delay

Le

ak

ag

e C

urr

en

t

Low VTH

Nominal VTH

High VTH

-

Delay

Le

ak

ag

e C

urr

en

t

Low VTH

Nominal VTH

High VTH

Multi-Threshold


Predictable Success

Advanced Low Power Techniques

Summary

Non minimum size gate lengths VTCMOS

A Z

Stack Effect

Power Gating

A Z

VDDB

VSSB

nSLEEP

Virtual VDD

Virtual VSS

SLEEP

0.8V0.7V

Multi-Voltage (MV)

1.0V


Predictable Success

Details on each Technique

• Clock Gating

Basic Understanding

Advantages

Concerns in the flow


Predictable Success

Understanding Clock Gating

CLK

D

ENFF

Q

CLKCLK

D

EN FF

Q

FF

Q

EN

CLK

D

FF

Q

EN

LT

ICG

LTLT

CLK

D


Predictable Success

• Enable Timing

• Insertion delay increase

Impact on OCV

• Peak Power during ON/OFF of clock

IR drop as well

• Verification Impact

Clock Gating Flow Challenges


Predictable Success

Managing Enable Timing


Predictable Success

Clock Gating Impact on Verification

• RTL functional Simulation

None

• Gate level Simulation

FF

Q

EN

CLK

D

FFEN

LT

ICG

LT

ICG

LT

ICG

DReset

“0/1”

“X”

“0/1”

FF


Predictable Success


• Multi-Threshold Leakage Optimization

Basic Understanding

Advantages



Predictable Success

• Multiple Threshold Cells

Understanding Multi Threshold

16ps

Vdd 0.9v

Vth 0.3v

10ps

Vdd 0.9v

Vth 0.22v


Predictable Success

Multi-Threshold Flow Challenges

• Looking at a different view of the problem, optimizations push towards zero-slack

• High-Vt cells tend to be weaker and can be more susceptible to variability

+ve slack-ve slack

Power critical

range

Slack


Predictable Success

Multi-Threshold Flow Challenges

• Implant Spacing

Violations

• Min Width Violations

• Chip Finishing

requires Proper filler

Cell Insertion


Predictable Success


• Power Gating

Basic Understanding

Advantages



Predictable Success

Understanding Power Gating

VDDG

Gating

Control

Switch Fabric

Switch Fabric

Sw

itch

Fab

ric

Power Gated

Block

Always On

Block

VSS

ISO


Predictable Success

Architectural Tradeoffs

• Amount of leakage power savings that is

possible

• Entry and exit time penalties incurred

• Energy dissipated entering and leaving such

leakage saving modes


Predictable Success

Activity Profile for Power Gating

WAKESLEEPSLEEP WAKE SLEEP

Dynamic Power

Activity “X”

Leakage Power

Activity “X”

Leakage Power

Power Gated

Dynamic Power

Activity “Y”

Leakage Power

Activity “Y”

Dynamic Power

Activity “Z”

Leakage Power

Activity “Z”Leakage Power

Power Gated

TIME

Po

wer


Predictable Success

Realistic Profile for Power Gating

WAKESLEEPSLEEP WAKE SLEEP

Dynamic Power

Activity “X”

Leakage Power

Activity “X”

Leakage Power

Power Gated

Dynamic Power

Activity “Y”

Leakage Power

Activity “Y”

Dynamic Power

Activity “Z”

Leakage Power

Activity “Z”Leakage Power

Power Gated

Po

wer

TIME


Predictable Success

Architectural Tradeoffs

• Gate VDD or

VSS?

• Retention

Mechanism


Predictable Success

• Functional Verification

Power Gating Flow ChallengesClock wiggling while

power-gated

Island Power-gated

(Z)

Save

Restore

RETENTION Rail

Registers RESTORED

Rail ramp-up

Rail with Standby

value (0.6 volts)Rail ramp-down


Predictable Success

Power Gating Sequence/Coverage

Voltage States: 8/8

Logical States: 2/3

Is the wakeup/shutdown

sequence correct ?


Predictable Success

VDD

on/off VDD_BACKUP

Shut

Down

RR

CP

D

SI

SE

LDRS

Q

•Logic Synthesis

Power Gating Flow Challenges

GATE

VSS

OFF VDD

Active

Logic

Active

Logic

X ISOEN

save

restore

Insert Isolation Cell Insert Retention RegisterHookup Retention Register


Predictable Success

Power Planning the Switches

MAXIR

(mV)

Area

(%) Resistance

# PWR

SWITCHE

S

X_INC

R

Y_INC

R LIB_CEL_NAME

37.2 0.4 650.0 328.0 26.3 3.6 SXXZZYX8L

42.7 0.3 1300.0 328.0 26.3 3.6 SXXZZYX4L

43.6 0.2 650.0 164.0 26.3 7.2 SXXZZYX8L

53.2 0.2 2600.0 328.0 26.3 3.6 SXXZZYX2L

55.3 0.2 1300.0 164.0 26.3 7.2 SXXZZYX4L

72.5 0.2 650.0 164.0 52.6 3.6 SXXZZYX8L

53.2

39.9


Predictable Success

NSLEEP

VDD

VVDD

t0 t1 t2

Power-up Normal - Power-on

NSLEEP

VDD

VVDDPower-up Normal - Power-on

IR-Drop Management

IN

VSS

NSLEEP

VDD

VVDD

NOT_IN

Limit the voltage

drop across the switch

TimeT

T- T+

Volts

Turn On All Switches at Once

Sequentially Turn On Switches


Predictable Success


• Multi-Voltage

Basic Understanding

Advantages



Predictable Success

• Static Voltage

• Multi-Level Voltage Scaling

• Dynamic Voltage and Frequency Scaling

• Adaptive Voltage Scaling

Multi-Voltage Design Style

Mode

Control

Monitor Monitor

Monitor

Voltage Island Voltage Island

A B

C

Voltage

Regulators

Voltage Island


A

1.2 V, 350 MHz

Voltage Island

B

1.0 V, 250 MHz

C

1.5 V, 500 MHz

Mode

Control


A B

C

Voltage

Regulators

Voltage Island

Pro

gra

mm

able


Predictable Success

Understanding Multi-Voltage/Scaling

• Avoid completing tasks early – energy is wasted

• Use only enough energy required to complete task in time

Time

VoltageReduce

Voltage

Reduce

Voltage

Reduce

Voltage

Task 1 Task 2 Task 3Idle

Energy

Energy

Saved

Energy

Run Task Slow

as Possible

Run Task in

Available Time


Predictable Success

• Voltage/Frequency are not changed at runtime

Change of V/F is defined either through s/w or h/w

Voltage/Frequency changed in a specific direction based on the “amount of change”

Wait till Voltage/Frequency are locked

Designs at run time will operate on locked Frequency/Voltage

• Identify the various operating voltages under which blocks will be operating at any point of time

• Do we have libraries characterized at these V points?

Voltage Scaling Facts

Control

Unit(CU)

requests VCU to

ramp up Voltage

VCU Interrupts

CU when Target

Voltage Reached

CU programs clock

generator to maximum

Frequency

CU requests

VCU to ramp

down voltage

and reprograms

clock generator

to lower

Frequency

0V

1.08V

0.7

6V


Predictable Success

Voltage Scaling Flow Challenges

When Vsrc is between VIH

And VIL propagate “X”

Vsrc1.0v

0.6v

0.0v

HiX ZSIM

Output

• Accurately represent effects of dynamic change

in voltage values during simulation

Logic0

X

Logic1

Vｄｓｔ

Vｓｒｃ

1.0V

0.0V

0.6VVIH

VIL


Predictable Success

Voltage Scaling Flow Challenges• Synthesis

Multi-Mode Optimization

Optimal Voltage for Timing/Area/Power Optimization

Level Shifter Optimization based on Mode

• Power Planning

Optimal Power Grid

• Choose the appropriate Power Numbers


Predictable Success

Voltage Scaling Flow Challenges

• Placement, CTS and Route

Minimize Skew

MCMM

Placement of Level Shifters

Temperature Inversion

0

1000

2000

3000

3.5 3.8 3.9 4 4.2 4.4 4.5

# Fl

op

s

Large Skew Across Domains

0

1000

2000

3000

3.5 3.9 4.1 4.4 4.7

# Fl

op

s

Reduced Skew Across Domains

VDDMax

VDDMin

VDDMax

Mode1

Mode2

Mode3


Predictable Success

Voltage Scaling Timing Challenges

• Functional or Performance Failures

DFF

D Q

CLK

DFF

D Q

CLK

Combinatorial

DFF

D Q

CLK

DFF

D Q

CLK

VDD=1.0 VDD=1.0 VDD=1.0 VDD=1.0

VDD=1.0

VDD=1.0VDD=1.0

D

CLK

Set-up Time Met


Predictable Success

Voltage Scaling Timing Challenges

• Functional or Performance Failures

Set-up Time

Failure

DFF

D Q

CLK

DFF

D Q

CLK

Combinatorial

DFF

D Q

CLK

DFF

D Q

CLK

VDD=1.2 VDD0.95 VDD=0.99 VDD=0.91

VDD=1.0

VDD=0.99VDD=0.98

D

CLK


Predictable Success


• Back Biasing

Basic Understanding

Advantages



Predictable Success

Understanding Biasing

Short Stop

Body Bias (VTCMOS)

Reduced Leakage

Long Stop

MTCMOS

Zero Leakage

Shut-Down Wake-Up


Predictable Success

Reducing Leakage using Well Bias

• When VPW < Source

Vth increases

ID decreases

Leakage decreases

FILLBIAS

VDD

VSS

VPW

VNW

Connect N-Well to

VDD

Connect P-Well to

VSS – 0.3V

Source DrainGate

ID

p-well

n+ n+

VPW

Source

Drain

Gate VPW ID


Predictable Success

Well Biasing Flow Challenges

• Impact on Area due to extra Pick-Up cells

• Multi-Corner Analysis required for Sign-Off

VBB = 1V, VBB = 2V…etc

• Sleep to Transition Power Overhead

• LVS complexity

• Well RC extraction


Predictable Success

Power Savings Data

Technique Used Technology % Leakage

Savings

% Total Power

Savings

Clock gating 90nm NA 57%

Multi-Vt 90nm 31% NA

Power Gating 130nm 25X 13x

Power Gating 65nm 2x NA

DVFS 45nm 98% during

Standby

NA

Predictable Success

Thoughts on Efficient Leakage Power Management


Predictable Success

Source:IBM

Efficient Leakage Power

Management

VD

D

VS

S

VDD

VSS VIRTUAL_VSS

VVSS

VDD

Gate Voltage

Gate Voltage

Source:IBM


Predictable Success

Voltage Generator

Multiple Power Mode Implementation

VD

D

VS

S

VDD

VSS VIRTUAL_VSS

VVSS

VDD

Gate Voltage

S0 S1 S2

S0 S1 S2

1 0 0 Snore

0 1 0 Dream

0 0 1 Sleep

0 1 1 Active

Source:I

BM


Predictable Success

Activity Profile of Multiple Sleep Modes

Sleep

Snore

Shut-DownWake-Up

DreamDream

Active


Predictable Success

Recycle Energy - Hybrid Car

Mo

tor

Ge

ne

rato

r

Battery


Predictable Success


Mo

tor

Ge

ne

rato

r

Battery


Predictable Success

Recycle Leakage

Full Chip

Standard

Cell Area

VDD

GND


Predictable Success

Recycle Leakage

Full Chip

Standard

Cell Area

VDD

TEMP_GND

Charge

Collector

GND


Predictable Success

Recycle Leakage

Full Chip

Standard

Cell Area

VDD

TEMP_GND

Charge

Collector

GND

VDD_SPARE


Predictable Success

RTL

Synthesis

Simulation

Vector

Analysis

TB

Vector

Good?

No

Power

Analysis

Power

Good

Yes

No

Place

and

Route

Sign-Off

Analysis

VCD

Yes Parasitic

Extraction

Re-architect

vectors

Re-architect

Design

Where Best to Manage Power and How?

Architectural Changes


Predictable Success

Synopsys Low Power Flow Summary


Predictable Success

Predictable Success

lp trend08 godwin

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