low-power design and architecture

5
n recent years, total power consumption has contin- ued to increase despite the use of lower supply volt- ages. Increased power consumption is driven by higher operat- ing frequency. It is also driven by higher overall capacitance and resistance of larger chips with more on-chip functions (see Table 1). Thus, power consumption has become an increasing concern to many designers. This concern focuses on two particular categories: portable battery operations and high performance desktop applications. Due to its limited power-supply capa- bility, we are facing a dilemma in current battery technology that has two design problems. One is meeting the stringent speed constraint for real-time multimedia applications. The other is how to prolong the operating time of wireless multime- dia systems. For high-performance desktop appli- cations, the second concern arises where heatsinks on the packages are permitted. In Table 1, the operating power for a 626 MHz, 320 M transistor Integrated Circuit (IC) can be upwards of 115 W. This power level is outpacing the capacity of the packages to dissipate the heat. The reduction in package size and environ- mental impacts, such as the heat dissipa- tion noise, need to be addressed. In addi- tion, ceramic substrates can resist high transition temperatures for increased reli- ability but they increase costs. Superior thermal design and simulation proce- dures are needed for packages and devices with more effective heat dissipa- tion characteristics that provide an assur- ance of quality. Thus, for Application Specific Integrated Circuits (ASIC) designers, power is becoming more of a constraint: the increasing power con- sumption decreases reliability and increases costs associated with packaging and cooling devices. In this article, we will review some design techniques for low-power systems. What are the main components for saving power? Figure 1 shows the common approach to achieving low power. First, start with a low voltage technology—while the other criteria, such as performance and speed, are initially met—and then work on suc- cessive solutions until an optimal one for the project is reached. However, remem- ber that at the various levels of design abstraction, varying degrees of power sav- ing will occur. Table 2 shows the power savings observed by using low-power design techniques and IBM Blue Logic design methodologies in an Application Specific Integrated Circuit (ASIC). Actual power savings will probably vary from design to design. However, most power savings come from these two extremes: voltage reduction and architec- tural/logic changes. Table 1 clearly shows that reducing the supply voltage works best for decreasing the switching power dissipation. Low voltage tech and power model design Power model. There are three princi- pal components of power consumption in complementary metal-oxide-semicon- ductor (CMOS) integrated circuits: switching power, short-circuit power and leakage power. Subsequently, power consumption in CMOS devices is classi- fied as both a static and a dynamic com- ponent. The dominant part is the dynam- ic part. It is known that reduced voltage operation comes at the cost of reduced throughput. The maximum rate at which a circuit is clocked monotonically decreases as the voltage is reduced. Thus, for low voltage technologies to be effec- tive appropriate metrics, i.e., energy, power-delay product, must be estab- lished, initially. These metrics can be used in different applications (depending on the design requirements) to guide optimization towards the best solution and to provide strict criteria for compar- ing performances. Low voltage technology. An effective method for low power design is to reduce 18 0278-6648/01/$10.00 © 2001 IEEE IEEE POTENTIALS In conserving energy, every bithelps Hyeongseok Yu and Jun-Dong Cho I © 1997 Artville, LLC. Year 2001 2002 2003 2004 2005 Technology node 180 nm 130 nm 100 nm ASIC usable Mega transistors/cm2 40 54 73 99 133 (auto layout) ASIC maximum functions per chip 320 432 584 800 1064 (Mega transistor/chip) Package cost(cents/pin)- 1.71/0.81 1.63/0.77 1.55/0.73 1.47/0.70 1.40/0.66 maximum/minimum On-chip, across chip clock, high- 626 700 761 828 900 performance ASIC (MHz) Minimum logic Vdd(V)-minimum 1.2 1.2 1.2 0.9 0.9 (for lowest power) Power consumption for High- 115 130 140 150 160 performance with heatsink(W) Power consumption for Battery(W)- 1.7 2 2.1 2.3 2.4 (hand-held) Table 1 Expected VLSI Technology in the International Technology Roadmap for Semiconductors (ITRS) Hyeongseok Yu and Jun-Dong Cho

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n recent years, total powerconsumption has contin-ued to increase despite theuse of lower supply volt-ages. Increased power

consumption is driven by higher operat-ing frequency. It is also driven by higheroverall capacitance and resistance oflarger chips with more on-chip functions(see Table 1). Thus, power consumptionhas become an increasing concern tomany designers. This concern focuses ontwo particular categories: portable batteryoperations and high performance desktopapplications.

Due to its limited power-supply capa-bility, we are facing a dilemma in currentbattery technology that has two designproblems. One is meeting the stringentspeed constraint for real-time multimediaapplications. The other is how to prolongthe operating time of wireless multime-dia systems.

For high-performance desktop appli-cations, the second concern arises whereheatsinks on the packages are permitted.In Table 1, the operating power for a 626MHz, 320 M transistor Integrated Circuit(IC) can be upwards of 115 W. Thispower level is outpacing the capacity ofthe packages to dissipate the heat. Thereduction in package size and environ-mental impacts, such as the heat dissipa-tion noise, need to be addressed. In addi-tion, ceramic substrates can resist hightransition temperatures for increased reli-ability but they increase costs. Superiorthermal design and simulation proce-dures are needed for packages anddevices with more effective heat dissipa-tion characteristics that provide an assur-ance of quality. Thus, for ApplicationSpecific Integrated Circuits (ASIC)designers, power is becoming more of aconstraint: the increasing power con-sumption decreases reliability and

increases costs associated with packagingand cooling devices. In this article, wewill review some design techniques forlow-power systems.

What are the main componentsfor saving power?

Figure 1 shows the common approachto achieving low power. First, start with alow voltage technology—while the othercriteria, such as performance and speed,are initially met—and then work on suc-cessive solutions until an optimal one forthe project is reached. However, remem-ber that at the various levels of designabstraction, varying degrees of power sav-ing will occur. Table 2 shows the powersavings observed by using low-powerdesign techniques and IBM Blue Logicdesign methodologies in an Application

Specific Integrated Circuit (ASIC). Actual power savings will probably

vary from design to design. However,most power savings come from these twoextremes: voltage reduction and architec-tural/logic changes. Table 1 clearlyshows that reducing the supply voltageworks best for decreasing the switchingpower dissipation.

Low voltage tech andpower model design

Power model. There are three princi-pal components of power consumption incomplementary metal-oxide-semicon-ductor (CMOS) integrated circuits:switching power, short-circuit power andleakage power. Subsequently, powerconsumption in CMOS devices is classi-fied as both a static and a dynamic com-ponent. The dominant part is the dynam-ic part. It is known that reduced voltageoperation comes at the cost of reducedthroughput. The maximum rate at whicha circuit is clocked monotonicallydecreases as the voltage is reduced. Thus,for low voltage technologies to be effec-tive appropriate metrics, i.e., energy,power-delay product, must be estab-lished, initially. These metrics can beused in different applications (dependingon the design requirements) to guideoptimization towards the best solutionand to provide strict criteria for compar-ing performances.

Low voltage technology. An effectivemethod for low power design is to reduce

18 0278-6648/01/$10.00 © 2001 IEEE IEEE POTENTIALS

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Hyeongseok Yu and Jun-Dong Cho

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Year 2001 2002 2003 2004 2005Technology node 180 nm 130 nm 100 nmASIC usable Mega transistors/cm2 40 54 73 99 133(auto layout)ASIC maximum functions per chip 320 432 584 800 1064(Mega transistor/chip)Package cost(cents/pin)- 1.71/0.81 1.63/0.77 1.55/0.73 1.47/0.70 1.40/0.66maximum/minimum On-chip, across chip clock, high- 626 700 761 828 900performance ASIC (MHz) Minimum logic Vdd(V)-minimum 1.2 1.2 1.2 0.9 0.9(for lowest power) Power consumption for High- 115 130 140 150 160performance with heatsink(W) Power consumption for Battery(W)- 1.7 2 2.1 2.3 2.4(hand-held)

Table 1 Expected VLSI Technology in the International TechnologyRoadmap for Semiconductors (ITRS)

Hyeongseok Yu and Jun-Dong Cho

AUGUST/SEPTEMBER 2001 19

the supply voltage while satisfying theperformance constraints. This methodinvolves combining architectural and cir-cuit optimization techniques. Reducingthe supply voltage dramatically reducespower. It is driven by several factors:reduction of power dissipation, reducedtransistor channel length, and reliabilityof gate dielectrics. Thus, maintainingchannel length and transistor thresholdvoltage increases circuit delay, decreasesclock speed, and degrades performance.The core using the lower supply-voltageconsumes lower average power whilestill meeting the performance deadlines.

For a fixed supply voltage level, lowpower techniques try to reduce the aver-age current drawn by the circuit. Voltagescaling techniques, on the other hand,scale the supply voltage to reduce powerconsumption. These techniques can bedivided into static voltage scaling anddynamic voltage scaling. So if there is asingle computation that needs to be exe-cuted by some deadline, it is always bet-ter to run the computation at a constantspeed (corresponding to the averagespeed required) than to change the speed(and correspondingly the voltage level)during the computation. Thus, each taskis executed at a static voltage level.

However, the level of this single volt-age may change from task to task. As aresult, this technique is ineffective whentight deadlines are present in systems. Inthese cases, performance can then beenhanced with reducing the thresholdvoltage. Of course, then greater leakagecurrent occurs. For analog and mixed-sig-nal devices, noise problems must beeffectively dealt with, as the operatingvoltage becomes lower. At the same time,maintaining capacitor capacity and mini-mizing parasitic capacitance will be chal-lenges upon further scaling of devices.

(Note: Another power optimizationtechnique is the system shutdown. Thesystem shutdown technique, thoughusable even with tight deadlines, is inferi-or to the supply-voltage reduction tech-nique when both techniques can be used.)

Logic style, integration techand core library choiceCore library. The macro performancemust be optimized to meet the lowpower macro objectives. Also, the core

libraries required for synthesis need tooperate at a low power rate. For exam-ple, a phase-locked loop (PLL) analogwas designed with low-power features.Read-only memory (ROM) inputs thelatched addresses, which are accessedonly if requested. ROM output data isheld until the next ROM read is execut-ed, reducing downstream switching.

The choice of integration technology.This is one of the driving forces behindthe big improvement in performance,functionality and power in integrated cir-cuits. For example, subthreshold leakagecurrents become a larger component inthe overall power consumption. Leakagecurrents are especially important in burstmode-type integrated circuits. The rea-son is that the system spends most of itstime in an idle or sleep mode. Smallersubthreshold leakage currents can reducethe standby power required.

Silicon On Insulator (SOI) technologywith its high-performance at low Vdd atthe various levels of design abstractionand its low parasitic capacitance could bean important solution. Novel structuressuch as dual gateSOI or verticalmetal-oxide semi-conductor-field-effect transistors(MOSFETS) mightbe needed. Also,novel switchingdevices such asquantum dot or sin-gle electron transis-tors are possiblefuture solutions.However, moreaccurate, compre-hensive, and easy touse TechnologyComputer AidedDesign (TCAD) andmodeling tools areneeded to developand implementthese solutions.

Logic style. Thelogic synthesisprocess to be powerdriven must observea power budget.Thus, the ASIClibrary used in thesynthesis processmust also includedrive strengths withsmaller devicewidths. This waypower can be mini-

mized on paths with non-critical timing.Moreover, the logic style in the ASIClibrary significantly affects the powerconsumption. Many techniques havebeen proposed to decrease the power dis-sipation over the circuit design. The mainfour techniques in this level could besummarized as:

• Low swing voltage,• Multi-threshold voltage,• Differences between values of

threshold voltage of p or nMOS transis-tor, and

• Charge recycling technique.Pass-Transistor Logic is used in mod-

ern very large scale integration (VLSI)applications to increase the speed and toreduce the power dissipation. This logicfamily has advantages compared to con-ventional static CMOS logic. Pass-tran-sistor circuits achieve important saving oftransient power and they are twice as fastas conventional static CMOS circuits. Onthe other hand, experimental results fromprototype integrated circuits (ICs) andpower supplies have demonstrated thatenergy-recovery CMOS logic circuits—

Low-Voltage Technology

Gate Level PowerCalculation & Methodology

Transistor Level PowerCalculation & Reduction

Power ModelingPower Design

Power Driven Synthesis

Logic Style

Power DrivenPhysical Design

RTL/Behavioral LevelPower MethodologyRTL Toggle Reduction

Architectural PowerAnalysis & RestructuringClock Gating

Power Verification

Fig. 1 Power saving techniques at various degreesof design abstraction

In

CLK

CLM1

F

O LG

M2

GCLK

CLK t1 t2 t3

A

O

G

GCLK

Timing DiagramA

Fig. 2 Sampled clock gating model and timing diagram

Technique SavingLow power synthesis 15%Clock gating 8%Logic/architectural changes 45%Voltage reduction 32%

Table 2

20 IEEE POTENTIALS

when combined with resonant or step-wise charging—can conserve significantcircuit energy for digital functions imple-mented in VLSI MOS technologies.

Adiabatic circuits achieve low energyconsumption by steering currents across

devices with low voltage differences.They also save by recycling the energystored in their capacitors. Adiabatic cir-cuits offer a promising alternative to con-ventional circuitry for low energy design.

Clock gatingThe clock distribution network can

consume anywhere from one-quarter toone-half of the active power in a design.Thus, attention must be given to the clockdistribution network. Techniques such asclock gating have traditionally been usedto manage clock distribution power.Moreover, in synchronous circuits, theclock signal switches at every clock cycleand drives a large capacitance. As aresult, the clock signal is a major sourceof dynamic power dissipation.

Clock gating is a technique thatreduces dynamic power consumption byselectively stopping the clock to portions

of the circuit that are inactive at certainperiods of time. This technique also elim-inates power distribution in the clock dis-tribution network. The clock is gated witha control signal that is low during periodsof inactivity (and high otherwise). It

works well for data-flow logic,where clocking requirements canbe predetermined at least onecycle ahead.

Figure 2 shows a simple modelfor a gated clock circuit. Themodel contains registers (MI) and(M2), combinational logic (CL)between input and output regis-ters, and the clock control circuit(F) that generates the control sig-nals to gate the clock. The outputof F (0) is an input to a level trig-gered latch (L).

The latch output (G) is ANDedwith the clock sig-nal to produce thegated clock signal(GCLK) whichclocks the registerM2. The flip-flopsare assumed to beedge triggered.Without loss ofgenerality, weassume that theedge-triggered ele-ments sample dataon the rising transi-tion. We alsoassume a singleclock. Under nor-mal conditions,

when M2 has to be clocked, theoutput of the clock control func-

tion (0) is high. This passes through thelatch L and appears at G when CLK islow. Since G is high, CLK appears atGCLK after the AND gate delay and M2is clocked. During idle conditions, whenM2 does not have to be clocked, the out-put of F (0) is low. This causes one inputof the AND gate to be low. Thus, GCLKremains low and M2 is not clocked. Forcorrect operation of the circuit, the gatedclock signal GCLK must be hazard free.GCLK is the logical AND of CLK andG. When the CLK is low, glitches on theG signal do not appear in GCLK.

While gating the clock can provideenormous power efficiency gains, theaddition of clock gating complicates theclock signal distribution. Thus, an effec-tive low power gated clock tree must becarefully structured within the logical andphysical design to reach the best solution.Another challenge with clock gating is

determining the conditions during whichthe clock to a register can be shut off.

Spurious toggle reductionOther approaches to power reduction

are 1) to minimize the power required toperform functions; and, 2) to minimizehow often the function needs to be exe-cuted. The switch and frequency of val-ues of primary input and output at thearithmetic units can also substantiallyaffect power consumption. Thus, variousmethods to minimize unnecessary togglesof the data values used in data path orarithmetic units from cycle-to-cycle havebeen devised.

First, just by minimizing cycle-to-cycle functional toggle requirements,power can be saved. In this method,next-cycle control signals are derived as afunction of the next-cycle function, alongwith the previous cycle-state. That is, if afunctional path is not required on the cur-rent cycle, ensure that all control pathsand data paths remain at the previouscycle’s state. This move eliminates allnode toggles.

Secondly, a common element in datapath processors is the bus multiplexer.The multiplexer selects one of severaldata buses to be driven onto a single out-put bus. If care is not taken, unwantedtransitions on multiplexer inputs canpropagate to the output buses and todownstream logic. This can occur evenwhen the multiplexer is not being usedduring the current cycle.

The standard approach to multiplexernode toggle reduction is to hold the previ-ous value or to force the multiplexer to aconstant state when not in use. However,when applied to heavily used multiplex-ers, this approach does not yield any sig-nificant power reduction. While power issaved when the multiplexer is not usedfor many cycles, if the multiplexer mustchange values frequently, no significantpower savings will be observed.

Thus, an alternative method was creat-ed for data path multiplexing. Thismethod guarantees that the multiplexeroutputs will switch once, and only once,during the cycle when they are needed.They will never switch on cycles whenthe multiplexer is not functionally needed.

In a normal data path design, differentbits of a bus will arrive at different timeswithin the cycle because of individualpath delay differences. These staggeredarrivals may result in repeated arithmeticor logical calculations downstream as aninput bus settles on the final value for thecycle. To minimize data path power,

sum

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cs

cs

cs

a

b

Full Adder

cb

cb

cs

cs

Fig. 4 Modified adder cell with bypass function

h 1

h 2

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bypass bit2

bypass bit3

Fig. 3 Bypass bit generation

AUGUST/SEPTEMBER 2001 21

inputs to arithmetic units, such as multi-pliers, shifters, and adders, should beapplied only once during the cycle theyare used. For these goals, IBM proposeda new transition-once multiplexer. Thetransition-once multiplexer ensures a sin-gle transition on the output bus per cycleby guaranteeing that data is propagatedthrough the multiplexer only when theinput data buses are valid and stable. Thetransition-once multiplexer holds the pre-vious value when the multiplexer is notselected or during transitions to a newvalue. If the multiplexer is not selected inthe current cycle, the output is held at theprevious cycle’s state.

Architectural analysis and restructuring

Low power correlator structure. Nowlet’s talk about the correlator in the CodeDivision Multiple Access (CDMA) com-munication systems being widelydeployed today. Direct Sequence SpreadSpectrum (DSSS) transmissions require ade-spreading stage within the standardreceiver block to recover the spread spec-trum signal. The correlator is used in theDirect Spread Code Division MultipleAccess (DS-CDMA) receiver for cellsynchronization, timing recovery, datarecovery and channel estimation.

The synchronization process deter-mines the location of a periodicallyoccurring marker (say N bits long, whereN may be as large as 256) transmitted byall transmitters (base station) in the sys-tem. For long spread spectrum codes, thecorrelation block can be a large portion ofthe receiver’s overall size, hence con-sume a considerable portion of the power.

A general correlator structure is theshift register storage. Within the shift reg-ister storage, there are potential powersavings that can be realized in the addertree by looking at the data statistics. Asthe data is shifted by one position, theprevious coefficient and the new coeffi-cient will remain the same for half thenumber of samples (in runs of length 2 orgreater). To capture this behavior wedefine, “bypass bits” (see Fig. 3) whichtell the adder stages if a term is notchanging. Thus, it has zero contributionto the difference between the present andnext correlation sum.

By storing the previous sum and iden-tifying the factors that are changing, wecan streamline the arithmetic operationto reduce the number of terms. Theoverall number of adders cannot bereduced as different codes change thelocations of inactive adders. But we can

shutdown the unused adders and limittheir power consumption.

Another approach to reduce powerdissipation is to reduce the activity in thestorage area. One way to reduce theunnecessary activity on the data lines is touse a register file (with pointer) imple-mentation instead of the n-bit wide shiftregister (Fig. 4). With this scheme, onlyone register out of the total of 2 m –1 willexperience clock and output transitionsfor each new sample. Because the globalbus feeds every register in the registerfile, minimizing the transitions on thisbus can reduce the overall power con-sumption considerably. A simple, buteffective coding technique to reducepower is the Bus Invert method. For a 6-bit bus, it reduces transition activity byapproximately 20%.

Low power SRAM architecture. Inpast years, a divided bit-line approachwas developed to reduce the power con-sumption in the Static Random AccessMemories (SRAMs). By grouping the Mcells and connecting the group to the bit-lines, the bit-line capacitance is reduced.This move reduces the active power con-sumption by about a factor of 2 at theexpense of a 4% increase in capacitance.Recently this divided bit-line approachwas generalized to a hierarchical dividedbit-line architecture. Based on simpledelay models, optimum levels ofhierarchy and the optimum number ofSRAM cells in a hierarchy were derived.Also, these theoretical results matched theexperimental simulation results. It showedthat for the optimum case, a 50-60%reduction in power consumption and a20% reduction in access time were gained.

Low power bit-serial Viterbi decoder.The bit-serial arithmetic can be adoptedfor the Add-Compare-Select (ACS)operation since the performance obtainedwith the bit-serialapproach is suitablefor the target speed.Although one canplace fewer bit-paral-lel ACS units andutilize them repeated-ly to attain the targetspeed, the area andpower of overheadcontrol circuits—such as selectors anda state metric memo-ry address genera-tor—is quite signifi-cant. Furthermore,the bit-parallelapproach requires very

high-speed memories for state metrics. A disadvantage of the bit-serial

approach is that extra memory elementsare required to store intermediate resultsof the ACS operation. This problem canbe solved by developing an area efficientstorage unit for state metrics based onthe register file architecture. Moreover,by adopting this register file-basedarchitecture instead of a simple architec-ture with shift registers, power efficientACS units with less switching activitiescan be obtained.

Low-power parallel FIR digital filters.Efforts have been directed towards low-power implementation of parallel finite-impulse result (FIR) digital filters. Inpast research, efficient parallel FIR fil-ters were developed, which require lesscomplexity and, thus, required lesspower consumption since they could beoperated with lower supply voltage.These filters, also, required a less-than-linear complexity increase in the numberof adders needed for a linear increase inthe level of parallelism.

Current research has determined twofurther improvements. First, out of a largenumber of possible parallel filter blocksof identical complexity, an appropriateblock can be selected depending on thefilter spectrum, such as low-pass or high-pass. Second, a more efficient quantiza-tion scheme was developed to encode thecoefficients in a power-of-2 form. Usingthe parallel filter block selection and newquantization scheme, power consumptioncan be reduced by 20%.

Asynchrony for low power architec-ture. The potential advantages of asyn-chrony for energy efficiency and lowpower are well-known: no clock distribu-tion power, no spurious transitions, auto-matic and perfect shut-off of idle parts,low peak current, automatic adaptation to

2m-1Registers

Ik

Ik+1

Ik+2

Ik+3

Ik+2m+1

clk

clk

clk

clk

clk

1

0

0

0

0

Multiply&

Add

Fig. 5 Register file concept

22 IEEE POTENTIALS

variations of voltage and temperature,flexible and modular architectures. Thus,asynchronous circuits are intrinsicallymore energy-efficient than clocked cir-cuits by a significant factor. Energy-effi-cient strategies will require a betterunderstanding of the energy efficiency ofalgorithms at the hardware, operating sys-tems and application levels. An importantadvantage of asynchronous design is thatit is very easy to vary the voltage over alarge range without risking malfunction-ing. Thus, one can choose to optimize forlow energy, or low delay, by adjustingthe voltage.

Low power DSP design forreconfigurable architecture

The time-varying nature of the chan-nel—flexibility demanded by 3G wire-less standards and mobility require-ments—make reconfigurable architec-tures attractive in low-power solutions.For example, a software-defined radiocan support multiple modulation wave-forms and multiple-air interface stan-dards, and have a configurable hardwareplatform that consumes low power.

Recently, most approaches to recon-figurable digital signal processors (DSPs)seek to maintain the flexibility of beingfully programmable. The goal is to devel-op a family of low power, programmableprocessors for embedded applicationssuch as encountered in communications,portable multimedia and space applica-tions. This way very-low levels of power(energy) dissipation (mW range) can beobtained using single-chip reconfigurablehybrid multiprocessors of mixed granu-larity. Achieving high-energy efficiencyrequires the elimination of the waste thattypically dominates energy consumptionin general-purpose programmableengines. For this purpose, we must 1)match computation and architecture, 2)preserve the locality inherent in algo-rithms, and 3) exploit signal statistics.Moreover, providing programmability atjust the right granularity (instruction,functional module, data path or gate)makes it possible to eliminate virtuallyall overhead. It also makes it possible toexploit other energy-reducing tech-niques, such as parallelism, pipeliningand dynamic voltage scaling. To achievethis goal, a number of approaches andtechniques can be integrated:

1. Combining multiple computationalgranularity levels on the same die,

2. “On-the-fly” processor compositionleads to orders of magnitude in powerreduction,

3. Template for “domain-specific”processors,

4. Data-driven synchronization, 5. General-purpose embedded proces-

sors with a power-scalable performance, 6. On-chip integrated and efficient

dc-dc converters, 7. low power embedded Program-

mable Gate Arrays (PGAs) and reconfig-urable data paths,

8. Globally asynchronous, locally syn-chronous design, low-swing interconnect,adaptive voltage and clock frequencyscaling, and

9. Quantifiable design methodologysupports design-space exploration.

Subsequently, the design of lowpower DSP-based ASIC for high-perfor-mance applications requires appropriatelystructured tradeoffs. Satisfying thedemand at low power, requires attentionto power dissipation throughout thedesign of ASIC like the Multi-purposeMODEM Chip (MMC). Significanttradeoffs could include algorithms thatare optimum from a performance per-spective but that dissipate excessivepower versus sub-optimum algorithmsthat dissipate less power.

Conclusion Low-power consumption requires

attention to the entire design process.This includes the integration technology,the choice of ASIC library/logic style andthe architectural level design techniques.Even though power reduction is expectedat the various levels of design abstraction,and various low-power techniques havebeen successfully employed in manyreal-life applications, basic correlationmust exist among these techniques. Inaddition, for deeper understanding muchwork is required. There must be feedbackof observation for power reduction resultsamong the degrees of design abstraction.

Read more about it• IBM Micronews. [Online].

Available: http//: www.chips.ibm.com.• Semiconductor Industry Association,

“International Technology Roadmap forSemiconductors.” [Online]. Available:http://www.public.itrs.net.

• H. Elwan, H. Alzaher, and M.Ismail, “A new generation of global wire-less compatibility, “ IEEE CircuitsDevices Mag., vol. 17, Jan. 2001.

• M. Goez and N.R. Shanbhag, “Alow-power VLSI design methodology forhigh bit-rate data communications overUTP channel,” in Proc. IEEE Int. Symp.Circuits and Systems, 1998.

• L. Benini, A. Bogliolo, and G. DeMicheli, “A survey of design techniques forsystem-level dynamic power management,”IEEE Trans. VLSI Syst., v. 8, June ’00.

• N. Raghavan, V. Akella, and S.Bakshi, “Automatic insertion of gatedclocks at register transfer level,” in Proc.12th Int. Conf. VLSI Design, 1999.

• M. Pedram and Qing Wu, “Designconsiderations for battery-powered elec-tronics,” in Proc. 36th DesignAutomation Conf., 1999.

• M. Sgroi, J.L da Silva, Jr., F. DeBernardinis, F. Burghardt, and J. Rabaey,“Designing wireless protocols: methodol-ogy and applications,” in Proc. 2000IEEE Int. Conf. Acoustics, Speech, andSignal Processing, 2000.

• F. G. Wolff, M. J. Knieser, D.J.Weyer, and C.A. Papachristou, “High-level low-power FPGA design methodol-ogy,” in Proc. IEEE 2000 Nat. Aerospaceand Electronics Conf., 2000.

• I. Hong, D. Kirovski, Gang Qu, M.Potkonjak, and M.B. Srivastava, “Poweroptimization of variable-voltagecore-based systems,” IEEE Trans.Computer-Aided Design, Dec. 1999.

• D. Radhakrishnan, “Low-voltagelow-power CMOS full adder, “IEE Proc.Circuits, Devices and Systems, vol. 148,Feb. ’01.

• S. Sriram, K. Brown, and A. Dabak,“Low-power correlator architectures forwideband CDMA code acquisition,” inConf. Record 33rd Asilomar Conf. Signals,Systems, and Computers, vol. 1, 1999.

About the authorsHyeongseok Yu received his BS

degree and MS degree from Sung KyunKwan University in Suwon, Korea in1997—all in electrical engineering. He iscurrently working towards his Ph.D.degree at Sung Kyun Kwan University.

Professor Jun-Dong Cho received hisBS in EE from Sung Kyun KwanUniversity in Seoul, Korea, his MS fromPolytechnic University (Brooklyn, NY)and his Ph.D. from NorthwesternUniversity (Evanston, IL) both in comp.science. He was a Senior CAD Engineerat Samsung Electronics, Co., Ltd.,Buchun, Korea. He is now an AssociateProfessor of Electronic Engineering atSung Kyun Kwan University. He wrotethe book, High-Performance DesignAutomation of MCMs and Packages,World Scientific in 1996. He has been aguest editor of VLSI DESIGN for sever-al special issues. He is an IEEE SeniorMember and is visiting IBM. T. J.Watson Research Center (NY).