low cost bumping for rfid chips

Certified DIN EN ISO 9001

Low-Cost RFID IC Packaging and Assembly Workshop

November 14th 2005

Low Cost Bumping for RFID Chips

Dr. E. Zakel; T.Oppert

www.pactech.de


• Electroless Ni/Au Bumping

– Market share & Usage– Process/Yield/Reliability– Equipment– Assembly– Applications

Content


Locations Worldwide

Italy

DenmarkSweden

Singapore

TaiwanThailand Application Center Philippines

Pac Tech USA IncSanta Clara, CA

Boston

Pac Tech GmbHBerlin/ Nauen

TokyoFukui

ManufacturingFacilities

Distributor/ Rep. Office

Finland

Korea

IsraelChina

1995 2005


II

ElectrolessElectroless Ni/Au BumpingNi/Au Bumping

Market Share & UsageMarket Share & Usage


Worldwide Use of Electroless Ni/Au

Distribution

USA (30%)Europe (40%)Asia (30%)

Memory 12.5%

RFID 20%

Pass. Comp./CSP's20%MOSFET 10%

LCD Driver 2.5%

ASIC 22.5%

Medical 12.5%

Applications

Production 50%Qualification 30%Prod. Ramp Up 20%

ImplementationStatus

RFID – Growth !


♣ Europe

- 1 subcontractor bumping facility

- 4 wafer foundries

♣ Asia

- 4 subcontractor facilities

- 5 wafer foundries

♣ USA

- 2 subcontractor facilities

- 3 wafer foundries

WorlwideWorlwide Implementation of electroless Ni/Au Implementation of electroless Ni/Au for Al pad for Al pad metalizationmetalization


Main products using electroless Ni/Au

- ASIC (Sensors)- LCD Drivers- PowerMOS (Automotive)- MOSFET- Protection devices (Passives) CSP‘s, WLCSP‘s- Memories and memory modules- Consumer electronics- Battery control (Mobile Phone)- Medical (Ear phone)

• Products under very high price pressure (RFID)


2000 2001 2002 2003 2004 2005 2006 Year

Gro

wth

JapanSubCon

STWKorea

USAMemory

PacTechUSA

SubCon

Europe

RFID

Business Development – Licenses of Pac Tech

Asia

&

Europe

Chinan.a.

AsiaWL-CSP


IIII


Process/Yield/ReliabilityProcess/Yield/Reliability


Bumping methods

lowMassNi/Au + Solder

n.a.DevelopmentElectroless Pd

highsmall/mediumproduction

Au-Stud

highmass productionElectroplated Au

howmass productionElectroless Ni/Au

CostProduct Scale


Comparison of Bumps for ACF/ NCP bonding

Electroplated Au Electroless Ni/ Au

- Low Hardness

- State of the Art

- Single Wafer Process

- Lowest Cost

- Higher Hardness Requires Modified Assembly Parameters

- Batch Process up to 50 Wafers

- Volume Production for

RFID Applications

Si - Wafer Si - Wafer

Passivation Passivation

Al - Pad Al - PadPlating Base


Backside Coating

Pad Cleaning

Pad Activation

Electroless Nickel

Flash Gold

Coating Removal

Under Bump Metal Process

Electroless Plating of Ni/Au Bumps 1/2


Backside Coating

Aluminum Cleaning

Zincate Pretreatment

Electroless Nickel

Immersion Gold

Coating Removal

Under Bump Metal Process

Electroless Plating of Ni/Au Bumps 2/2


25µm Ni/Au UBM on RFID-Wafers 1/2

Customer A


20µm Ni/Au UBM on RFID-Wafers 2/2

Customer B


Shearforce Measurements of 25µm Ni/Au

Shearvalue: 725g

Shearheight @ 9µm

Customer A


Bump Yield Ni/Au September 2005Yi

eld

(%)

90

91

92

93

94

95

96

97

98

99

10050

3133

; 109

13

5031

32; 1

0916

4848

28; 1

0917

4848

19; 1

0918

5031

20; 1

0919

5034

89; 1

0920

5031

31; 1

0921

5037

70; 1

1012

5037

68; 1

1013

5037

67; 1

1014

5037

69; 1

1015

5037

69; 1

1015

HH

SS

R.0

0; 1

1040

HH

ST2

.00;

110

41

HH

SS

W.0

0; 1

1094

HH

SS

W.0

0; 1

1094

HH

SS

Y.0

0; 1

1095

5037

71; 1

1096

5037

72; 1

1097

HH

ST1

.00;

111

33

HH

SS

S.0

0; 1

1134

HH

SS

S.0

0; 1

1134

HH

ST0

.00;

111

35

HH

ST4

.00;

111

78

HH

SS

T.00

; 111

79

Customer A

Lot #


80,00

85,00

90,00

95,00

100,00

105,0010

932

1094

810

964

1098

110

987

1099

411

005

1101

711

023

1103

511

057

1106

311

081

1108

711

101

1110

611

122

1113

811

151

1115

711

167

1118

411

191

1119

611

201

Process #

Yiel

d (%

)

98,00

Bump Yield Ni/Au September 2005Customer B


Process Time September 2005

0,00

1,00

2,00

3,00

4,00

5,00

6,00

7,00

8,00

9,00

10,00

1093

210

945

1095

510

967

1098

410

991

1100

311

009

1102

111

034

1105

711

063

1108

011

086

1110

011

106

1112

111

136

1115

011

156

1116

611

184

1119

011

196

1120

2

Process #

Day

s

Customer B


Chip size: 2.5 x 2.5 mmNumber of I/O's: 4Pitch: 400 µmAssembly type: ACFSubstrate: Polyester

Reliability:· 40°C, 80% rH: 1000 hours - no failure· 125°C 1000 hours - no failure· mechanical torque(ISO) 500 cycles - no failure

Number of samples for test conditions: 100

87 REL

Reliability - Smart Label

Customer C


IIIIII


EquipmentEquipment


Pacline 300 - A50

8 Plating Systems in the Field


♣ Maskless Process

♣ No Sputtering

♣ Low Initial Capital Investment

♣ Quality/Reliable/Proven Chemistries

♣ Suitable for Solder Bumping & Adhesives

♣ Wire bondable Interface

♣ Less cost than Electrolytic Plating

♣ Fastest and Most Cost Effective Method

Electroless UBM AdvantagesElectroless UBM Advantages

• 150 Wafers / hour• 4“ – 12“ Capability• SECS GEM• 300mm Handling• SPC Sofware


Pac Tech Worldwide Production Capacity

Q1* Q2* Q3* Q4* Q1* Q2* Q3* Q4*

Pac Tech Nauen

PacLine 200 A25 40.000 40.000 40.000 40.000 40.000 40.000 40.000 40.000

PacLine 300 A50 ____ ____ ____ ____ 5.000 25.000 75.000 75.000

Japan (Alpha Bumping Technology)

PacLine 200 A25 40.000 40.000 40.000 40.000 40.000 40.000 40.000 40.000

PacLine 300 A50 ____ ____ ____ ____ ____ ____ 25.000 75.000

Pac Tech USA

PacLine 300 A50 ____ ____ ____ ____ 5.000 25.000 75.000 75.000

Total 80.000 80.000 80.000 80.000 90.000 130.000 255.000 305.000

Total Capacity per Year 320.000 Wafers 780.000 Wafers

2004 2005


IVIV

AssemblyAssembly


Low Cost Flip Chip – Attach for Smart Cards / Smart LabelsLow Cost Electroless Ni/Au Bump

1.) Leadfree Soldering 2.) Anisotropic Conductive Adhesive

3.) Isotropic Conductive Adhesive 4.) Nonconductive Adhesive

Low Cost Flip Chip.ppt

Laser Polymer Curing (ICA)

Laser Reflow (LaPlace) Laser Polymer Curing (ACA, ACF)

Laser Polymer Curing (NCA, NCF)


Chip Assembly on RFID- Cards and Labels

• Module– Wire bonding - Flip Chip

• Bare Die Assembly onto Antenna– Wire bond - Flip Chip

168 LAP


Advantage of Flip Chip Technology

• Reduction of Card / Label Thickness– by eliminating wire bond loop

• Cost Reduction

169 LAP


RFID Substrate and antenna material

• Limitation on selection of flip chipprocesses– assembly temperature below TG of substrate

material– joining technology compatible with antenna

material

174 LAP


Challenges of Flip Chip Attach in RFID- Cards and Labels

Solutions/advantages of laser soldering/curing• Low cost materials

– Substrate materials• PVC,PET, PP,....., Paper• TG below 100 °C• Material Property: flexible

– Antenna material• bare Copper (etched, coated wire)• Aluminium• Printed Antenna


Flip Chip Bonder - LAPLACE


VV

ApplicationsApplications


Applications

Ni/Au on Copper

RFID-Tag


FC with ACF - Smart Label


Flip chip on coil for contactless smart cards


Chip-Card-IC on Copper-Coil

Chip: Mifare, Phillips

Coil: Etched Cu-Coil

Contact: Ni/Au + Leadfree Solder

or

NCP, ICP ConductiveAdhesive


Flip Chip Modules for contactless Smart Cards

Substrate handling: reel to reel

Assembly: Laplace soldering Flip chip attach

low cost bumping for rfid chips

Documents

field certified din

year certified din en

niau customer

niau ubm

content electroless

bump yield niau

process time

low cost bumping