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Loop Bandwidth Optimization and Jitter MeasurementTechniques for Serial HDTV Systems

Atul Krishna Gupta, Aapool Biman and Dino ToffolonGennum Corporation

Abstract:

This paper describes a system level optimization of a studio serial digitalinterface for uncompressed High Definition Television (HDTV). The HDTV datarate is 5.5 times that of Standard Definition Television (SDTV) which allows littledesign margin for jitter. An intuitive time domain discussion of different sources ofjitter is presented. This paper provides design guidelines for video sources,routers, digital signal processing units with serial interface, distribution amplifiersand production switchers. These guidelines reinforce the SMPTE 292M standardand other recommended practices, e.g. EG33-1998. Using commerciallyavailable general-purpose test units and some custom built boards it is shownthat some of the important jitter parameters associated with serial HDTV can beeasily measured.

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1. Introduction

The HDTV signal is standardized by the SMPTE 292M standard [1]. SMPTE292M is very similar to SMPTE 259M [2] with respect to several electricalcharacteristics. The randomizing polynomial and channel coding pose the samepathological signal challenges [3]. Table 1.1 compares jitter specifications for theSMPTE 259M and 292M standards. Figure 1.1 graphically illustrates the SMPTE-292M jitter specification.

Table 1.1Jitter Parameter SMPTE 259M-1993 SMPTE 292M-1996B1 (f1) (Timing jitterlower band edge)

10Hz 10Hz

B2 (f3) (Alignment jitterlower band edge)

1kHz 100kHz

B3 (f4) (Upper bandedge)

>27MHz >148.5MHz

A1 (Timing jitter) 1.0UI 1.0UIA2 (Alignment jitter) 0.2UI 0.2UITest Signal Colour bar test signal Colour bar test signalClock divider ratio (n) Except 10 Except 10 (preferred)

Jitter Frequency for HDTV

Sinusoidal InputJitter Amplitude

10HzB1 (f1)

100kHzB2 (f3)

148.5MHzB3 (f4)

0.2UI A2

1.0UI A1

-20dB/decade slope

20kHz (f2)

Figure1.1 Jitter template for SMPTE 292M

Timing Jitter

Alignment Jitter

According to the above table, the source should not have jitter more than 1UI(673ps) in the frequency band above 10Hz. The alignment jitter should not bemore than 0.2UI (135ps) in the frequency band beyond 100kHz. The alignmentjitter lower frequency has changed from 1kHz to 100kHz from SMPTE 259M toSMPTE 292M. Even though the alignment jitter is defined from 100kHz to greater

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than 1/10th the serial clock frequency, it is important to make sure that the jitter isnot more than 0.2UI up to 1/2 the serial clock frequency. This is because the SDIsignal may have jitter in that band which could cause errors when it is sampled atthe receiver or the re-timer. There could be fair amount of jitter present in thefrequency band around 1/2 the serial clock frequency, because any data dutycycle distortion appears as jitter at 1/2 the serial clock frequency.

The need for video field and line synchronization, and the unique channel codingmakes the SMPTE standard different from other digital communication protocols,e.g. SONET, Fiber channel etc.

2. The Studio Model

A simplified studio model is illustrated in Figure 2.1. Distribution Amplifiers (DAs),Digital signal processors (DSP) and Routers can be used several times in onesignal stream. All the sources have to be synchronized to the master clock or thehouse synch. House synch is used to synchronize lines and frames so thatswitching does not create partially blank screens during multiplexing of varioussources.

Because both front-end (sources) and back-end (production switcher) aresynchronized with the same master clock, it is important to control jitter andprovide sufficient input jitter tolerance in individual blocks to prevent errors.

House synch for Genlock

Camera

VTR

Other sources

SDI Sources

DistributionAmplifier (DA)

N inputs X M outputs

Router

DigitalSignal

ProcessingUnit

ProductionSwitcher

Monitor

Transmitter

Figure 2.1 A Simplified Model of a TV Studio

3. Sources of Jitter and Their Frequency Spectrum

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Bandwidth limited devices in the signal chain e.g. cable drivers, cable equalizersand crosspoints all add jitter. Let us assume that there is a NRZI signal passingthrough a bandwidth-limited device. Figure 3.1 shows the generation of phaseerror by bandwidth limited circuits in the time domain.

R=75, C=4pFBandwidth limited

channelInput Output

0.1UI

-0.1UI0.0UIOutput

Phasetime

Pseudo Random Pathological (27 us) Pseudo RandomJitter

Histogram

Figure 3.1: Illustration of time domain jitter introduction in a bandwidth limitedsystem. (A) A bandwidth limited circuit. (B). The waveform of the input and output of a bandwidth limited system. (C) The eye diagram of the waveform in (B). (D) Thephase plot with respect to time.

(A)

(B)

(C)

(D)

Phase =0 UI Phase =0 UI Phase =0 UI Phase =-0.5 UI Phase =0 UI

Input

Output

Zerocrossing

Shiftedoutputto determinephase error

Input

Output

The jitter introduced from this effect is a systematic jitter and it accumulates asarithmetic addition in a cascaded system. In some cases, it could subtract aswell, however to build a robust system, we have to consider that it adds in everypass. This type of timing problem is also known as inter symbol interference (ISI).

Most types of equipment used in the studio are based on phase locked loops(PLLs) because they are either synchronized to the house synch or to thereceived serial digital data. Depending upon the loop bandwidth (LBW) of thePLL, low frequency jitter will be passed and high frequency jitter will be filtered.Figure 3.2 shows a typical second order traditional PLL [4]. White noise in theVCO is assumed. Figure 3.2(C) shows the typical open loop voltage controlledoscillator (VCO) and phase locked loop VCO phase noise, which shows that thenoise is also present within the loop bandwidth. The pathological pattern, whichis unique to SMPTE signals, may last as long as the active video line. Similar tobandwidth limited circuits, the PLL could also have time domain jitter as shown inFigure 3.1(D). This is especially true for data recovery circuits, which extractclock from data, and are inevitably pattern dependent. The noise in PLLs insideserializers is not directly related to the data pattern because the PLL locks on toa clock, which does not have any pattern. However, board noise is often relatedto the data pattern, and thus could introduce jitter which has similar time domaincharacteristics as shown in Figure 3.1.

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Delay in most microchips is a function of the temperature. When the temperaturechanges over time, the output phase changes. However, the temperature changein microchips is slow, and the drift in the output phase happens slowly. This kindof jitter will fall in “wander” category, and does not pose any problem. Whileevaluating any unit for jitter, it is recommended for the unit to be temperaturestabilized to isolate timing jitter and alignment jitter from wander jitter.

Phase Detector Charge pump VCOLoop FilterInputPhase

OutputPhase

Frequency

Gain

White Noise

Frequency

Noise

Open loop VCO noise spectrum (1/f2 noise)

PLL VCO noise spectrum

Integrator pole Loop Bandwidth Pole

(A)

(B) (C)

0db

-20dB/decadeSlope

Loop bandwidth pole

Figure 3.2 Intrinsic jitter generation in a typical PLL. (A) Typical linear PLL. (B) Jitter transfer function. (C) Noise spectrum density of the typical PLL.

4. Jitter Measurement Techniques:

4.1 Timing and Intrinsic Jitter Measurement:

The clock extractor method is generally used to measure jitter. The timing jitter ismeasured with a clock extractor of 10Hz LBW and alignment jitter is measuredwith 100kHz LBW clock extractor. It is difficult to attain a clock extraction LBW of10Hz without adding the intrinsic jitter of the clock extractor. As an alternate, werecommend measuring the intrinsic jitter of the individual units as shown inFigure 4.1. This is based on the assumption that the timing jitter of a device canbe approximated to the intrinsic jitter of the device. The intrinsic jitter is theamount of jitter present in the entire jitter frequency spectrum with respect to aclean reference input. The timing jitter excludes jitter content in the frequencyband from DC to 10Hz. Thus, intrinsic jitter overestimates timing jitter. However,in the case of a PLL (Figure 3.2), the presence of a integrator pole reduces thecontent of the jitter in the lower frequency band. In most cases the integrator poleoccurs beyond 10Hz. As long as this assumption is true, timing jitter is very closeto the intrinsic jitter. Figure 4.2 illustrates intrinsic jitter, timing jitter and alignmentjitter

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Any HDTV source

Jitter Reconditioning Unit

ReceiverLBW=4.2MHz

Parallel Clock PLLLBW < BW of DUT

SerializerLBW=1.41MHz

Clock Multiplier

Device UnderTest (DUT)

With Known LBW

Figure 4.1 Intrinsic jitter measurement setup

CSA803 Scope

Ch 1

DirectTrigger

Index

Single ended signals

Differential signal

Parallel data

Frequency

Intrinsic Jitter

Timing Jitter

Alignment Jitter

10Hz 100kHz 1/2 Data Rate1 / Persistence Time

Figure 4.2 Intrinsic, Timing and Alignment Jitter Spectrum

NoisePower

It is important to verify that the LBW of the jitter-reconditioning unit is much lowerthan the LBW of the device under test. If the LBW of the jitter reconditioning unitis greater than the device under test and if there is fair amount of jitter present inthat frequency band, the trigger will have more jitter than the device under test. Inthis case, the intrinsic jitter measurement will be more than the actual jitter of thedevice under test. Figure 4.3 illustrates a case where a cleaner PLL with narrow

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LBW is measured with a source having jitter beyond the LBW of the device undertest.

Source Jitter Spectrum

Jitter Reconditioning Board Jitter Spectrum

Device Under Test Jitter Spectrum

Measured Intrinsic Jitter Not Due to DUT

Figure 4.3 Incorrect choice of LBW in Jitter Reconditioning Board

f

f

f

f

NoisePowerSpectrum

NoisePowerSpectrum

NoisePowerSpectrum

NoisePowerSpectrum

The jitter reconditioning unit must be checked for its own intrinsic jitter before itcan be used to precisely characterize other units. A pristine bit error rate testerwas used to test the jitter reconditioning unit. We also verified the intrinsic jitterusing a special signal pattern programmed in the bit error rate tester, whichaccurately models the SMPTE pathological signal.

A jitter-reconditioning unit was realized with a LBW of approximately 1.0kHz at0.2UI input jitter modulation. The particular PLL which was used, with a voltagecontrolled crystal oscillator (VCXO), behaved partially as a slew PLL (Section 5)when used with a specific loop filter to achieve low LBW. The intrinsic jitter of theunit measured was approximately 60ps p-p for 223-1 pseudo random pattern and70ps p-p for pseudo pathological pattern.

4.2 Alignment Jitter:

The high frequency (above 100kHz) component of the timing jitter is classified asalignment jitter. The limits for the alignment jitter are tighter than those of timingjitter. As a result we may have to isolate the alignment jitter if timing jitter is morethan the SMPTE alignment jitter limit, to make sure that the unit is testedaccording to SMPTE specifications. The alignment jitter can be tested using acalibrated 100kHz linear clock extractor.

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To measure the alignment jitter in accordance with the SMPTE guidelines, wedevised a unit using a wide LBW clock recovery circuit. The 100kHz LBW wasprecisely set by a secondary PLL locked to the clock recovery circuit’s extractedclock as shown in Figure 4.4. In most cases, the intrinsic jitter measurementalone is sufficient. In Section 6.3.2, it is mentioned where this measurement isabsolutely required. Using a pristine data source, we measured alignment jitter ofapproximately 30ps for pseudo random pattern and 50ps for pseudo pathologicalpattern. This could be considered as the intrinsic jitter of this test setup. It is notobvious whether root-mean-square (rms) or arithmetic subtraction should bedone to find the true alignment jitter of the device under test. We recommendmentioning the intrinsic jitter of the test instrument while describing jitter of anydevice.

Clock Recovery Circuit

LBW=1.41MHz

DifferentialInput

BypassOutput

CSA803 Scope

VCO

VCO output

Div 2

PhasefrequencyDetector

ChargePump

Loop filterLBW= 100kHz

BufferExtracted

Clock

Div 2

Ch 1

DirectTrigger

100kHz Clock Extractor Board

Figure 4.4. Alignment jitter measurement using a clock extractor

DeviceUnderTest

5. Slew Phase Lock Loop

Most PLLs used in electronic circuits are linear. Linear PLLs are thoroughlycovered in the literature. A brief discussion of a slew PLL used by Gennum ispresented in this paper. A slew PLL is a non-linear PLL where the output phasevariation is slew limited. A slew PLL offers significant advantages for SMPTE SDIsignals over linear PLLs. In Section 6, bandwidth optimization is described whereeither a linear PLL or slew PLL could be used.

While designing a PLL, there are two main objectives, jitter attenuation andVCO/board noise immunity. The jitter attenuation is achieved by lowering theLBW whereas noise tolerance is achieved by increasing the LBW. These twocontradicting requirements are conveniently met with the slew PLL.

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Figure 5.1 compares linear and slew PLLs. For a fair comparison, the phase slewof the slew PLL and LBW of the linear PLL are chosen such that at 0.2UI inputjitter modulation, both achieve 3dB1 attenuation at 1.4MHz modulation frequency.The jitter transfer function is plotted at 2.8MHz to show how the PLL attenuatesinput jitter at higher frequency. It can be seen that the output jitter of the slew PLLattains a maximum and then it is limited. This is an attribute of the non-linearitypresent in the slew PLL.

A linear PLL is unaffected by the input jitter modulation index. The slope of thejitter transfer line can be calculated by the jitter transfer function of a first orderlow pass filter.

Consider, the slew PLL transfer function at 2.8MHz, the 3dB attenuation occursat 0.1UI input jitter modulation. In other words, if the input jitter modulation islowered, the 3dB LBW increases. For an infinitesimal small input signal, the slewPLLs have infinitely large LBW, where as the LBW of the linear PLL is fixed. In acareful design, the intrinsic VCO noise and board interference can be consideredas a small signal noise. As we know that the higher LBW accounts for cancelingmore VCO noise, the PLLs with wider LBW tend to be more robust. Therefore,we believe that slew PLLs are more robust than the linear counterparts.

Because of the non-linear characteristics, the slew PLL achieves higher jitterattenuation in the presence of large input jitter while providing small signalVCO/board noise immunity.

In this paper, if bandwidth of any slew PLL is mentioned, unless otherwise noted,it is defined at 0.2UI (135ps) input jitter modulation.

1 The 3dB bandwidth of a non-linear system cannot be defined as it can bedefined for the linear system. We define 3dB bandwidth as peak to peak jitterattenuation. For example if the input jitter is modulated at 0.2UIp-p then the 3dBjitter attenuation will result in 0.141UIp-p output jitter.

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Input Jitter (UI)

OutputJitter (UI)

0.00.10.0

0.1

0.2 0.3 0.4 0.5

At 2.8MHz

Input JitterModulationAt 1.4MHz

Linear PLL

Slew PLL

0.2

0.3

0.4

0.5

Figure 5.1 Transfer functions of Linear and Slew PLL

6. LBW optimization for different units in the Studio

As mentioned in Section 2, several of the units could be cascaded in a studio. Insuch a signal chain, the jitter will accumulate from unit to unit. For error freeoperation, the LBW of the receiver of the subsequent units should be wider totrack the accumulated jitter. Gennum recommends the bandwidth ranges shownin table 6.1 for the different units. This scheme will guarantee a trouble freeinterface between units.

Table 6.1Type of Unit Bandwidth RangeTransmitter (Serializer) 1Hz-100kHzRe-timer 500kHz-2MHzReceiver (De-serializer) 3MHz-6MHz

6.1 Video Sources:

In the studio, we define a source as a unit, which generates serial digital datae.g. cameras, VTRs etc. For synchronous use, it has to be genlocked to thehouse synch. Generally a very stable controlled crystal with very little intrinsicjitter is used for this purpose. Figure 6.1.1 shows a very simple diagram of asource.

The house synch reference could have jitter. The specification on thesynchronization pulse is mentioned in RP 154. The genlock utilizing a VCXO maybe used with very low LBW (<10Hz) such that the recovered parallel clock (p-

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clock) meets the SMPTE 292M jitter specification where jitter is measured intime, and A1=673ps and A2=135ps (Table 1.1). Ideally, the jitter on the genlockgenerated parallel clock should be much better than the SMPTE specifications toaccommodate jitter accumulation in the serializer and subsequent cascadedunits. The design of the genlock circuit is beyond the scope of this paper.

Because the parallel clock is derived from a clean VCXO, there is no need tofurther filter the jitter using the PLL in the serializer. In this case, the optimumbandwidth recommended by the manufacturer can be used.

Serializer &Cable Driver

LBW=(129Kz-1.4MHz)

Genlock PLLV C X O

Data Source

0.05 UI2 UI

Fig 6.1.1 An HDTV source

House Synch

Parallel clock cleanreference signal

6.1.1 Jitter Characterization of the Video Sources

The intrinsic jitter of the serializer output can be measured using the TektronixCSA 803 scope, triggered by the genlocked parallel clock. The output of theserializer could have a parallel clock jitter component, which may not be seen inthis case, as it will be synchronous to the parallel clock. To accurately measurethe jitter, we recommend multiplying the parallel clock to the HDTV rate, andusing this to trigger the serial data stream. However, the multiplied clock may addsome jitter. The jitter reconditioning unit (Figure 4.1) mimics a video source. Italso has an on-board clock multiplier. Table 6.1.1 summarizes the achievablejitter measurements of these units.

Table 6.1.1Video Pattern Intrinsic jitter of the

serializer at 129kHz LBWSMPTEspecification

673ps (Timing)135ps (Alignment)

Colour bars 30ps-60psPathological 40ps-60ps

Since the intrinsic jitter is less than the SMPTE alignment jitter specification,there is no need to isolate alignment jitter.

6.2 Routers

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A simplified router is shown in Figure 6.2.1. The cable driver, cable equalizer andthe crosspoint can be modeled as a bandwidth limited channel. Figure 6.2.2shows the jitter addition and jitter filtering inside a router. It is assumed that theequalizer jitter is 0.2UIp-p at the input of the re-timer and the source is clean.

During the pseudo random section of the data pattern, the jitter is attenuated.During the pathological section, the re-timer follows the input jitter. The time ittakes to follow the input jitter is decided by the LBW. If LBW is set low, it ispossible to reduce the jitter of the router, however, it will take significant time tosettle during synchronous switching. In synchronous switching, the worst casephase offset could be 0.5UI. If it takes several lines to recover the 0.5UI step,then during this time, the phase offset will look like input jitter. If the phase offsetis more than the input jitter tolerance, errors will result. We believe the bestcompromise is to set the LBW between 500kHz to 2MHz.

Equalizer

Cross Point

Re-timer &Cable Driver

Equalizer

Equalizer

Re-timer &Cable Driver

Re-timer &Cable Driver

Figure 6.2.1 Simplified Router architecture

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0.05UI

-0.05UI

0.0UIOutputPhase

time

Pseudo Random Pathological (27 us) Pseudo Random

Input phase of the Re-timer

Output phase of the Re-timerPseudo random pattern output

peak-peak jitter

Pathological patternoutput peak-peak jitter

Figure 6.2.2: Illustration of jitter filteringin a router

Due to the synchronous lock time specification we do not recommend using avery narrow LBW. Conversely, if very high LBW is used, some of the highfrequency jitter will be passed onto next unit in the chain, causing jitteraccumulation.

The jitter peaking in re-timers is usually less than 0.1dB, which addsapproximately 1% jitter. Thus the effects of jitter peaking could be ignored inmost cases.

6.2.1 Jitter Characterization of Routers

An application circuit board containing an equalizer and a re-timer(LBW=1.4MHz) can be used to model the router. The intrinsic jitter of the routercan be characterized according to the Figure 4.1. Table 6.2.1 summarizes theachievable intrinsic jitter for 0m and 100m of Belden 8281 cable between thejitter reconditioning unit and the device under test.

Table 6.2.1Video Pattern 0m Belden 8281 Cable 100m Belden 8281 CableSMPTEspecification

673ps (Timing)135ps (Alignment)

673ps (Timing)135ps (Alignment)

Colour Bars 30ps-60ps 30-80psPathological 40ps-70ps 40-100ps

The jitter added by the crosspoint can be assumed as bandwidth limited andsystematic and should be added to the intrinsic jitter for worst case analysis.

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6.3 De-serializer and Serializer Units

A de-serializer and serializer unit receives a serial digital signal, and converts itinto 20 bit words. A parallel clock is also generated which is 1/20th the serial clockrate. Digital signal processing is then done on the parallel, 20 bit data, after whicha serializer converts the 20 bit words into the serial digital stream.

The interface between serializer and de-serializer is a 20 bit parallel bus.Because of this interface, there is a built-in data buffer, which increases the jittertolerance (specified as set-up and hold time) between these two microchips.Ideally this could add +/-10 bits of data buffer. However, because of slowerrise/fall times and set-up and hold times, +/-5 bits of data buffer is usuallyachieved. The LBW of the de-serializer should be chosen between 3MHz to6MHz and the LBW of the serializer should be chosen less than 100KHz. Thiscombination allows the input jitter tolerance template to overlap with the jittertransfer function. If the receiver’s LBW is 4.2MHz and the router’s LBW is1.4MHz, the receiver will follow the jitter of the router during the pathologicalvideo line. Both, the receiver and re-timer could be based on the slew PLL. Thephase at the re-timer at 1.4MHz slews slowly so that 4.2MHz receiver couldclosely track it even for the worst case manufacturing LBW tolerances. Thechoice of these two LBWs is key to a robust system design.

The parallel clock interface is single ended and the presence of single ended 20bit parallel data could add fair amount of systematic jitter (approximately 0.7UI)during pathological signal. Noise resulting from parallel DSP microchips isanother source of systematic jitter introduction.

We can differentiate the De-serializer/Serializer units as being of two types. Thefirst type filters the jitter in the parallel clock using a VCXO/PLL and the secondtype of unit circuit does not filter the parallel clock which feeds the serializer.

6.3.1 VCXO based De-serializer/Serializer units:

The VCXO based PLL is the most commonly used approach for De-serializer/Serializer units. Figure 6.3.1 shows the block diagram.

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Equalizer De-serializer(LBW =3MHz-

6MHz)

Serializer &Cable Driver

(LBW = 129kHz-1.4MHz)

Slew PLL1kHz-3kHzLoop BW

VCXO

DSP Core

0.2 UI 0.3 UI

1.0 UI

0.023 UI

0.073 UI 3.0 UI

Figure 6.3.1 VCXO Based De-serializer/Serializer Unit

1.0 UI

0.023 UI

Assuming alignment jitter of the source to be 0.2UI and 0.1UI of jitter added bythe equalizer, the jitter seen by the de-serializer is 0.3UI. The typical input jittertolerance of the de-serializer is about 0.5UI. The wider LBW follows input jitter asmuch as possible. Delay between the clock and the output data of the DSP coreshould be properly considered. The PLL with a VCXO is used to clean the jitterpresent in the parallel clock from the receiver. The data input to the serializer isfrom a DSP microchip or an FPGA whereas the clock with which the parallel datais sampled is from the clean VCXO output. The alignment and jitter of the paralleldata may stress the input jitter tolerance (set-up and hold time) of the serializer.

The designer should watch for two potential pitfalls in today’s off-the-shelf PLLmicrochips designed to work with the VCXO.

1. Dead zone:

Some PLL microchips could have a dead zone. This may result in abnormallyhigh jitter when the input phase aligns in the dead zone of phase detector.This happens because there is no corrective feedback for the VCO phasewhen the phase alignment is in the dead zone of the phase detector. To avoida dead zone, a shunt resistor to ground or power supply should to be used atthe phase frequency detector (PFD) output. This shunt resistor may cause aphase offset. The choice between shunting to ground or power supply isdetermined by the one, which provides the best set-up and hold time for theserializer.

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2. Input phase offset:

Some PLLs, which do not have a charge pump, could have input phase offsetdue to a different locking position for the VCXO.

By choosing proper LBW or phase slew, the phase drift during one video line canbe chosen as low as 15ps-20ps. Due to the clean reference available, the PLLwithin the serializer does not need to filter any jitter; thus wider LBW can beused. A wider LBW is more tolerant to board noise. However, phase detectornoise passes through the wider LBW and therefore increasing the LBWexcessively may also increase the output jitter. We recommend LBW within129kHz to 1.4MHz.

6.3.1.1 Jitter Characterization of VCXO Based De-serializer/Serializer Units

This type of unit can be tested for intrinsic jitter using the jitter reconditioning unit(Figure 4.1). In this case the LBW of the jitter reconditioning unit should be setlower than the VCXO based De-serializer/Serializer unit under test. Table 6.3.1summarizes the achievable jitter.

Table 6.3.1Video Pattern Intrinsic Jitter

SMPTE Specification 673ps (Timing),135ps (Alignment)

Colour Bars 30ps-100psPathological Pattern 30ps-100ps

Since the total jitter is less than the alignment jitter, there is no need to isolatetiming jitter and the alignment jitter.

6.3.2 De-serializer/Serializer units without a VCXO:

In certain situations, it is desirable to have a low cost solution by just using aserializer and a de-serializer without filtering the parallel clock. The block diagramof such a De-serializer/Serializer unit is shown in Figure 6.3.2. The source isassumed to have 0.2UI jitter and the jitter added by the equalizer is assumed tobe 0.1UI. The jitter is additive assuming systematic jitter. The jitter that is addedat the parallel clock generation from the de-serializer is assumed to be 0.7UI.The jitter that is added by the DSP core is assumed to be 2UI. Therefore the totalphase step (jitter) could be as high as 3.0UI into the serializer.

With a narrow LBW the serializer can be designed with a phase slew, whichresults in 0.4UI phase drift during the pathological line. Depending upon thepattern dependency, the peak to peak systematic jitter would be 2X0.4=0.8UI.

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Adding 0.05UI random jitter, the total output jitter would be 0.85UI, which is lessthan the SMPTE 1UI timing jitter specification. Most of the jitter component isaround 37kHz (pathological line) which is low frequency jitter. The timing jitterextracted using a 10Hz clock extractor will be close to the intrinsic jitter. Thus, thetiming jitter can be considered as intrinsic jitter and there is no need to use theclock extraction method to measure timing jitter. Since the timing jitter is greaterthan the alignment jitter specification, we have to measure the alignment jitter. Asmentioned in Section 4.2, the clock extractor with 100kHz LBW setting should beused. This architecture meets the SMPTE requirement, however, it may requirecareful board layout because of the low LBW involved and it does not providesuperior jitter performance.

Let us consider how jitter accumulates in the time domain when similar De-serializer/Serializer units are cascaded (Figure 6.3.2). The longest run of patterndependency in a SMPTE SDI signal is about 27µs (equal to one active videoline). Since the phase drift in every unit is determined by the PLL slew, we couldset the slew such that the maximum phase drift is limited to 0.85UI. As a firstorder of approximation the overall phase will not drift more than 0.85UI evenwhen similar units are cascaded.

0.2 UI

0.3 UI

1.0 UI

0.85 UI

0.85 UI

Clock Extractor100KHz loop BW

Equalizer

De-serializer DSP Core SerializerLBW=50kHz

3.0 UI

Figure 6.3.2: Jitter accumulation in a cascaded De-serializer/SerializerUnits without a VCXO

0.85 UI

0.95 UI

1.65 UI

0.85 UI

0.85 UI

Equalizer

De-serializer DSP Core SerializerLBW=50kHz

3.65 UI

6.3.2.1 Jitter Characterization of De-serializer/Serializer Units without aVCXO:

The intrinsic jitter and the alignment jitter could be measured according toSection 4. Table 6.3.2 summarizes the expected jitter of these types of units.

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Table 6.3.2Video Pattern Intrinsic (Timing) Jitter Alignment JitterSMPTE specification 673ps 135psColor Bars 50ps-300ps 40ps-80psPathological pattern 400ps-600ps 50ps-110ps

6.4 Distribution Amplifier (DA)Two types of DAs could be realized depending upon the performance neededand the cost target; re-timer based units and De-serializer/Serializer based units.

6.4.1 Re-timer based DA:The block diagram of the re-timer based DAs is shown in Figure 6.4.1

Equalizer Re-timer

Cable Driver

Figure 6.4.1: Re-timer based DA

Cable Driver

Cable Driver

Cable Driver

This is the simplest DA. Because the re-timer does not have any data buffer, thetypical input jitter tolerance is 0.5UIp-p beyond the LBW. Since this architectureof the DA is very similar to that of the router, jitter filtering happens in the sameway as shown in Figure 6.2.2.

In a system, a DA could be used directly after the source, or it could be cascadedin front of another similar DA or a router. Figure 6.4.2 shows how jitteraccumulates in a multiple pass situation.

Consider jitter from a router as a first pass (Figure 6.2.2). The output phase ofthe router’s re-timer is the input of the DA through a bandwidth-limited channel(shown with the thick line in Figure 6.4.2). The jitter during pseudo-randompattern does not add arithmetically, however during pathological line, the jitter

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from one pass to the next adds arithmetically. This is because the response time,which is related to the LBW of the re-timer, is less than the pathological lineduration.

If all the DAs and Routers in a chain have exactly the same LBW, then the nextre-timer will follow the accumulative jitter. However, in manufacturing it is notpossible to manufacture PLLs with exactly the same loop bandwidth. Thebandwidth of similar re-timer microchips may vary over process (approximately+/-45%) and from manufacturer to manufacturer it may vary even more (up to500%). The worst case results when re-timers earlier in the chain have a widerLBW causing accumulation of jitter in that frequency band and the last re-timerwith a nominal LBW or lower LBW does not track the accumulated jitter. Whenthe accumulated jitter exceeds the input jitter tolerance of the last re-timer, errorswill be generated.

The jitter peaking which is typically less than 0.1db or 1%, is not a major reasonfor jitter build up in SMPTE signal because the pathological line induced jitterdominates.

0.05UI

-0.05UI

0.0UI

OutputPhase

time

Pseudo Random Pathological (27 us) Pseudo Random

Output phase of the first Re-timer + Jitter ofBandwidth limited channel before second

Re-timer

Output phase of the secondRe-timer

Pseudo random pattern outputpeak-peak jitter

Pathological patternoutput peak-peak jitter

of second DA

Figure 6.4.2: Illustration of jitter accumulation

-0.10UI

6.4.2 De-Serializer and Serializer Based DA

To ensure a large number of passes, the jitter may be filtered in the paralleldomain to utilize the data buffer provided by the de-serializer and serializerinterface. This type of DA is very similar to the De-serializer/Serializer units and asimilar design criterion could be used. Again, a VCXO based or a non-VCXObased DA could be realized.

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6.5 Production Switcher

A production switcher representation is illustrated in Figure 6.5.1

Input Channel 1 EqualizerDe-serializerLBW 4.2MHz

+/-1 Video LineFIFO

DigitalMultiplexorand FIFOController

Genlock P-clockVertical Synch andHorizontal Synch Recovery Block

Input Channel 2 Equalizer+/-1 Video Line

FIFO

P-clockV-SynchH-Synch

Serializer LBW

(129kHz -1.4MHz)

House Synch

Figure 6.5.1 Simplified Production Switcher Architecture

De-serializerLBW 4.2MHz

DigitalSignal

ProcessorBlock

Production switcher uses a combination of De-serializer/Serializer units and asource. The output jitter will be a function of the genlocked parallel clock and theserializer jitter, irrespective of the input jitter. Since the internal parallel clock isnot derived from the input data, it may momentarily drift from the input dataalignment. If there is not sufficient amount of data buffer, it could cause bit errors.Generally De-serializer/Serializer units have a latency in the order of 1 video line,thus 1 line worth of FIFO is used in a production switcher. This FIFO also takescare of the momentarily drift of the internal parallel clock.

The jitter of the production switcher should be characterized just like a videosource (Section 6.1) because the output is referenced to the house synch.

7 Miscellaneous Tips on PLL Based System Design

The paper has shown several configurations of video equipment which may beencountered in the studio. One element common to most of the configurations isa PLL. The following design tips are useful in such systems.

1. Wider LBW PLLs are more immune to the board noise. It is the best choicewhen jitter filtering is not required, as in the case of a serializer when a cleanparallel clock is available. However, phase detector noise may increase thetotal output jitter at high LBW. Therefore, the LBW should be optimized for theminimum output jitter.

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2. A regulated or filtered power supply should be used when designing low LBWcircuits. Even VCXO based PLLs may require clean power supplies when abandwidth around 1kHz at 0.2UI phase modulation is designed.

3. A loop-through output derived from a de-serializer may have jitter content upto 6MHz because of the higher LBW. If total jitter content increases more thanthe 0.4UI limit of a re-timer, it could cause errors. Thus, loop-through outputsshould not be used for cascading units. If a loop-through output must be usedas a cascading output, this signal should be re-timed with a lower LBW toprovide a clean output.

8 Conclusion

System level design considerations for various units used in a studio arepresented in this paper. Time domain jitter is discussed to show the challengespresented by the pathological pattern in the SMPTE signal coding. It isdemonstrated how slew PLL based units could achieve higher jitter attenuationwithout sacrificing robustness. It is also shown how it is possible to attain or evensurpass the SMPTE jitter requirements if the designer optimizes the LBWselection.

Acknowledgment

The authors would like to thank J. Francis, T. Kapucija, E. Fankhauser and D.Lynch for their helpful advice and contributions.

References

1. ANSI/SMPTE 292M-1996, Bit-Serial Digital Interface for High-DefinitionTelevision Systems.

2. ANSI/SMPTE 292M-1993, 10-Bit 4:2:2 Component and 4fsc CompositeDigital Signals - Serial Digital Interface.

3. J. R. Waschura, “Testing in Uncompressed HDTV Signals,” 140th AnnualSMPTE Technical Conference and Exhibit, pp. 528-551, Oct 28-31, 1998.

4. A. Hajimiri, T. H. Lee, “Low Noise Oscillators,” Phase Noise and Jitter inPhase-Locked Loops, Kluwer Academic Publishers, pp. 166-178.