Logic Synthesis PrimerLogic Synthesis Primer

Alan MishchenkoAlan Mishchenko

UC BerkeleyUC Berkeley

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OutlineOutline Introduction to logic synthesisIntroduction to logic synthesis

GoalsGoals Exact vs. heuristicExact vs. heuristic Sequential vs. combinationalSequential vs. combinational

Technology-independent synthesisTechnology-independent synthesis Optimization for area and delayOptimization for area and delay

MappingMapping Standard cells, LUTs, macro-cellsStandard cells, LUTs, macro-cells

VerificationVerification ConclusionConclusion

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Goals of SynthesisGoals of Synthesis

Generating good circuit structure fromGenerating good circuit structure fromTruth tables, BDDsTruth tables, BDDs

Irredundant sums-of-products (used in Irredundant sums-of-products (used in strashstrash))Boolean decomposition (Boolean decomposition (bidecbidec))Converting decision trees into MUX circuits (Converting decision trees into MUX circuits (muxes)muxes)

Sums-of-productsSums-of-productsFactoring (used in Factoring (used in strashstrash))Kernel extraction (not implemented in ABC)Kernel extraction (not implemented in ABC)fast_extractfast_extract algorithm (command algorithm (command fxfx))

Improving available circuit structureImproving available circuit structureTechnology-independent synthesisTechnology-independent synthesis

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Technology Independent SynthesisTechnology Independent Synthesis

AIG rewriting for areaAIG rewriting for areaScripts Scripts drwsat, compress2rsdrwsat, compress2rs

AIG rewriting for delayAIG rewriting for delayScripts Scripts dc2, resyn2dc2, resyn2

High-effort delay optimizationHigh-effort delay optimizationPerform SOP balancing (Perform SOP balancing (st; if –g –K 6st; if –g –K 6))Follow up with area-recovery (Follow up with area-recovery (resyn2resyn2) and ) and

technology mapping (technology mapping (map, amap, ifmap, amap, if)) Iterate, if neededIterate, if needed

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Exact SynthesisExact Synthesis Exact synthesisExact synthesis attempts to minimize the number attempts to minimize the number

of logic gates / logic levels needed to implement a of logic gates / logic levels needed to implement a given functiongiven function

Minimum solutions are known only for simple Minimum solutions are known only for simple circuits, or circuits with special propertiescircuits, or circuits with special properties

Minimum solutions are often not uniqueMinimum solutions are often not unique A new approach to synthesis is being developed, A new approach to synthesis is being developed,

which uses pre-computed minimum solutions for which uses pre-computed minimum solutions for practical functions up to 16 inputs to construct good practical functions up to 16 inputs to construct good (but not minimum) solutions for larger circuits (but not minimum) solutions for larger circuits See recent IWLS’14 paper for detailsSee recent IWLS’14 paper for details

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Sequential SynthesisSequential Synthesis

Uses reachable state information to further Uses reachable state information to further improve the quality of resultsimprove the quality of results Reachable states are often approximatedReachable states are often approximated

Types of AIG-based sequential synthesisTypes of AIG-based sequential synthesis Retiming (Retiming (retime, dretimeretime, dretime, etc), etc) Detecting and merging sequentrial equivalences Detecting and merging sequentrial equivalences

((lcorr, scorr, &scorrlcorr, scorr, &scorr, etc), etc) Negative experiencesNegative experiences

Sequential redundancy removal is often hardSequential redundancy removal is often hard Using sequential don’t-cares in combinational Using sequential don’t-cares in combinational

synthesis typically gives very small improvementsynthesis typically gives very small improvement

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Logic Synthesis for PLAsLogic Synthesis for PLAs Enter PLA (.type fd) into ABC using Enter PLA (.type fd) into ABC using readread Perform logic sharing extraction using Perform logic sharing extraction using fxfx

If If fxfx is complaining that individual covers are not prime and is complaining that individual covers are not prime and irredundant, try “irredundant, try “bdd; sop; fxbdd; sop; fx””

After After fx, fx, convert shared logic into AIG and continue AIG-convert shared logic into AIG and continue AIG-based synthesis and mappingbased synthesis and mapping

Consider using high-effort synthesis with don’t-caresConsider using high-effort synthesis with don’t-cares First map into 6-LUTs (First map into 6-LUTs (if –K 6; psif –K 6; ps), optimize (), optimize (mfs2mfs2), synthesize ), synthesize

with choices (with choices (st; dchst; dch) and map into 6-LUTs () and map into 6-LUTs (if –K 6; psif –K 6; ps)) Iterate until no improvement, then remap into target technologyIterate until no improvement, then remap into target technology

To find description of PLA format, google for “Espresso To find description of PLA format, google for “Espresso PLA format”, for example:PLA format”, for example: http://www.ecs.umass.edu/ece/labs/vlsicad/ece667/links/http://www.ecs.umass.edu/ece/labs/vlsicad/ece667/links/

espresso.5.htmlespresso.5.html

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Technology Mapping for SCsTechnology Mapping for SCs Read library usingRead library using

read_genlibread_genlib (for libraries in GENLIB format) (for libraries in GENLIB format) read_liberty read_liberty (for libraries in Liberty format)(for libraries in Liberty format)

For standard-cellsFor standard-cells mapmap: Boolean matching, delay-oriented, cells up to 5 inputs: Boolean matching, delay-oriented, cells up to 5 inputs amapamap: structural mapping, area-oriented, cells up to 15 inputs: structural mapping, area-oriented, cells up to 15 inputs

If Liberty library is used, run If Liberty library is used, run topotopo followed by followed by stimestime (accurate timing analysis) (accurate timing analysis) bufferbuffer (buffering) (buffering) upsize; dnsize upsize; dnsize (gate sizing)(gate sizing)

Structural choices are an important way of improving Structural choices are an important way of improving mapping (both area and delay)mapping (both area and delay) Run “Run “st; dchst; dch” before calling ” before calling mapmap or or amapamap

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Technology Mapping for LUTsTechnology Mapping for LUTs

It is suggested to use mapper It is suggested to use mapper if –K <num>if –K <num>For area-oriented mapping, try “For area-oriented mapping, try “ if -aif -a””For delay-oriented mapping, try delay-oriented For delay-oriented mapping, try delay-oriented

AIG-based synthesis with structural choicesAIG-based synthesis with structural choicesStructural choices are an important way of Structural choices are an important way of

improving mapping (both area and delay)improving mapping (both area and delay)Run “Run “st; dchst; dch” before calling ” before calling ifif

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Technology Mapping for MacrocellsTechnology Mapping for Macrocells

Custom mapping optionsCustom mapping optionsLUT structures composed of two or three LUTsLUT structures composed of two or three LUTs

if –S <XYZ> if –S <XYZ> User-defined macro-cells up to 16 inputs, User-defined macro-cells up to 16 inputs,

composed of LUTs, MUXes, and standard-cellscomposed of LUTs, MUXes, and standard-cellsUnder developmentUnder development

Minimizing circuit parametersMinimizing circuit parametersnumber of factored-form literals (renode)number of factored-form literals (renode)number of cubes (renode –s)number of cubes (renode –s)number of BDD nodes (renode –b)number of BDD nodes (renode –b)number of CNF clauses (write_cnf)number of CNF clauses (write_cnf)

As usual, structural choices can helpAs usual, structural choices can help

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VerificationVerification

Verification and synthesis are closely related Verification and synthesis are closely related and should be co-developedand should be co-developed

Combinational verificationCombinational verification ““r <file1>; cec <file2>r <file1>; cec <file2>” (small/medium circuits)” (small/medium circuits) ““&r <file1.aig>; &cec <file2.aig> (large circuits)&r <file1.aig>; &cec <file2.aig> (large circuits)

Sequential verificationSequential verification ““r <file1>; dsec <file2>r <file1>; dsec <file2>””

Running Running ceccec or or dsecdsec any time during a synthesis any time during a synthesis flow compares the current version with the specflow compares the current version with the spec The spec is the circuit obtained from the original fileThe spec is the circuit obtained from the original file

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Future WorkFuture Work

Improve usability of ABCImprove usability of ABCDevelop mapping for user-specified Develop mapping for user-specified

macro-cellsmacro-cellsDevelop more scalable technology-Develop more scalable technology-

dependent synthesisdependent synthesis

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ConclusionConclusion

Reviewed logic synthesisReviewed logic synthesis Proposed ABC commands forProposed ABC commands for

Technology-independent synthesisTechnology-independent synthesis Technology mappingTechnology mapping Formal verificationFormal verification

Discussed future developments Discussed future developments