EOVSA Preliminary Design Review 1

LO Distribution Subsystem

Wes GrammerNRAO

March 15-17, 2012

EOVSA Preliminary Design Review 2

Outline

• Design requirements• Top-level block diagram• Subsystem analysis• Component selection• Packaging and cooling• Interfaces (mechanical and electronic)• Production assembly and test• Costing and schedule

March 15-17, 2012

EOVSA Preliminary Design Review 3

LO Distribution Subsystem Design Requirements and Specifications

• Deliver +10 dBm min. LO power to 1st and 2nd IF mixers in all 15 Downconverter modules, over the specified tuning range

• 1st LO (LO1) tuning range: 21.5 – 38 GHz, 0.5 GHz steps• 2nd LO (LO2) output frequency: 21.15 GHz• LO1 frequency switching time: < 1 ms, max.• LO1 and LO2 both externally lockable to a 10 MHz reference (from Timing Gen.)• Assume phase noise, spurious and harmonic output specs for Hittite 40 GHz synthesizer

applicable to both LO1 and LO2• Alternate LO1 source, remotely selectable for each antenna (for subarrays)• Monitor and control (except LO1 synthesizers):

– Serial I/O bus, RS-485 signaling, ~1.0-3.5 Mbps asynchronous transfer– Uses the same software protocol as Downconverter

• Monitor and control (LO1 synthesizers):– 10/100Base-T Ethernet; SCPI (Agilent) instrument control command protocol

• Environment: Indoor, temperature-controlled• MTBF > 10 years, for subsystem elements common to entire array

March 15-17, 2012

EOVSA Preliminary Design Review 4

LO Distribution SubsystemBlock Diagram (1)

March 15-17, 2012

10 MHzReference Inputs

L O 1 -A_ A N T 1

L O 1 -B_ A N T 1

LO2 Outputs 21.150 GHz

LO2 Outputs21.5 - 38 GHz

LO 1 -A _ A N T 1

LO 1 -A _ A N T 2

L O 1 _ S E L_ A N T1

T T LD r iv e r

S W 1 3

CI N 1

I N 212

G +V

LO 1 -A _ A N T 3

LO 1 -A _ A N T 4

L O 1 -A

RF Sy nthesizer

21.5 - 38 GHz Out0 to +10 dBm

H it t i teH MC -T2 2 4 0

R F O U T

R E F I N

T T LD r iv e r

S W 1 1

CI N 1

I N 212

G +V

M U L T1

x15 Freq. Mult.

150 MHz Out+13 dBm

S p ec t ra D y n a m ic sF S 1 5 0 -10

R F O U T

R E F I N

LO 1 -A _ A N T 5

LO 1 -A _ A N T 6 T T LD r i v e r

S W 2

CI N 1

I N 212

G +V

P A D 2

-3 d B

2 1 0 9 -3A TM

LO 1 -A _ A N T 7

LO 1 -A _ A N T 8

T T LD r iv e r

S W 7

CI N 1

I N 212

G +V

P A D 3

-7 d B

2 1 0 8 -3A TM

LO 1 -A _ A N T 9

LO 1 -A _ A N T 1 0

P A D 1

-3 d B

2 1 0 9 -3A TM

T T LD r i v e r

S W 1 2

CI N 1

I N 212

G +V

T T LD r i v e r

S W 1 4

CI N 1

I N 212

G +V

LO 1 -A _ A N T 1 1

LO 1 -A _ A N T 1 2

LO 1 -A _ A N T 1 3

T T LD r i v e r

S W 8

CI N 1

I N 212

G +V

LO 1 -A _ A N T 1 4

T T LD r i v e r

S W 4

CI N 1

I N 212

G +V

A 1

2 3 d B g a in , 9 d B N F+2 9 d B m P o _ 1 d BQ u in s t a rQ P W -2 1 3 8 2 9 3 0 -0 0

LO 1 -A _ A N T 1 5

LO 1 -A _ TE S T

L O 1 -A_ A N T 5

L O 1 -B_ A N T 5

T T LD r iv e r

S W 9

CI N 1

I N 212

G +V

L O 1 _ S E L_ A N T5

L O 1 -B

RF Sy nthesizer

21.5 - 38 GHz Out0 to +10 dBm

H it t i teH MC -T2 2 4 0

R F O U T

R E F I N

L O 1 -A _ A N T 6

L O 1 -B _ A N T 6L O 1 _ S E L_ A N T6

T T LD r iv e r

S W 1 5

S PD T R F S wit c h

5 2 1 Y -4 21 1 0 3 AD ow -K e yD C - 4 0 G H z

CI N 1

I N 212

G +V

L O 1 -A_ A N T 7

L O 1 -B_ A N T 7

T T LD r iv e r

S W 5

CI N 1

I N 212

G +V

L O 2

Ext. Ref . DRO

21.150 GHz Out+13 to +16 dBm

L u c ixL O -2 11 -E C -10 2 0 6 1

R F O U T

R E F I N

L O 1 _ S E L_ A N T7

T T LD r iv e r

S W 1

CI N 1

I N 212

G +V

L O 1 -A _ A N T 8

L O 1 -B _ A N T 8LO 1 _ S E L _ A N T8

S P L 3

S P L I TTE R 1 6-W A YPS 1 6 -2 7MC L I

1

2

3

S

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

S P L 2

S P L I TTE R 1 6-W A YPS 1 6 -2 7MC L I

1

2

3

S

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

T T LD r iv e r

S W 3

CI N 1

I N 212

G +V

S P L 1

S P L I TTE R 1 6-W A YPS 1 6 -2 7MC L I

1

2

3

S

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

T T LD r i v e r

S W 1 0

CI N 1

I N 212

G +V

T T LD r i v e r

S W 1 6

S P D T R F S w it c h

5 21 Y -4 2 1 1 0 3 AD o w -K e yD C - 4 0 G H z

CI N 1

I N 212

G +V

A 3

1 6 d B g a in , 5 d B N F+2 4 d B m P o _ 1 d BC ia o W ire les sC A 2 0 2 1 -3 0 1 4

A 2

2 3 d B g a in , 9 d B N F+2 9 d B m P o _ 1 d BQ u in s t a rQ P W -2 1 3 8 2 9 3 0 -0 0

L O 1 -A_ A N T 9

T T LD r i v e r

S W 6

CI N 1

I N 212

G +V

L O 1 -B_ A N T 9L O 1 _ S E L_ A N T9

L O 1 -A _ A N T 10

L O 1 _ A N T1

L O 1 _ A N T3

L O 1 _ A N T2

L O 1 -B _ A N T 10

L O 1 _ A N T6

L O 1 _ A N T5

L O 1 _ A N T4

L O 1 _ S E L_ A N T1 0

L O 1 _ A N T9

L O 1 _ A N T8

L O 1 _ A N T7

L O 1 _ A N T1 1

L O 1 _ A N T1 0

L O 1 _ A N T1 4

L O 1 _ A N T1 3

L O 1 _ A N T1 2

1 0 M H z_ I N 1

L O 1 _ TE S T

L O 1 _ A N T1 51 0 M H z_ I N 3

1 0 M H z_ I N 2

L O 1 -A_ A N T 11

L O 2 _ A N T3

L O 2 _ A N T2

L O 2 _ A N T1

L O 2 _ A N T6

L O 2 _ A N T5

L O 2 _ A N T4

L O 1 -B_ A N T 11

L O 2 _ A N T8

L O 2 _ A N T7

L O 1 _ S E L_ A N T1 1

L O 2 _ A N T1 1

L O 2 _ A N T1 0

L O 2 _ A N T9

L O 2 _ A N T1 4

L O 2 _ A N T1 3

L O 2 _ A N T1 2

L O 2 _ A N T1 6

L O 2 _ A N T1 5

+1 2 V

L O 1 _ S E L[ 1 5 . .0 ]

+1 2 V

L O 1 -A _ A N T 12

+1 2 V

+1 2 V

L O 1 -B _ A N T 12

+1 2 V

L O 1 _ S E L_ A N T1 2

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

+1 2 V

LO 1 -B _ A N T 1

LO 1 -B _ A N T 2

LO 1 -B _ A N T 3

LO 1 -B _ A N T 4

LO 1 -B _ A N T 5

LO 1 -B _ A N T 6

LO 1 -B _ A N T 7

LO 1 -B _ A N T 8

LO 1 -B _ A N T 9

LO 1 -B _ A N T 1 0

LO 1 -B _ A N T 1 1

LO 1 -B _ A N T 1 2

LO 1 -B _ A N T 1 3

LO 1 -B _ A N T 1 4

LO 1 -B _ A N T 1 5

LO 1 -B _ TE S T

L O 1 -A_ A N T 13

L O 1 -B_ A N T 13L O 1 _ S E L_ A N T1 3

L O 1 -A _ A N T 14

L O 1 -B _ A N T 14L O 1 _ S E L_ A N T1 4

L O 1 -A_ A N T 15

L O 1 -B_ A N T 15L O 1 _ S E L_ A N T1 5

L O 1 -A _ TE S T

L O 1 -B _ TE S TL O 1 _ S E L_ TE S T

M&C Input

L O 1 -A _ A N T 2

L O 1 -B _ A N T 2L O 1 _ S E L_ A N T2

L O 1 -A_ A N T 3

L O 1 -B_ A N T 3L O 1 _ S E L_ A N T3

L O 1 -A _ A N T 4

L O 1 -B _ A N T 4L O 1 _ S E L_ A N T4

LO Distribution Module Assembly Enclosure

EOVSA Preliminary Design Review 5

LO Distribution SubsystemBlock Diagram (2)

March 15-17, 2012

1st IF20-20.5 GHz

1st IF20-20.5 GHz

LO1 (21.5-38 GHz)

2nd IF0.65-1.15 GHz

2nd IF0.65-1.15 GHz

LO2 (21.15 GHz)

P A D 9

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

M 4

D o u b le -B a l. M ix e rM a rk iM 1 R -0 7 2 6 L S

R F

LO

I F

F I L T3

0 . 6 5 -1 . 1 5 G H z B P F<M a n u f a c t u re r><M a n u f a c t u re r p / n >

P A D 1 0

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

S P L 1

1 0 -4 0 G H z S p lit t e rP 2 K 9 AA TM

1

2

S

A 51 7 d B g a in , 6 d B N F+1 8 d B m P o _ 1 d BM a rk i A -1 8 4 4

A 31 7 d B g a in , 6 d B N F+1 8 d B m P o _ 1 d BM a rk i A -1 8 4 4

P A D 4

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s

P A D 3

-3 d B

B W -S 3 -2 W 2 6 3 +M in i-C k t s

M 1

D o u b le -B a l. M ix e rM a rk iM 9 -0 9 4 2 L N

R F

LO

I F

A 7

2 8 d B g a in , 1 . 3 d B N F+1 0 . 5 d B m P o _ 1 d BTe le d y n e / C o u g a rA C -1 2 8 6 C

F I L T4

0 . 6 5 -1 . 1 5 G H z B P F<M a n u f a c t u re r><M a n u f a c t u re r p / n >

I S O 2

2 0 -2 3 G H z I s o l.A Ti2 0 -2 3A TM

F I L T1

2 0 -2 0 . 5 G H z B P F<M a n u f a c t u re r><M a n u f a c t u re r p / n >

F I L T2

2 0 -2 0 . 5 G H z B P F<M a n u f a c t u re r><M a n u f a c t u re r p / n >

A 4

1 7 d B g a in , 6 d B N F+1 8 d B m P o _ 1 d BM a rk i A -1 8 4 4 A 6

1 7 d B g a in , 6 d B N F+1 8 d B m P o _ 1 d BM a rk i A -1 8 4 4

A 8

2 8 d B g a in , 1 . 3 d B N F+1 0 . 5 d B m P o _ 1 d BTe le d y n e / C o u g a rA C -1 2 8 6 C

M 3

D o u b le -B a l. M ix e rM a rk iM 1 R -0 7 2 6 L S

R F

LO

I F

M 2

D o u b le -B a l. M ix e rM a rk iM 9 -0 9 4 2 L N

R F

LO

I F

P A D 7

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

P A D 8

-3 d B

S A 3 0 1 5 -0 3F a irv ie w

S P L 2

2 -2 6 . 5 G H z S p lit t e r6 0 2 0 2 6 5K ry t a r

1

2

S

I S O 1

2 0 -2 3 G H z I s o l.A Ti2 0 -2 3A TM

EOVSA Preliminary Design Review 6

LO System Cascade Analysis• Excel workbooks created to perform stage-by-stage

cascaded analysis of the following:– System gain, including mismatch loss– Output power– 1 dB compression point, and output margin– Third-order intercept point (IP3)

• Three different distribution configurations were evaluated on performance and cost

• LO1 distribution design a challenge, because of higher loss, especially cables, at high frequencies, and additional cascaded components.

March 15-17, 2012

EOVSA Preliminary Design Review 7

LO1 Cascade Worksheet

March 15-17, 2012

EOVSA Preliminary Design Review 8

LO2 Cascade Worksheet

March 15-17, 2012

EOVSA Preliminary Design Review 9

Component Selection• LO1 power amplifier is a single-source item, from Quinstar. • Used modular x15 reference multiplier + PLO for LO2 source instead

of a synthesizer, to save cost• Mechanical switch for LO1 has lower loss, higher isolation and

better VSWR than PIN diode type.• Marki LO buffer amps have low power dissipation, small size, and

are relatively low cost.• Will need lots of flexible cables of various lengths with 2.92mm

connectors. Astrolab offers a hand-formable type with low loss, and can be ordered to pre-made custom lengths at a reasonable cost.

• As with the Front End and Downconverter, linear power supplies will be used to run all analog electronics

March 15-17, 2012

EOVSA Preliminary Design Review 10

Thermal Management• Cooling of LO amplifiers in the Downconverter is not a real issue – dissipation is

low.• Conversely, total power dissipation in the LO Distribution Module may be close

to 300W:– LO1 power amps each dissipate 60W– LO2 multiplier + PLO dissipate ~13W– LO2 power amplifier dissipates 7W– Linear power supplies with 50% efficiency will dissipate 140W– RF switches are latching self-cutoff type, so average is ~0W.

• Solutions:– Use a covered enclosure with a pair of rear-mounted fans to provide continuous flow-

through cooling.– Add or design in automatic thermal shutdown protection for the amplifiers and PLO, in

case of fan failure.– Make it impossible to power the electronics, unless the fans are on

March 15-17, 2012

EOVSA Preliminary Design Review 11

Mechanical Details• Enclosure and Interfaces:

– Use a 19” rack-mount 3U or 4U aluminum chassis– LO1 inputs from Hittite synthesizers need to be on the front panel, to

keep cables short– All RF outputs on rear panel, on the side closest the Downconverter

rack– M&C bus connectors and AC or DC power input on the opposite end of

rear panel• Component layout considerations

– Good heat sinking of amplifiers, and unobstructed airflow around them– Stacked arrangement for two LO1 splitters, with row of switches in

between, to keep cable lengths short and well-matched– Allow for later addition of bi-phase modulators on LO2 outputs

March 15-17, 2012

EOVSA Preliminary Design Review 12

LO Distribution Module Interfaces

• Hardware:– (16) 2.92mm-M LO1 outputs, to Downconverters– (16) SMA-M LO2 outputs, to Downconverters– (2) 2.92mm-M LO1 inputs, from Hittite sources– (1) BNC-M 10 MHz reference input, from TG– (2) DB-9 or 10-pin RJ-style connectors, M&C I/O– (1) AC fused power entry, IEC style w/switch

• Software:– Refer to table in following slide

March 15-17, 2012

EOVSA Preliminary Design Review 13March 15-17, 2012

Signal Name Dir. Type Mode Range Min Range Max Unit Connector Freq/Rate Precision

X / Y Pol from FE In RF on fiber Analog Fiber -30 -35 dBm SC/APC 1-18 GHz N/A

10 MHz Ref In RF CW Analog Elec (TBD) 16 dBm BNC 10 MHz N/A

50 Hz Sync In Pulse Analog Elec 0 5 V BNC 50 Hz 1 us

LO1 Sub A Mon/Ctrl I/O SCPI Data Digital Elec n/a n/a n/a Ethernet 50 Hz 10 us

LO1 Sub B Mon/Ctrl I/O SCPI Data Digital Elec n/a n/a n/a Ethernet 50 Hz 10 us

Subarray Setting In Integer Digital Elec 0 5 V RS-485 ~1/day 1 s

LO2 PLO Lock Alrm Mon Out Bool Digital Elec n/a n/a n/a RS-485 1 Hz 1 s

RX PwrOut Mon X-Pol Out Float Digital Elec -35 -15 dBm RS-485 50 Hz 1 ms

RX PwrOut Mon Y-Pol Out Float Digital Elec -35 -15 dBm RS-485 50 Hz 1 ms

Atten Ctrl X-Pol In Integer Digital Elec 0 15 dB RS-485 1 Hz 10 us

Atten Ctrl Y-Pol In Integer Digital Elec 0 15 dB RS-485 1 Hz 10 us

X Pol from DC Out IF Power Analog Elec -5 -2 dBm SMA650-1150 MHz N/A

Y Pol from DC Out IF Power Analog Elec -5 -2 dBm SMA650-1150 MHz N/A

EOVSA Preliminary Design Review 14

Production Assembly, Testing

• Production process steps– Two-port VNA and output power measurements of

power amplifiers at all LO frequencies– Bench test of cascaded multiplier + PLO– Assembly and test of LO Distribution Module with

RF output cables – Verification of M&C functionality – Test thermal shutdown features– Documentation: Test results, configuration (s/n) list

March 15-17, 2012

EOVSA Preliminary Design Review 15

Component Costing, Delivery

• All RF components have been specified, and price/delivery quotes received

• Reasonable estimates or preliminary pricing on remaining components, except embedded controller

• Enclosure and power supply pricing are rough estimates, final TBD

• Longest lead times:– LO1 power amplifiers (16 weeks), because of req. NRE– LO2 PLO (10 weeks); semi-custom design

March 15-17, 2012

EOVSA Preliminary Design Review 16March 15-17, 2012

EOVSA Preliminary Design Review 17

Important Schedule Dates for LO Distributor Module

• Have all RF components, some cables, and COTS support electronics on order by mid-April at the latest

• Complete enclosure fabrication drawings by June 1, send out for quotes, begin fab in mid-June

• July 1 – July 15: Order rack, cables, connectors, wire, remaining components for prototype unit construction and site installation

• July 1 – August 1: RF component characterization• August – September: Assemble and test prototype module• October 1: Ship prototype to California for installation• Embedded firmware and test software may need to be farmed out,

in the interest of saving time. This could happen during July and August, in parallel with assembly.

March 15-17, 2012