lecture 1. course introduction and plc programming re-cap
TRANSCRIPT
Lecture 1.Course Introduction and
PLC Programming Re-cap
School of Electrical Engineering
Department of Electrical Engineering and Automation
ELEC 8102 Design of Distributed Intelligent Automation Systems
Valeriy Vyatkin, Udayanto Dwi Atmojo
2021
Plan
• What this course is about?• Organisational matters• Generations of programmable control systems• Programming of PLCs• Computational model of PLC● IEC 61131-3 Standard
o Key featureso Software Modelo Basic operation sequence
● IEC 61131-3 PLC programming languages:o Structured Text (ST)o Function Block Diagram (FBD)o Sequential Function Chart (SFC)o Ladder Diagram (LD)
● Note: Lab1 PLC programming
2
Teaching staff
Lecturers:• Prof Valeriy Vyatkin• Dr Udayanto Atmojo
Tutors and Lab supervisors• Ms Polina Ovsiannikova• Mr Ronal Bejarano• Mr Arash Azangoo• Mr Pranay Jhunjhunwala• Mr Tuojian Lyu
3
Lectures
• Some lectures will be presented live during the lecture slots, while other will be pre-recorded.
• In such cases, lecture slots will be used for tutorial activities related to the corresponding lecture.
• Students are requested to watch the pre-recorded lectures before the lecture slots and prepare questions to clarify your doubts.
4
Quizes
• After each lecture slot you will be offered a quiz to be submitted via MyCourses within 24 hours.
• The quiz will be related to the material of that lecture.
• Each quiz corresponds to 1% mark of the course.
5
Marking schedule
• Exam 40%– you need 50% or more for the exam
Course work:• Quizes 11%• Homework 1 2%• Homework 2 2%• Assignment 1 10%• Assignment 2 10% + 5% bonus for the Mutex part
– individual, development, report• 6 labs 30%
– week #38, 40-42,44
Possible total is 110%
6
Labs• Labs will be performed online during a pre-booked lab session. • The VDI virtual machine will be used, it has all needed software
tools pre-installed• Students are asked to attend the lab session (only one!) they are
enrolled in.• Lab is announced on Thursdays right after the lecture• Schedule of lab slots:
– Thursday 14:15 – 16:00– Thursday 16:15 – 18:00– Friday 08:15 – 10:00 – Tuesday 10:15 – 12:00 (the following week)
• Enroll yourself once to one of the lab groups on MyCourses• If you have questions during the lab slot, please use the ”Lab
sessions” channel on Teams• Feel free to use your own laptop for labs 1-4
– Pre-install CoDeSys from MyCourses
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Lab protocol
• Each lab is accompanied with an extensive lab guide document. It is expected to be sufficient for completion of tasks without assistance.
• You can complete lab on your own laptop at home.• During the lab sessions you may get help from the designated tutor
only on the topics related to functioning of the tools, not the ways to solve the problem.
• The code is to be submitted via MyCourses by the specified deadline. The submission will be checked by tutors.
• No modifications is allowed after the submission, file modificationtimestamps do not prove timely submission, students must notifyabout emergencies before the deadline.
• Late submissions: – 50% reduction if submitted up to one day later. Not accepted after that (0
mark)
8
MyCourses Forum
The students are required to check the “News forum” on MyCourses or their emails regularly to receive important announcements.
The students are advised to discuss their questions by raising them in the “General discussion” forum!
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Exam
• Date: 13th of December, 2021• Time: 14-17• Room: online
Repeat dates: 1. 28th February 2022, 16:30-19:302. 16th May 2022, 16:30-19:30
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Course Syllabus (order can change)# Week# Lecture Lab Deadlines1 38 Introduction. Recap on PLC programming
2 39 Software intensive automation Lab 1: PLC recap. CoDeSys and simulation in the loop.
3 40 Automata-based programming in industrial automation
Lab 2: State based PLC design4 41 Implementation of automata models in PLC
5 42 Synchronisation and clocks Lab 3: PLC implementation of state-based control using Boolean logic
Assignment 1 out
6 43 Mutually exclusive access
7 44 NO LECTURE Assignment 1 submission
8 45 Distributed automation systems Lab 4: Development with Function Blocks
9 46 Distributed function block architecture of IEC 61499 Lab 5: Composing applications from library Function Blocks
Peer review of Assignment 1 due.Assignment 2 out.
10 47 Design patterns for distributed systems engineering
11 48 Engineering of peer-to-peer collaborating systems Lab 6. Advanced design with IEC 61499 and FactoryIO
12 49 Reliable communication mechanisms for distributed automation
13 50 Course summary NO LAB Assignment 2 submission
14 51 Exam: Date: 13/12/2021, Online, Time: 14-17
11
Reading• Textbook: Hugh Jack, Automating Manufacturing Systems with
PLCs, open source textbook, https://archive.org/details/ost-engineering-plcbook5_1
• Syntax of PLC languages:https://plcopen.org/sites/default/files/downloads/annex_a_e.pdf
• George Coulouris, Jean Dollimore and Tim Kindberg, Distributed Systems Concepts and Design, Fourth Edition, Addison Wesley/Pearson Education, June 2008, ISBN 0321263545
• Textbook: Vyatkin, V., IEC 61499 Function Blocks for Embedded and Distributed Control Systems Design, 297 pp., Instrumentation Society of America, USA, October, 2016 – Third Edition, Electronic book: https://primo.aalto.fi/discovery/fulldisplay?vid=358AALTO_INST:VU1&search_scope=MyInstitution&tab=LibraryCatalog&docid=alma999347003606526&lang=en&context=L
Click the EBSCOhost E-kirja/E-book
12
Generations of Automation Systems
15
1. Relay based controllers (40s – 50s)2. Microprocessor based PLCs (70s)3. Multifunctional PLCs4. Industrial Networks5. Internet of Things
Generation 0. Mechanical regulators
16
Mine in Cornwall equipped with first steam engine in 1790. First industrial regulator invented by James Watt to keep the wheel’s speed constant.
Generation 1: Relay Ladder Circuits
Hard-wired ladder logic circuits were widely used to control industrial equipment. This explains current popularity of the Ladder Diagram language for programming industrial controllers
Slide 17
Generation 2: Programmable Logic Controllers (PLCs)
PLCs – specially hardened industrial computers -tremendously improved flexibility of automation systems
Slide 20
The Modicon 084 PLCSource: C. C. Bissel, A history of Automatic Control
Programmable Logic Controllers
21
Generation 3: Multifunctional PLCs
Modern PLCs know many programming languages and have versatile and easily expandable architecture.
Slide 22
Programmable Logic Controllers: Form Factors
Small Controllers
Industrial PCs
Panel PCs
and much more…
IntelligentBoardsPC 104
VME BoardsAnd Racks
Tiny Controllers
RTUs/PLCs/PACs
PLC on FPGA
Generation 4: Industrial Networks
25
IF S1 & START THEN LED:=0;FWD:=1;S2:=1;S1:=0;
ELSIF S2 & END THENFWD:=0;S3:=1;S2:=0;
ELSIF S3 & HOME THENLED:=1; S1:=1;S3:=0;
END_IF
PLC Market
27
The programmable logic controller (PLC) market was valued at USD 3897.36 million in 2019 and is expected to reach USD 4292.66 million by 2025.
https://www.mordorintelligence.com/industry-reports/programmable-logic-controller-plc-market
Formal Models of Automation Logic
33
Let us denote by I and O Boolean vectors of inputs and outputs, and S is Boolean vector of state variables. Then the semantics of the controller can be described by the following system of Boolean assignments:
SI O
General Models of PLC execution
34
Combinatorial:O(i)=F(I(i))
Moore type state machine:S(i+1) := T(I(i+1), S(i));O(i+1) := F(S(i+1)),
Mealy type state machine:S(i+1) := T(I(i+1), S(i));O(i+1):= F(I(i+1), S(i));
SI O
ti i+1
Why PLCs are around?
• Reactivity• Timeliness • Reliability: if input is read with an error, the
error will be corrected in the next scan.
36
Preface
This is a recap lecture on PLC programming. Students who have taken the bachelor level course Automation 1 (or Automation Systems 1) should be familiar with this content
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IEC 61131 Standard● IEC 61131-1:2003:
o Programmable controllers - Part 1: General information
● IEC 61131-2:2007:o Programmable controllers - Part 2: Equipment requirements and tests
● IEC 61131-3:2013:o Programmable controllers - Part 3: Programming languages
● IEC TR 61131-4:2004:o Programmable controllers - Part 4: User guidelines
● IEC 61131-5:2000:o Programmable controllers - Part 5: Communications
● IEC 61131-6:2012:o Programmable controllers - Part 6: Functional safety
● IEC 61131-7:2000:o Programmable controllers - Part 7: Fuzzy control programming
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Software Tools
• CoDeSys• Software tool for developing and engineering IEC 61131-3 controller
applications• a soft PLC from 3S-Smart Software Solutions GmbH
• TwinCAT• OEM version of CoDeSys for Beckhoff, under Visual Studio Shell
• ISaGRAF• KW • Tools of SIEMENS, Rockwell, Schneider Electric, ABB…
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Key Features of IEC 61131-3● Finalised in 1993 as a joint effort of representatives of the leading
automation companies: Siemens, Rockwell Automation, ABB, Schneider Electric, etc.
● IEC 61131-3 is the most important automation language in industry.● 80% of all PLCs support it, all new developments base on it.
Depending on the country, some languages are more popular.● Structured software - through use of Configuration, Resource, and
Program Organization Units (POU)● Software encapsulation - through use of POU, and complex data
types● Strong Data Typing - through languages that restrict operations to
only apply to appropriate types of data● Execution control - through use of tasks
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PLC Software Model - Configuration
• This total structure of a PLC software project is called as the software configuration
Figure. Structured Project in CoDeSys
Device = Resource = PLC
Programming Organization Units (POU)
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● Each POU has a defined interface with inputs and outputs● For the purpose of modularization and structuring a well-defined portion of the
program● may be called and executed several times.
● Functions (FUN)o ADD, SQRT, SIN, COS, GT, MIN, MAX, AND, OR, etc.
● Function Blocks (FB)o Standard, vender supplied, and user defined
● Programs (PRL)
PLC operation principle – Cyclic execution !!!
Figure 1 illustrates the operation principle of the cyclic PLC
Task 1: 20ms
Task 2: 100ms
Task 3: 200ms
Tasks with different cycle rates
CODE------------------------------
Read Inputs
Set Outputs
exe cycle
POU execution order
• At the beginning of each task cycle the current values of all the input variables are read
• POU instructions and function blocks are executed from top to bottom and left to right
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execution order
instant effect on the following instruction
effects the input value for the next cycle
Task configuration in CoDeSys
Figure. In Codesys, double clicking on Main Task will bring up the Configuration tab.
Cycle time
Global and Local variables• Variable declaration consists of:
• Variable name (Identifier) : Data type := Initial value (optional) ; Comment (optional)
• Global variable is needed when• It is used in more than one POU as a shared variable in data exchange• It is a physical in/output address• it will be monitored by HMI or used in visualization
• Local variable can be used when• It is used only in the POU where it is declared• It is used as a local state variable
• Note: Global variables enable simple data exchange and signaling between different POUs of PLC applications
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Global and Local variables• Declare variables either globally in a Global Variable List or locally in the
declaration part of each POU
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Structured Text - ST ● Structured Text (ST) is a textual high-level
programming language (like e.g. C) ● ST language can be used in:
● ST programs● Function and Function block logic coding● Action logic coding in SFC programs
● The program code is composed of statementsseparated by semicolons; and containing expressions
● Numerous constructs can be used for programming e.g. different loops, thus allowing the development of complex algorithms
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ST Basics
Each statement must end with a semi-colon (";")Basic statements:
• Assignment - := - Q:=IN; - Q:=sin(angle); - Q := (IN1 + (IN2 / IN 3)) * IN4;
• Conditional statement - IF / THEN / ELSE (simple binary switch) - CASE (enumerated switch)
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ST: Conditional Statements
● IF / THEN / ELSE / ELSIF
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IF Switch1 = True THEN
Switch1 := False;
ELSIF PumpOn1 = True THEN
PumpOn1 = False;
END_IF;
IF Switch1 = True THEN
Switch1 := False;
ELSE
Switch1 := True;
END_IF;
ST: Conditional Statements
● CASE statement ExampleCONST
plus:= 1;
minus:= 2;
times:= 3;
END_CONST
CASE operator OF
plus: a := b + c;
minus: a := b - c;
times: a := a * b;
END_CASE;
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ST: WHILE Statement
The WHILE statement contains an expression whose truth value determines whether or not the statement that follows DO is to be carried out again.
//Searching a value from a data array:
i := StartValue;WHILE Data[i] <> x DO
i := i + 1;
END_WHILE;Index := i;
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ST: REPEAT Statement
The statement is carried out repeatedly until the expression takes on the value TRUE. The statement is carried out at least once j := -4;
REPEAT
j := j + 2;
UNTIL j > 60 END_REPEAT;
REPEAT
a := in1 + in2;
b := 2 * in1;
c := in1 * in2;
UNTIL EndCondition END_REPEAT;
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ST: FOR Statement
The FOR statement carries out a DO loop in which new values are assigned to a variable (the controlled variable).
//Searching the maximum value in a data array:Maximum := 0;
FOR lw := 2 TO 63 DOIF Data[lw] > Maximum THEN;
Maximum := Data[lw];
MaxIdx := lw;END_IF;
END_FOR;
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IEC 61131-3 Function Blocks• Function blocks (FB) are the main building blocks for structuring PLC
programs• They are called by programs and FBs and can themselves call functions as well
as other FBs• Function Block or a Function (FUN) are user made subroutines
• Instead of writing the same program code several times, it can be written once and invoked as a block with new in-/out parameters
64
Function Blocks: Parameters
• Variables can be declared as:• INPUT,
OUTPUT, • IN_OUT,
EXTERNAL, and TEMP
65
Function Block Definition Example
FUNCTION_BLOCK HYSTERESIS
VAR_INPUT
XIN1, XIN2 : REAL;
EPS : REAL; (* Hysterisis band *)
END_VAR
VAR_OUTPUT
Q : BOOL := 0
END_VAR
IF Q THEN
IF XIN1 < (XIN2-EPS) THEN
Q := 0 (* XIN1 decreasing *)
END_IF;
ELSIF XIN1 > (XIN2 + EPS ) THEN
Q := 1; (* XIN1 increasing *)
END_IF;
END_FUNCTION_BLOCK
HysteresisQXIN1
XIN2EPS
BOOLREALREALREAL
1
EPSEPS
0
XIN2
Q
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● Three timer instructions in IEC 61131o TP - Pulse timero TON - Timer On Delayo TOF - Timer Off Delay
● Timer operationso IN = Input conditiono Q = Comparison output results; varies with
timer typeso PT = Preset Timeo ET = Elapsed Time
TONIN
T#200ms
Pump_Tmr
PT ET 178
Q
INQ
ETPT|0
On-Delay (TON) Timing
INQ
ETPT|0
Pulse (TP) Timing
INQ
ETPT|0
Off-Delay (TOF) Timing
Pulse width time Delay time
TP
TON
TOF
FB: Timers
Sequential Function Chart (SFC)
69
• Stems from the Grafcet languageintroduced by the company Telemecanique (now a part of Schneider Electric)
• Powerful graphical technique for describing the sequential behaviour of a control program
• Used to partition a control problem
• Shows overview, also suitable for rapid diagnostics
• The basic elements are STEPS with ACTION BLOCKS and TRANSITIONS
• Support for alternative and parallel sequences
Step 1 N FILL
Step 3
Step 2 S Empty
Transition 1
Transition 2
SFC in CoDeSys
Steps can be directly programmed in other PLC languages.Steps can have three “implicit” associated actions for entry, exit and main activity.To create the “implicit” action Step_active just double click on the new step and select the language.
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SFC in CoDeSys – Actions
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• In CoDeSys: There are two main types of actions:A. Step ActionsB. IEC Actions
• Difference between IEC actions and step actions:• See Codesys help pages:• https://help.codesys.com/api-
content/2/codesys/3.5.12.0/en/_cds_sfc_element_action/
SFC in CoDeSys – A: Step Actions
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• In CoDeSys: Step Action can be created by dragging “a Action” from the toolbar to the highlighted corner of a step
• Active action (i.e. main activity): Continuous execution while the step is active
• Entry action: executed once when the step becomes active
• Exit action: executed once when the step is exited (deactivated)
Active action
Entry action Exit action
SFC in CoDeSys – B: IEC Actions
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• In CoDeSys: These actions comply with the IEC1131-3 standard.
• They are executed according to their qualifiers• Each action box includes the qualifier and the action name
SFC in CoDeSys – IEC Action Qualifiers
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• Action qualifiers are used to define how long the action of a step should be active
• Codesys example: • S: PumpOn1 : Action PumpOn1 := TRUE (in
step: StartPump) is executed until it receives a reset
• R: PumpOn1 : Action PumpOn1 is deactivated (in step: StopPumps)
• N: Pressure_ACT: Activity is active as long as the step is active (in step: CtrlPressure)
SFC Action Qualifiers
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N Non-stored The action is active as long as the step is active.
R0 overriding Reset
The action is deactivated.
S0 Set (Stored) This action is executed as soon as the step is active. The action is executed until it receives a reset, even if the step has already been deactivated.
L time Limited This action is executed as soon as the step is active. The action is executed until the step is deactivated or the given time interval has elapsed.
D time Delayed Execution of this action begins only after the given delay time has elapsed following step activation and the step is still active. The action is executed until the step is deactivated.
P Pulse This action is executed one time as soon as the step is active.
SD Stored and time Delayed
Execution of this action begins only after the given delay time has elapsed following step activation. The action is executed until it receives a reset.
DS Delayed and Stored
Execution of this action begins only after the given delay time has elapsed following step activation and the step is still active. The action is executed until it receives a reset.
SL Stored and time Limited
This action is executed this action as soon as the step is active. The action is executed until the given time has elapsed or it receives a reset.
Step 1 N FILL
Step 3
Step 2 S Empty
Transition 1
Transition 2
SFC in CoDeSys – Actions Example
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A. Step ActionsB. IEC Actions
A: active action
A: entry action
B: active action
SFC - Step Timer
• Each step has an implicit step timer• The step timer is started when the step becomes active• The value of timer can be used in the following transition guard
expression• StepName.t > T#10s
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Simulation..
Step active until timer value > 5s.
SFC in CoDeSys – Branches
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• CoDeSys: two types of branches• Alternative branches: Only one of the
branches is active at the time• Parallel branches: Both branches are
active at the same time
Active step in alternative branches during simulation
Active steps in parallel branches during simulation
SFC - Alternative Branch with Step (1)
• Add a new branch• The new branch will be a parallel branch
• Change it to an alternative branch• (Continue…)
SFC - Alternative Branch with Step (2)
• Delete old transitions• Add four new transitions• Alternative branch with a step is now ready
SFC - Alternative Branch with Jump
• Start from an alternative branch with a step• Add a jump into one branch• Delete the step under the jump• Alternative branch with a jump is now ready
Ladder Diagram (LD)● Originated from the graphical representation of relay logic used to
design electrical control systems using relays.
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Ladder Diagram (LD)● Originated from the graphical representation
of relay logic used to design electrical control systems using relays.
● LD was developed to make program creation and maintenance easier:o Computer based graphical representation of wiring
diagrams that was easy to understando Reduced training and support costo Still widely used
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AIN BOUT
Contact Coil
AIN BOUT
Contact Coil
Structure of Ladder DiagramAn LD is composed of a left power rail, a right power rail and a number of rungs/links in between:o The state of the link element shall be denoted “ON” (1) or “OFF” (0)o The state of the left rail shall be considered ON at all timeso No state is defined for the right rail
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A
B
D ELeft Power Rail Right
Power Rail
Rung/Link
Associated BooleanVariable
Branch
LD: Basic Boolean Logic - Positive Contact
• Boolean input variable: AIN (positive contact)• Boolean output variable: BOUT (positive coil)
• The same logic as a Structured Text ST programIF A = TRUE THEN
B := TRUE;
ELSEB := FALSE;
END_IF;
AIN BOUT
TRUE TRUE
AIN BOUT
FALSE FALSE
LD: Basic Boolean Logic – Negative Contact
• Boolean input variable: AIN (negative contact)• Boolean output variable: BOUT (positive coil)
• The same logic as a Structured Text ST programIF NOT A = TRUE THEN
B := TRUE;
ELSEB := FALSE;
END_IF;
AIN BOUTTRUE FALSE
AIN BOUTFALSE TRUE
Ladder Diagram Execution● Rungs of LD are solved from left to right and top to bottom● Branches within rungs are solved top left to bottom right
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P S
R
A
B
D E
F G H
I J K
1. Left to Right
2. Top to Bottom
Series and Parallel Operations
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OR
AND
A
B
C D
IF ((A OR B) AND (NOT C) AND D) THEN
E := 1; F := 1;
ELSE E := 0; F := 0;
END_IF;
E
F
Branches
AND: Input instructions in seriesOR: Input instruction in parallel
Standard Contacts● Positive Contact: Normally Open Contact -| |-o Enables the rung to the right of the instruction if the rung to the left is enabled and
the associated Boolean variable is TRUE/ON (1)● Negative Contact: Normally Closed Contact -|/|-o Enables the rung to the right of the instruction if the rung to the left is enabled and
the associated Boolean variable is FALSE/OFF (0)
● Positive transition contact -|P|-o Enables the right side of the rung for one scan when the rung on left side of the
instruction is true and an OFFà ON transition of the associated variable is sensed
● Negative transition contact -|N|-o Enables the right side of the rung for one scan when the rung on left side of the
instruction is true and an ONàOFF transition of the associated variable is sensed
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Standard Coils● The referenced bit is reset when processor power is cycledo Coil -( )-: sets a bit when the rung is true (1) and resets the bit when the
rung is false (0)o Negative coil -( / )-: sets a bit when the rung is false (0) and resets the bit
when the rung is true (1)o Set (latch) coil -(S)-: sets a bit (1) when the rung is true and does nothing
when the rung is false. The bit remains set until reset by a Reset coil.o Reset (unlatch) Coil -(R)-: resets a bit (0) when the rung is true and does
nothing when the rung is false. The bit remains reset until set by a Set coil.
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Standard Coils● Positive transition-sensing coil -(P)-o Sets the bit (1) when rung to the left of the instruction transitions from OFF
(0) to ON (1)o The bit is left in this state in current cycle
● Negative transition-sensing coil -(N)-o Sets the bit (1) when rung to the left of the instruction transitions from ON
(1) to OFF (0)o The bit is left in this state in current cycle
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Unlatched vs Latched coils
IF ((A OR B) AND (NOT C) AND D) THEN E := 1; F := 1;
ELSE E := 0; F := 0;
END_IF;OR
AND
A
B
C D E
F
Branches
OR
AND
A
B
C D E
F
Branches
S
S
IF ((A OR B) AND (NOT C) AND D) THEN E := 1; F := 1;
END_IF;
Latched coils:
Unlatched coils:
(S like ‘Set’)
LD with Function Blocks - Comparison Instructions in LD
● Function blocks (FB) can be used in a ladder circuits● For example:● Comparison FBs● Timer FBs● Counter FBs
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TONIN
T#200ms
Pump_Tmr
PT ET 178
Q
CTU
200
Load_Cnt
PV CV 178
QIN
R
EQEN
100.000
ENO
78.251Tank_max
Tank1_Level IN1
IN2
Note: Computer Exercises: Lab1 PLC Programming
● Dateso (Group1 Tue 17/09 (08:15-10:00); if needed) o Group2 Tue 17/09 (10:15-12:00); o Group3 Thu 19/09 (14:15-16:00); o Group4 Thu 19/09 (16:15-18:00);o Group5 Fri 20/09 (08:15-10:00);
o Venueo In the PC class (AS5, TUAS)
● Remember to:o Enroll on MyCourses for one of the weekly sessionso See through the Codesys tutorials 1,2,3 and 5 (Youtube) before coming to
the labs
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Notes:
• See the following Codesys tutorials (Youtube) before coming to the labs:
• Codesys 01 Intro and Ladder (for Lab1)• Codesys 02 Structured Text• Codesys 03 Function Block Diagram• Codesys 05 Sequential Function Chart
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References• Introduction to Codesys:
• http://files.beijerelektronik.com.tr/downloads/Soft_Control/Dokumanlar/CoDeSys_Intro.pdf
• Codesys intro and tutorials 1,2,3 and 5 in YouTube• Codesys 01 Intro and Ladder• https://www.youtube.com/watch?v=2tX6gumm2zg&t=2s
• Codesys 02 Structured Text• https://www.youtube.com/watch?v=GP_3n8GgjOE
• Codesys 03 Function Block Diagram• https://www.youtube.com/watch?v=lirafGE6GxI&t=37s
• Codesys 05 Sequential Function Chart• https://www.youtube.com/watch?v=JP9_hhc1gRM
• Codesys Help Pages• Basics of ST (ST_Basics.pdf in materials)
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