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Lecture (03) Multiplexers, Decoders By: Dr. Ahmed ElShafee Dr. Ahmed ElShafee, ACUFOE : Spring 2020, Code - Name 1

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  • Lecture (03) Multiplexers, Decoders

    By:

    Dr. Ahmed ElShafee

    Dr. Ahmed ElShafee, ACUFOE : Spring 2020, Code - Name 1

  • Introduction

    • Integrated Circuits (ICs)

    – Small-scale integration (SSI)

    • NAND, NOR, AND, OR, inverter, Flip-Flop

    • 1-4 gates, 6 inverters, 1-2 Flip-flops

    – Medium-scale integration (MSI)

    • Adder, multiplexer, decoder, register, counter

    • 12-100 gates

    – Large-scale integration (LSI)

    • Memories, microprocessors

    • 100- a few thousand gates

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 2

  • – Very-large-scale integration (VLSI)

    • Microprocessors, FPGA, Application-specific integrated circuit (ASIC),…

    • Several thousand gates or more

    – Programmable logic devices (PLDs)

    • Programmable logic arrays (PLAs)

    • Programmable array Logic devices

    • (PALs)

    • Complex programmable logic devices

    • (CPLDs)

    • Field-programmable gate arrays (FPGAs) Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 3

  • Multiplexers

    • Multiplexers (MUX, or data selector)

    – A MUX has a group of data inputs and a group of control inputs.

    – The control inputs are used to select one of the data inputs and connect it to the output terminal.

    • 2-to 1 MUX

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 4

  • • 4-to-1, 8-to-1, 2n-to-1 MUX

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 5

  • Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 6

  • • Logic equation for 8-to-1 MUX

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 7

  • Multiplexers

    • Logic Diagram for 8-to-1 MUX

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 8

  • • Logic equation for 2n-to-1 MUX

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 9

    where mk is a minterm of the n control variables and Ik is the

    corresponding data input

  • • Quad Multiplexer Used to Select Data

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 10

  • • Quad Multiplexer with Bus Input and Output

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 11

    A=0, Z=X

    A=1, Z=Y

  • 74157 (Quad 2-line to 1-line data selectors) •

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 12

  • Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic Design II 13

  • Three-State Buffers

    • A gate output can only be connected to a limited number of other device inputs without degrading the performance of a digital system.

    • A buffer may be used to increase the driving capability of a gate output.

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 14

  • • A logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other.

    • Use of three-state logic permits the outputs of two or more gates or other logic devices to be connected together.

    • Three-state buffer (Tri-state buffer)

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 15

  • Enable input B=1, output C=A, when B=0, C acts like an open circuit, C is effectively disconnected from the buffer output so that no current can flow.

    This is referred to a Hi-Z (high-impedance) state of the output

    because the circuit offers a very high resistance or impedance to the flow of current.

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 16

  • • Four kinds of Three-State Buffers

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 17

  • • Data Selection Using Three-State Buffers

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 18

    D=B’A+BC

  • Decoders and Encoders

    • Decoder

    • Generates all of minterms

    • Exactly one of the outputs lines will be 1 for each combination of the values of the input variables.

    Dr. Ahmed ElShafee, NileU : Fall 2017, Microprocessor System Design 19

  • • 3-to-8 Decoder

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 20

  • • 4-to-10 Line Decoder with Inverted Output

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 21

  • • n-to-2n line decoder:

    • Generate all 2n minterms (or maxterms) of the n input variables Outputs

    • Noninverted

    – yi=mi , i=0,1,2,…,2n-1

    • Inverted

    – yi=mi’=Mi , i=0,1,2,…,2n-1

    • Use decoder and gates to realize a function

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 22

  • Example

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 23

  • Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 24

  • • Encoder

    – The inverse function of a decoder

    • 8-to-3 Priority Encoder

    Dr. Ahmed ElShafee, ACU : Spring 2020, CSE303 Logic design II 25

  • Thanks,..

    See you next week isA,..

    Dr. Ahmed ElShafee, ACUFOE : Spring 2020, Code - Name 26