Introduction of Intel Processors

Intel 4004 (First Microprocessor) : 1969First MicroprocessorRevolution from fixed functionality to variableHandled 4 bit dataHad 46 instructionsAllowed 4KB of program code and 1KB of data.

Intel 8-bit processorsThey are 8008, 8080 and 8085They were used in many early microcomputers in applications such as electronic instruments and printers

Intel 16-bit processorsThey included 8086, 8088 and 80286

Intel 32-bit processorsThey include 80386 and 80486.First they introduced 80386DX, 80386SX and 80386SL.It was compatible with 8088/8086/8028680386DX(DX refers to floating point capability)80386SX(SX refers to 16-bit data bus)It offers 24 bit address bus(16MB physical m/m)80386SL(offered several power management options and sleep modes to conserve battery power for laptops)

Intel 32-bit processor - 8048680486DX Improved with memory cache and math coprocessor80486SX Does not have math coprocessorClock doubler/tribler were also released (75% faster than the comparable non-doubled processor)DX2-66 33MHzDX2-50 25MHzDX4-100 25MHzDX4-75 25MHz

80386DX

Features of 80386DXIt supports 8/16/32 bit data operandsIt has 32-bit internal registersIt supports 32-bit data bus and 32-bit non-multiplexed address busIt supportsPhysical Address of 4GBVirtual Address of 64TBMaximum Segment size of 4GB

Features of 80386DXIt operates in 3 different modesRealProtectedVirtual 8086MMU provides virtual memory, paging and 4 levels of protectionClock Frequency : 20,25 and 33MHzIt has 132 pin package

Architecture of 80386UQ: Draw the block diagram of the 80386 DX Processor and explain each block in brief*

Architecture of 80386*Three Sections:Bus Interface unitsCentral Processing UnitMemory Management Unit

Architecture of 80386The internal architecture of 80386 is divided into three sections:

Central Processing UnitMemory Management UnitBus Interface unit*

Central Processing Unit*

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Central Processing UnitThe CPU is further divided into:Instruction UnitExecution Unit Instruction Unit:It decodes the opcode bytes received from the 16-byte instruction queue and arranges them into a 3-decoded instruction queue.After decoding it is passed to control section for deriving necessary control signals

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Central Processing UnitExecution Unit:It has 8 general purpose and 8 special purpose registers which either handles data or addressesThe 64-bit barrel shifter increases the speed of all shift, rotate, multiply and divide operationsThe multiply/divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time(Even 32bit multiplication is done in 1s)

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Central Processing UnitElement of the EUArithmetic/logic unit (ALU)Performs the operation identified by ADD, SUB, AND, etc.Flags registerHolds status and control informationGeneral-purpose registersHolds address or data informationControl ROMContains microcode sequences that define operations performed by machine instructionsSpecial multiply, shift, and barrel shift hardwareAccelerate multiply, divide, and rotate operations

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Memory Management Unit*

Memory Management UnitMMU consists of a segmentation unit and paging unitSegmentation Unit:It allows the use of two address components - segment and offset for relocability and sharing of dataIt allows a maximum segment size of 4GBIt provides a 4-level protection mechanism for protecting and isolating systems code and data from those of application program

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Memory Management UnitThe limit and attribute PLA checks segment limits and attributes at segment level to avoid invalid accesses to code and data in memory segment. Paging Unit It organizes physical memory in terms of pages of 4KB sizeIt works under the control of segmentation unitIt converts linear addresses into physical addressesThe control and attribute PLA checks privileges at page level.

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Bus Interface Unit*It has a prioritizer to resolve the priority of various bus requests. This controls the access of the busThe address driver drives the bus enable and address signals A2 A31.The pipeline/bus size unit handles the control signals for pipelining and dynamic bus sizing units

Bus Interface UnitThe data buffers interface the internal data bus with system bus

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NEXT : Signal Interface of 80386DX *

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