lect8_blg231e_2013_04_18

Digital Circuits

BLG231E

Instructor: Dr. Fuat Kucuk

BLG231E DIGITAL CIRCUITS by Fuat Kucuk 1


These lecture notes have been prepared on the basis of the course reference book.

Sequential Logic Circuits


A sequential circuit is another type logic circuit whose outputs are defined by past as well as present input values.

Such a circuit must remember the results of past input values.

This means that a sequential circuit is constructed by combinational circuits and memory (storage) elements.

Combinational

circuit Memory elements

Outputs inputs

Sequential Logic Circuits


The binary information stored in the memory elements at any given time defines the state of the sequential circuit at that time.

The next state of the storage elements is also a function of external inputs and the present state.

Thus, a sequential circuit is specified by a time sequence of inputs, outputs, and internal states.

There are two main types of sequential circuits and their classification depends on the timing of their signals: asynchronous sequential circuit synchronous sequential circuit

Types of Sequential Logic Circuits


A synchronous sequential circuit changes their states and output values at fixed points of time, which are specified by the rising and/or falling edge of a free-running clock signal.

The operation of the entire circuit is controlled and synchronized by the periodic pulses of the clock.

Combinational circuit

Memory elements

Outputs inputs

Clock

Types of Sequential Logic Circuits


An asynchronous sequential circuit changes their states and output values whenever a change in input values occurs.


Memory elements

Outputs inputs

Synchronous Sequential Circuits


The sequential circuit that is regulated by a clock signal is said to be synchronous.

Typical clock signal consists of periodic logic-1 pulses.

The clock pulses are generated by a device called clock generator.

A Clock Signal


Sync. Sequential Circuits

Clock period: time between two consecutive rising edges or falling edges (measured in ms,ns,or ps).

Clock frequency: the inverse of clock period (measured in KHz, MHz, or GHz).

Clock width: time during which the clock signal is high (value is 1).

Clock duty cycle: ratio of clock width and clock period.

Clocked sequential circuits



Synchronous sequential circuits that use clock pulses in the inputs of storage elements are called clocked sequential circuits.

These are the type most frequently encountered in practice.

The storage elements used in clocked sequential circuits are generally called, flip-flops.


Flip-Flops

Outputs inputs

Clock pulses

Synchronous clocked sequential circuits

General characteristics of Flip-Flops



Its a bistable device and capable of storing one bit information (0 or 1).

The state of the flip-flops can change only during a clock pulse transition.

A flip-flop circuit can maintain a binary state indefinitely as long as no pulse transition and no power brake is occured.

A flip-flop has two outputs, one of which is often the complement of the other.

SR Latch



Latches are basic memory devices which can store one bit of information.

They are often used for constructing all types of flip-flops.

The SR latch has two input signals, the set signal (S) and the reset signal (R) and two output signals, Q and Q'. Q is called the state of the latch.

SR latch

S

R

Q

Q'

outputs inputs

Schematical representation of SR latch

SR Latch



The SR latch can be constructed with two cross-coupled NOR gates

1.When S=R=0, the latch remains in its present state.

2.When S=1 and R=0, the latch is set to 1 state (thus, S is for set)

3.When S=0 and R=1, the latch is reset to 0 state (thus, R is for reset)

4.The condition S=R=1 is not permitted (undefine state).

SR Latch



The SR latch can also be constructed with two cross-coupled NAND gates

1.When S=R=1, the latch remains in its present state.

2.When S=1 and R=0, the latch is set to 0 state

3.When S=0 and R=1, the latch is reset to 1 state

4.The condition S=R=0 is not permitted (undefine state).

Example



For the series of input given below, a) Determine the type of storage element. b) Find the output Q.

Answer



For the series of input given below, a) This is an SR latch constructed with NOR gates.

Because R=0 and S=0 is allowed.

Note that the SR latches are level-sensitive.

Reset and set operations are executed only after the R and S inputs have reached to their appropriate levels.

Clocked SR Latch



An extension version of the SR latch has an additional enable input.

The enable input is connected to SR latch through two AND gates.

With the configuration, any transition can be controlled by enable input.

The enable input may consist of a clock, in which case the latch is called clocked and the operation is said to be synchronous.

Clocked SR Latch



Logic diagram

Function table

Clocked SR latch (NAND- type)

Graphic symbol

D Latch



One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 in NAND type (0 in NOR type) at the same time.

This is done by constructing another type latch called D latch.

Graphic symbol

AND-type D Latch

No change

No change

Reset state

Set state

Latches vs Flip-Flops



A latch enabling whenever C=1 is called a level-sensitive latch (or level-triggered latch).

When this type of latches is used in the sequential circuits, serious difficulty may occur.

Usually, the state transitions of the lathces requires that the clock pulse becomes logic level 1.

During logic level 1, changes in the input values may results a new state. The result is unpredictable, because the state of latches may keep changing for as long as the clock pulse stays in the logic level 1.




The problem with the latch is that it responds to a change in the actice level of a clock pulse.

The key to the proper operation of a flip-flop is to trigger it only during a signal transition.

A clock pulse has two different transitions. First is from 0 to 1, called positive edge transition. The second is from 1 to 0, called negative edge transition.




The clock transitions (edges) can be used to fix the change of the state of the memory elements.

The FFs that can change their states at only edges of the clock signals are called edge triggered FFs.

All versions of flip flops (FF) can be built by using the latches in different forms.

There are mainly two ways to construct edge-triggered FFs:

By using two D latches in a cascaded configuration (master-slave FFs) By using three SR latches in an interconnected configuration

Both configurations can be either positive edge triggered or negative edge triggered.

D-type Master – Slave FF



A master - slave FF is constructed with two D latches and an inverter.

Each time, one of the latches is enabled.

The output of the flip flop can change only during the transition of the clock from 1 to 0 (negative – edge triggered)

Negative edge triggered FF

Timing diagram

D-type Master – Slave FF



positive edge triggered FF

Graphical representations of edge triggered FFs

positive edge negative edge

D-Type positive edge-triggered FF


An edge-triggered FF can also be implemented with three interconnected SR latches: set, reset, and output latches.

Positive-edge-triggered FF (0-to-1 transition)

Set latch

Reset latch

Output latch




Effect of 0→1 transition on the D line




Effect of 0→1 transition on the clock line

JK Flip-Flops



The most economical and efficient FF constructed in this manner is the edge-triggered D flip-flop because it requires the smallest number.

Other types of FFs can be constructed by D Flip-flops and external logic circuits.

In a JK flip-flops, the J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are enabled, the output is complemented.

Graphic representation

Circuit diagram

T Flip-Flops



The T (toggle ) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs J and K are tied together.

Using JK flip flop

Using D flip flop

Graphical representation

Flip Flop Types and their characteristics



Flip flop types and their characteristic tables



lect8_blg231e_2013_04_18

Documents