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Computer Organization

Instructors :

Dr. Abdul Raouf Khan

Mr.Marwan El-Haj

Instruction Formats

� The common fields found in an instruction format

are:

1. An operation code field that specifies the

operation to be performed.

2. An address field that designates memory

address or a processor register

3. A mode field that specifies the way the operand

or the effective address is determined

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CPU organization

� Three types of Computer Organization

1. Single accumulator

2. General register organization

3. Stack organization

Single accumulator

� Basic computer is an example of single

accumulator type#

� Instruction formats eg. ADD X

where X is the address of the operand

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General register organization

� Instruction formats

� ADD R1, R2, R3 means R1� R2 + R3

Or ADD R1, R2 means R1�R1+R2

� Computers with multiple register organization

use MOV instruction for transfer

� MOV R1, R2 means R1� R2

� General register type computers use two or

three address fields in the instruction format

Stack organization

� Computers with stack organization use

PUSH & POP instructions

� PUSH x will push the word at address X to

the top of the stack.

� The insdtruction ADD consists of an

operation code only with no address field.

The instruction will pop two top numbers &

will add them and push the sum in the stack.

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Three address instruction

� X= (A+B)*(C+D)

� ADD R1, A, B R1�M[A] + M[B]

� ADD R2, C, D R2�M[C] + M[D]

� MUL X, R1, R2 M[X]�R1 * R2

Two address instruction

� X= (A+B)*(C+D)

� MOV R1, A R1�M[A]

� ADD R1, B R1�R1+M[B]

� MOV R2, C R2�M[C]

� ADD R2, D R2�R2+M[D]

� MUL R1, R2 R1�R1*R2

� MOV X, R1 M[X]�R1

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One address instruction

� X= (A+B)*(C+D)

� LOAD A AC�M[A]

� ADD B AC�AC+M[B]

� STORE T M[T]�AC

� LOAD C AC�M[C]

� ADD D AC�AC+M[D]

� MUL T AC�AC * M[T]

� STORE X M[X]�AC

Zero address instruction

� X= (A+B)*(C+D)

� PUSH A TOS � A

� PUSH B TOS � B

� ADD TOS �A+B

� PUSH C TOS � C

� PUSH D TOS � D

� ADD TOS �C+D

� MUL TOS�(C+D)*(A+B)

� POP X M[X]�TOS

� TOS means TOP OF STACK

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RISC Instruction

� RISC (Reduced Instruction Set Computer)

� The instruction set of a typical RISC processor is

restricted to the use of load and store instructions

when communicating between memory and CPU. All

other instructions are executed within the registers

without referring to memory. A program for a RISC

type CPU consists of LOAD & STORE instructions

that have one memory and one register address and

computational type instructions that have 3 address

with all 3 specifying processor registers.

RISC Instruction

� X= (A+B)*(C+D)

� LOAD R1, A R1�M[A]

� LOAD R2, B R2�M[B]

� LOAD R3, C R3�M[C]

� LOAD R4, D R4�M[D]

� ADD R1, R1, R2 R1�R1+ R2

� ADD R3, R3, R4 R3�R3+ R4

� MUL R1, R1, R3 R1�R1* R3

� STORE X, R1 M[X]�R1