lcfi collaboration status report
DESCRIPTION
LCWS 2004 Paris Joel Goldstein for the LCFI Collaboration Bristol, Lancaster, Liverpool, Oxford, RAL. LCFI Collaboration Status Report. R&D for a vertex detector at NLC or TESLA Physics Studies (See Sonja Hillert’s talk in Simulation session) Mechanical Development Ultra low-mass ladders - PowerPoint PPT PresentationTRANSCRIPT
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LCFI CollaborationStatus Report
LCWS 2004
Paris
Joel Goldstein
for the LCFI Collaboration
Bristol, Lancaster, Liverpool, Oxford, RAL
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Joel Goldstein, RAL LCWS 20/4/04 2
LCFI Research Programme
R&D for a vertex detector at NLC or TESLA
1. Physics Studies(See Sonja Hillert’s talk in Simulation session)
2. Mechanical Development• Ultra low-mass ladders
• FEA/physical models
3. Detector Development• Fast CCD technology (50 MHz for TESLA)
• Custom CMOS readout chips
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Joel Goldstein, RAL LCWS 20/4/04 3
LC Vertex Detector
• 800 Mchannels of 2020 m pixels in 5 layers
• Optimisation:– Inner radius (1.5 cm?)
– Readout time (50 s?)
– Ladder thickness (0.1% X0?)
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Joel Goldstein, RAL LCWS 20/4/04 4
Mechanical Options
Target of 0.1% X0 per layer
(100m silicon equivalent)
1. Unsupported Silicon– Longitudinal tensioning provides stiffness– No lateral stability– Not believed to be promising
2. Semi-supported Ultra-thin Silicon– Detector thinned to epitaxial layer (20m)– Silicon glued to low mass substrate for lateral stability– Beryllium has best specific stiffness– Composites, ceramics, foams...
3. Novel Structures
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Joel Goldstein, RAL LCWS 20/4/04 5
Mechanical Studies of Be-Si
FEA Simulations Physical Prototyping• Laser survey system
Thinned CCD ( 20 μm)
Beryllium substrate (250 μm)
Adhesive
0.2mm
~160 μm ripples at -60°C
• Good qualitative agreement
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Joel Goldstein, RAL LCWS 20/4/04 6
New Approaches
• Be-Si unstable when cooled due to CTE mismatch
• Choose substrate with closer CTE match– 100 μm carbon fibre – ceramic foam
• Micromechanical techniques....
Microstages
replace glue pillars
Sandwich
UV lithography on dummy
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Joel Goldstein, RAL LCWS 20/4/04 7
Column Parallel CCD
N+1
Column Parallel CCDReadout time = (N+1)/Fout
• Separate amplifier and readout for each column
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Joel Goldstein, RAL LCWS 20/4/04 8
Prototype CP CCD
CPC1 produced by E2V
• Two phase operation
• Metal strapping for clock
• 2 different gate shapes
• 3 different types of output
• 2 different implant levels
Clock with highest frequency at lowest voltage
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Joel Goldstein, RAL LCWS 20/4/04 9
CPC1 Results
• Noise ~ 100 electrons (60 after filter)
• Minimum clock ~1.9 V
• Maximum frequency > 25 MHz– inherent clock asymmetry
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Joel Goldstein, RAL LCWS 20/4/04 10
CP Readout ASIC
CPR1 designed by RAL ME Group
• IBM 0.25 μm process
• 250 parallel channels with 20μm pitch
• Designed for 50 MHz
• Data multiplexed out through 2 pads
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Joel Goldstein, RAL LCWS 20/4/04 11
CPR1 Testing
• Flash ADCs tested
• Voltage and charge amplifiers tested
• Voltage gain ~40
• Very sensitive to timing and bias values
• Outstanding digital problems
• Charge amplifiers not fully understood
Voltage injection into ADC
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Joel Goldstein, RAL LCWS 20/4/04 12
Wirebonded Assembly
• Total noise ~130 electrons
• Noise from preamps negligible
Bump bonding underway at VTT
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Joel Goldstein, RAL LCWS 20/4/04 13
Future Detector Work
• Test Programme– Bump bonded assemblies expected early May– Radiation effects on fast CCDs– High frequency clocking
• Next Generation CCDs and ASIC– Detector scale CCDs– Cluster finding logic– Design underway; production later in year
• In-situ Storage Devices– Resistant to RF interference– Reduced clocking requirements(See Chris Damerell’s talk on Thursday)
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Joel Goldstein, RAL LCWS 20/4/04 14
Summary
• Excellent progress over past two years– Mechanical options studied in detail
– CCD+ASIC operation achieved
– New ideas being discussed
• CP CCDs are viable technology for linear collider
• Next generation will be full-scale prototype CCDs
Accelerator technology choice will determine path