laboratory 3 - college of engineering of electrical and computer engineering, university of...

Department of Electrical and Computer Engineering, University of Saskatchewan

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EE 342 (VLSI Circuit Design)

Laboratory 3

- Using Spectre netlist and Calculator for simulation

By Mulong Li, 2013


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Background knowledge

Spectre: is a SPICE-class circuit simulator. It provides the basic SPICE analyses and

component models. Spectre comes in enhanced versions that also support RF simulation

(SpectreRF) and mixed-signal simulation (AMS Designer). It was developed at Cadence

Design Systems, and is currently a leading circuit simulator, competing with HSPICE and

several others

Netlist: describes the structure of circuits and subcircuits by listing components, the

nodes that the components are connected to, the parameter values that are used to

customize the components, and the analyses that you want to run on the circuit.

Common Linux commands: Below are some of the most common Linux commands that

you may need to use in this tutorial.

- cd /directorypath: Change to directory

o “.” indicates the current directory, “..” indicates the parent

directory, “~” indicates the user’s home directory. For example,

“cd ..” means move to the parent directory

- pwd: Show the path of the current directory

- ls: List directory contents

- cp source destination: Copy files and directories

- mv source destination: Rename or move file(s) or directories

- mkdir directory: Create a new directory

- rm filename: Permanently remove file(s) and/or directories.

- gedit filename [&]: Open a file with gedit text editor. If file name does

not exist, create a new one. Add “&” to run the job in background, so that

you can run other commands using the current terminal window when the

job is running


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1 Netlist and Spectre syntax

In this tutorial, we will run the simulation by writing a netlist in Spectre. Spectre syntax

is different from SPICE. In this part, we are going to create a simple netlist file using

Spectre syntax.

1.1 Login the Linux machine and open a new terminal window.

1.2 Create a new directory

a) In the terminal window, create a new directory for this course and this lab in your cabinet:

$ mkdir ~/cabinet/CME342/cadence_netlist

b) Go to the newly created directory.

$ cd ~/cabinet/CME342/cadence_netlist/

And source the toolkit again:

$ source /CMC/scripts/kit.tsmc180nm.5.2.csh

c) We will then create the netlist file and run simulation under this directory.

d) In the current directory, create a new text file called “example_ckt.scs”.

$ gedit example_ckt.scs

e) Read carefully and try to understand the following codes, and then copy them into the

“example_ckt.scs” file:

//Design cell name: example_ckt

simulator lang=spectre //use Spectre syntax

global 0 vdd! //set global signals

//include model library

include "/usr/local/bin/cadence_lib/models/spectre/icfspectre.init"


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//vdd! voltage is 1.8V

V0 (vdd! 0) vsource dc=1.8 type=dc

//V1 is a pulse shape voltage source

V1 (net_a 0) vsource type=pulse val0=0 val1=1.8 period=2n delay=1n width=1n

//M0 (d g s b) is a 500nm*180nm PMOS

//as, ad: source/drain area; ps, pd: s/d perimeter; nrs, nrd: # of squares in s/d

M0 (net_out vdd! vdd! vdd!) pch w=500n l=180.00n as=0.48u*(500n) \

ad=0.48u*(500n) ps=0.96u+2*(500n) pd=0.96u+2*(500n) \

nrd=0.27u/(500n ) nrs=0.27u/(500n) m=1 region=triode

M1 (net_out net_a vdd! vdd!) pch w=500n l=180.00n as=0.48u*(500n) \

ad=0.48u*(500n) ps=0.96u+2*(500n) pd=0.96u+2*(500n) \

nrd=0.27u/(500n) nrs=0.27u/(500n) m=1 region=triode

M2 (net_out net_a net1 0) nch w=500n l=180.00n as=0.48u*(500n) \

ad=0.48u*(500n) ps=0.96u+2*(500n) pd=0.96u+2*(500n) \

nrd=0.27u/(500n) nrs=0.27u/(500n) m=1 region=triode

M3 (net1 vdd! 0 0) nch w=500n l=180.00n as=0.48u*(500n) ad=0.48u*(500n) \

ps=0.96u+2*(500n) pd=0.96u+2*(500n) nrd=0.27u/(500n) \

nrs=0.27u/(500n) m=1 region=triode

//run transient analysis, set the stop time to 5ns

tran tran stop=5n write="spectre.ic" writefinal="spectre.fc" \

annotate=status maxiters=5

//save all signals

saveOptions options save=allpub

f) Save the file.


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1.3 Now with the circuit structure in the netlist, we can start doing some

simulation.

a) In the terminal, start the Spectre simulation with the following command: (-f psfascii

specifies the output data format)

$ spectre example_ckt.scs –f psfascii

b) Then you will see the transient analysis running.

c) When the terminal shows “spectre completes with 0 errors, X warnings, and 0

notices”, the simulation is done. Now you’ll see a new directory “example_ckt.raw”

under your “cadence_netlist” directory. All the simulated signals are saved in it.

1.4 Now we will use “Results Browser” to view our simulation results.

a) Go up to your home directory ($ cd ~), and start the Cadence program ($ cadence).

b) In the icfb window, select “Tool -> Analog Environment -> Results Browser…”. Open

“example_ckt.raw -> tran-tran”, you’ll see a list of signals in the example circuit, similar

to Figure 1-1.

Figure 1.1

c) Choose the signals you want to see, and click “Plot signal”. A graph window will

pop out as in Figure 1-2.


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Figure 1.2

Exercise A:

Design a 3-input NOR gate in netlist, with transistor widths chosen to achieve

equal rise and fall resistance as a unit inverter (assume a unit inverter has size:

N 500nm, P 1um). Inputs are net_a = net_b = 0 and net_c = 500MHz pulse,

output is net_out. Measure the net_c to net_out delay.


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2 Virtuoso Tools and Calculator Now we will use Virtuoso tools to build circuits and run simulations in a more

straightforward way. Let’s start by making a simple D-latch.

2.1 Create schematic

a) In icfb window, open Library Manager. Select library abc123 (your NSID), and create a

new schematic view with cell name “D_latch” (never use “-” when naming libraries or

cells, the tool may not recognise it).

b) Add nfets and pfets to the schematic. Also we need to add supplies vdd and gnd from the

library “analogLib”. Press “q” to change the size of the transistors so that the width of

NMOS and PMOS are 500nm and 1um respectively, while the lengths are both 180nm.

The schematic should now look like this:

Figure 2.1


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c) Now connect all the instances.as in Figure 2-2. Don't forget to connect bulk terminals of

pfets to vdd and that of nfets to gnd by adding wire names vdd! and gnd!.

Figure 2.2

d) Add 3 input pins: D_in, Clock and Clock_bar to the left, and 2 output pins: Q_out and

Q_bar on the right.


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e) Add wire corresponding names to connect to all the pins. Remember to click “Check and

save” to see if there’s any error!

Figure 2.3

f) Create a symbol view as well.

2.2 Schematic simulations

a) After the schematic and symbol view are created, we need to create a testbench cell and

instance the latch within it to test its functionality.

b) First, select library abc123 in the Library Manager, and create a new Schematic cell view

called “D_latch_tb”.

c) Add instances of “vpulse” and “vdc” from “analogLib” to “D_latch_tb”, as well as “vdd”

and “gnd”. Also add the symbol of “D_latch” created in the previous step. Add 2 output

pins Q and Qbar. Connect all the components as in Figure 2.4.


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Figure 2.4

d) Modify the properties of the added components.

For vpulse to D_in

Figure 2.5


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For vpulse to Clock_bar

Figure 2.6

For vpulse to Clock

Figure 2.7

For vdc

Figure 2.8

e) Keep all the other parameters default. Check and save.


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2.3 Waveform results

a) Click “Tools -> Analog Environment” to open ADE window.

b) Go to “Setup -> Model libraries…”. Add Model Library File

“/usr/local/bin/cadence_lib/models/spectre/icfspectre.init”.

c) Go to “Outputs -> Save All… -> Select power signals to output (pwr)”, check “total”.

This step is needed for estimating power later on.

d) Go to “Analyses -> choose…”, choose “tran”(transient analyses) and set “stop time” to

500ns. Long stop time is needed for more accurate average power estimation. Click OK.

e) Select all the inputs and outputs of the D-latch to be plotted. Press Esc after you have

selected all the signals you need, you’ll see the signals now in ADE.

f) Click to start simulation. It will take up to several minutes to do compiling work for

the first time. When the simulation is done, a plot will pop up showing the simulation

results. (You can check the error information in icfb window if any)

Figure 2.9


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g) Click “Strip Chart Mode” to separate signals. Check if your D-latch works properly.

2.4 Calculator

a) Delay

1). Click “Tools -> Calculator…” to open the Calculator. Make sure “vt” under tab “tran”

is selected.

Figure 2.10

2). We will now use the “delay” function to measure the D to Q delay of the Latch. Click

on “delay” in the function panel, and you will see the delay function window as in Figure

2.11. Adjust the window to see all the options.

Figure 2.11


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3). Click in “Signal1” field, then switch to the Schematic window, and click on the D_in

(input) signal. You will notice that the “Signal1”filed is now replaced by the vt signal of

the wire you click on.

4). Repeat the last step to replace “Signal2” with Q (output) signal.

5). Set Threshold Value to 0.9 and the other parameters default as show in Figure 2.11.

Set “Edge Type” to both rising or both falling, so as to measure rising or falling edge

delay.

6). Click Apply, then click plot . The delay should be evaluated to around 25ps.

b) Frequency

1). Calculate signal frequency with the frequency function.

2). Click on clk (clock) signal in the schematic, then go back to Calculator and click on

frequency function. Click Plot, the frequency should be evaluated to about 100MHz.

c) Power Consumption

1). In the Graph window, go to “Tools -> Results Browser”.

2). Select “tran-tran”, and double click on “\:pwr”. The Graph window will pop up.

Figure 2.12


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3). Go to Calculator, click “average” in the function panel, and click plot, you’ll get an

average power consumption of 5.1 uW.

4). Select “wave” in “Selection choices”, switch to Graph window and click on the

dynamic power waveform. Switch back to Calculator and choose function “ymax”. Click

Plot, and you’ll obtain the maximum power consumption of 0.37 mW.

Exercise B:

1. Design a D latch with an ENABLE signal using NAND gates (P 1um, N 1um). Draw

the schematic, build a test bench to test its functionality, and measure its D to Q

delay and average/maximum power consumption using Calculator function.

2. Design a 1.2 GHz ring oscillator using the following inverter size: P 1um, N 500nm.

Use Calculator to verify its frequency. (Hint: set Initial Condition to make it

oscillate )

Report:

1. Exercise A: Netlist of your NOR gate

2. Exercise B1: Schematic of D latch and its test bench

3. Exercise B2: Schematic of ring oscillator

4. Waveforms of all the simulation along with your Calculator results

Instruction:

How to print schematic with a white background? (If you want to save some ink)

Method 1:

Invert colors in “Paint”. Or in Microsoft Word 2010, click on your figure, go to Picture tools -> Format -> Color -> Set Transparent color -> click on the black background.


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Method 2:

This method will change all the schematics and layouts background color in your

current cadence session.

Type the following command in your terminal:

echo "Opus.editorBackground: white" | xrdb –merge

You have to restart cadence to make it work.

To change back to black background:

echo "Opus.editorBackground: black" | xrdb -merge

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