lab4 nand schem sim

7/29/2019 Lab4 Nand Schem Sim

1/20

ECE 126 Logic Gate Creation: 2 input NAND Gate Schematic + Test Bench

Created at GWU by Anis Nurashikin Nordin & Thomas Farmer

Objectives:

Create a schematic for a 2 input NAND gate

Create a symbol for a 2 input NAND gate

Create a test bench for a 2 input NAND gate, that allows for transient simulation to verifyfunctionality of NAND gate

Create a test bench for a 2 input NAND gate, that allows for a swept DC analysis Create a layout for a 2 input NAND gate

Create an AND gate using Inverter (from Lab 3) with NAND gate (from this lab)

Assumptions:

Student has successfully completed Lab 1, 2, and 3

Part 1: Creating NAND Schematic

1. Login to workstation and start cadence

2. From the Library Manager, click on your DIGITAL libraryo Choose File->New->Cell Viewo Fill in the form:

o Library Name: Digitalo Cell: nand2o View: schematico Type: schematico Application: Schematics-L

3. Instance parts: pmos4, nmos4, vdd, gnd, to create the following schematic

o For now, use minimum sizes for W/L of each transistor, later you will adjust them


2/20

o You must rotate the PMOS and NMOS SIDEWAYS by doing the following:

Before Rotate After Rotate

(notice, current flow direction is still the same)

o Menu: Edit->rotate or press the letter ro Click Sidewayso Note the current flow direction after you rotate is still correct! (this is

important)o You can also rotate the input/output pins as well

4. Check and save schematic, make sure there are no warnings/errors


3/20

Part 2: Creating NAND Symbol

1. In the schematic editor, from the menu choose: Create->Cellview->From Cell Viewo Accept the defaults and press OKo The symbol editor appears

2. Press the delete key and click on the green box and red box in the editoro Do NOT delete the PINS or labels for the PINS, if you do, close the window and DO not

save, simply restart from step 1 above

3. Create the following symbol:

o From the menu choose: Create->Shape->Line, draw the left, top and bottom lines

o

o Choose Arc shape to draw the Arc of the NAND gateo Choose the Circle shape to draw the circle of the NAND gate

4. Save and close the symbol5. Save and close the schematic


4/20

Part 3: Creating the Functional Test Bench

1. From the Library Manager, click on your DIGITAL libraryo Choose File->New->Cell Viewo Fill in the form:

o Library Name: Digitalo Cell: nand2_tbo View: schematico Type: schematico Application: Schematics-L

2. Instance parts: 1 vdd, 4 gnds, 2 vpulse, 1 10pF capacitor, and your NAND gate, to createthe following schematic:

3. Add wire names to the input and output wires:1. From the menu, choose: Create->Wire Name2. Type the letter A then click on the wire you wish to name3. Repeat this process for wires: B and OUT

4. This gives names to your nets, as opposed to the random net7 type names5. This is very helpful when you are viewing your simulated results


5/20

4. Select each Pulse Input, press the letter q and set the vpulse properties as follows:

vpulse attached to A vpulse attached to B

5. Notice the overlapping periods in the figures above6. Set the VDC (for VDD) voltage to 5V7. Set the capacitor to 10pF

8. Save the schematic, and perform a transient analysis as follows: From the menu, choose: Launch->ADE-L Ensure that you use the Spectre simulator Choose Analysis type to be: transient lasting for 150u seconds (notice: thats about 4

cycles of vpulse B)

Plot the signals of Nets A, B, and OUT (from the schematic) as shown below (now yousee why we labeled the wires)

Run the simulation


6/20

When the resultant graph appears, choose from the menu: Axis->Strips to separate thesignals

Is it working?

Look at the graph for A, and B, when they are at 5V, this indicates a logical 1. Whenit is at 0 volts, this indicates a logical 0.

Write out the truth table for a 2 input NAND gate. See if the logic values for the OUT net match up with your expectations.

9. Once everything is working, save the STATE of the simulator and call it:nand2_functional_test

10. Close the simulator and schematic


7/20

Part 4: Creating the VTC Test Bench

1. From the Library Manager, click on your DIGITAL library

Choose File->New->Cell View Fill in the form:

o Library Name: Digitalo

Cell: nand2_tbo View: schematic_vtco Type: schematico Application: Schematics-L

By using this View Name, you may see the following error message:

o Answer YES to this error. It is occurring because were putting 2 schematics under 1 cellname

2. Instance parts: (1) vdd, 3 gnds, (2) vdcs, (1) 10pF capacitor, and your NAND gate, to createthe following schematic:

o Tip: You can copy and paste most of this stuff from your other test bench:o Select everything in your old schematico Press c and point at the selected componentso Then in your new schematic, point where you want the copy to be put

o Add Wire Names: IN and OUT (do NOT use A, B, OUT as before)o Set the DC voltage of the VDC attached to both inputs of the NAND gate, to 0

Why have we tied the inputs together???-if you look at the schematic, tie the inputs together in your mind, and youll see weve justturned our NAND gate into an inverter!-were now going to size the pmos and nmos just as we did in lab2 to obtain a midpoint onthe VTC graph


8/20

3. Click on the NAND symbol, press the letter X to descend into the schematic viewo Make sure you use capitol Xo Set the Width of bothPMOS transistors to a variable named: w_po Set the Width of bothNMOS transistors to a variable named: w_no Save the schematico Press the letter b to return to the test bench view

4. Open up the simulator, use Spectre, and create a DC analysiso Choose the sweep variable to be a Component Parameter and select the DC input to

your NAND gate as the component to be varied, from 0 to 5 volts as follows:o If you have forgotten these steps, see Lab 2 for detailed instructions

o Your components may have different names, so dont just fill in the form, select from theschematic

5. Copy the Variables you setup from the cell view:o From the menu, choose: Variables->Copy From Cell Viewo Give them default values by clicking on them:

o w_p=1.5uo w_n=1.5u

6. Choose the OUT Net to be plottedo This will plot the Output net vs. the swept component (the input!)


9/20

7. Your simulation should look like this:

8. Run the simulation and youll see the following output:

o The problem is that this VTC curve doesnt have X=Y=2.5 (midpoint), the PMOS andNMOS are not sized properly for optimum performance

o How to size them:

o In Lab 2b, you were shown how to perform a parametric analysis.o Perform a parametric analysis, leave w_n=1.5u and vary w_p

If that doesnt work, fix w_p=1.5u and vary w_no Once midpoint is achieved, go back and update your schematic with the proper

sizeso What is the ratio? How much bigger (or smaller) is the NMOS than the PMOS?

Any theories on why this is? It will eventually be a HW questiono In the simulator window, assign the optimum values for w_n and w_p

9. Save the STATE of the simulator, calling it: nand2_vtc10. Save the schematic and exit, rerun the simulation from part 3 to see if timing has changed!


10/20

Part 5: Creating the VTC Test Bench

1. From the Library Manager, click on your DIGITAL library

Choose File->New->Cell View Fill in the form:

o Library Name: Digitalo

Cell: nand2o View: layouto Type: layouto Application: Layout L

2. When the layout editor comes up, press the letter i to instance the following cells

NCSU_TechLib_ami06->pmos->layoutNCSU_TechLib_ami06->nmos->layout

3. Place the nmos & pmos in your editor as follows:

The distance between them is not important, you will change them later based on theDRC rules

Press the keys: f and this will fill in the outlined instances you see on theright in the figures above. To put it back to the outlined view, you may press f

This is a shortcut way to drawing the nmos & pmos, they are special layout cellscalled: parameterized cells, because we can change their attributes


11/20

4. Click on the PMOS device, press the letter q to bring up its attributes

Click on the Parameter button

Change the Multiplier field equal: 2

This indicates you want 2 PMOSdevices Make the width & length the same as

the width & length from your schematic

Press OK

Repeat this process on the NMOSdevice

5. After updating both the PMOS and NMOS devices, your layout should look as follows. Noticethe width & length are exactly as set in the parameter box above (W=1.5u L=.6u)


12/20

6. Instance (using the letter I) the following parameterized cells to create the body contactsfor the PMOS & NMOS devices:

NCSU_TechLib_ami06->ptap->layoutNCSU_TechLib_ami06->ntap->layout

Place the taps as you see below.

Outlined view (press f ) Filled-in view (press f)

A n-tap taps the n-well, forming a low ohmic contact to the n-well, typically called the

body contact for the pmos device. A p-tap taps the p-substrate, forming a low ohmic contact to the p-substrate, typically

this is called the body contact for the nmos device.

These taps are also parameterized cells, and you can increase the # of contacts to thebody of the device by changing appropriate parameter. As an example, select the n-tapdevice, press the letter q

Change the columns of contacts field to read 5 instead of 1. Press OK, and you seeyou now have 5 contacts to the n-well as shown on the right in the figure below.

For the remainder of this example, Ive set mine to 1, but you may wish for more contactsto the body, to ensure the n-well is at a common voltage potential


13/20

7. Connect the gates of the PMOS and NMOS devices by using the rectangle tool (pressingthe letter r), to draw a rectangle of poly, as follows:

8. Draw a rectangle of Metal-1 to connect the PMOS sources to the body contact for the PMOSdevices as follows:


14/20

9. Whenever poly crosses over an active area, a gate & drain are created. Which is source &which is drain is determined by how we electrically connect the terminals. Notice in the figurebelow that by placing this Metal-1 contact to the body terminal, we have assigned thesource & drain for the PMOS devices:

Shows Source, Drain, & Body of each PMOS

Notice the Sources overlap

10. Perform the same step, connecting the drain of the last NMOS device, to the body terminal(the p-tap):

11. Connect the drain of the first PMOS device to the drain of the first NMOS device using metal-1 as follows:

S1 B1

D1

S2B2

D2

S1

B1

D1

S2B2

D2


15/20

12. Remember, the drain & source of an NMOS or PMOS device are interchangeable. It is thevoltage we apply across them that forces the terminals to behave as the drain or the source.We have assigned the drains and sources for the NMOS devices by virtue of how weveconnected them:

Shows source, drain, body of each NMOS

Notice S1 & D2 are electrically connected

13. Connect the drain of the 2nd

PMOS device to the drain of the 1st

PMOS device & 1st

NMOSdevice as follows:

14. From the menu, choose Verify->DRC, ensure that you have no DRC errors:

S1

B1D1

S2

B2

D2

S1

B1

D1

S2

B2

D2


16/20

15. If you do have DRC errors, you must work to resolve them prior to going to the next step.

16. Once you have no DRC errors, place the input pins, and voltage supply jumpers as follows:

The A & B pins are of type INPUT on the poly-layer

The OUT pin is of type OUTPUT on the metal-1 layer

The vdd! and gnd! Pins are of type JUMPER on the metal-1 layer

17. Save the layout, then run the DRC check again, ensure 0 DRC violations

18. From the menu choose: Verify->Extract, remember to set the switch: Extract Parasitic Caps


17/20

19. Ensure the extraction has 0 errors from the CIW window.

20. After ensuring there are 0 errors, close the layout, and open the extracted view from theLibrary Manager:

Outlined View Filled in View (press f)

21. Press f, then click on the drains of the PMOS device, ensure the proper terminal pinsare being highlighted. Double check the extraction, see if the transistors are the correct sizeand wired as corrected.


18/20

22. From the menu, choose: Verify->LVS, populate your form as follows:(if a warning comes up, choose FORM CONTENTS)

23. Press the RUN button, then look at the OUTPUT & verify that the output is error free andthat the netlists of the schematic and layout match


19/20

Your output may not be exactly as it is above, but the netlists must match regardless.


20/20

24. Open the schematic view of the NAND gate, from the LVS window, back-annotate the

parasitics to the schematic:

25. After adding the parasitics to the layout, re-simulate the NAND device and check the transientoperation noting the effects of the parasitics.

lab4 nand schem sim

Documents