key technology challenges in computing package...

Key Technology Challenges in Computing Package and Assembly Kinya Ichikawa Assembly Technology Development Japan, Intel Corporation

1

Kinya Ichikawa iNEMI Substrate & Package Technology Workshop 2014 2

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Agenda Key Messages Technology Drivers

The Evolving World of Computing & Data

Industry Challenges

First Level & Second Level Interconnect Pitch Scaling

2.5D & 3D Packaging

Ultra Thin Packaging

IoT & Wearable Packaging

Closing Remarks IoT: Internet of Things


Key Messages • Technology getting more complex Gen-over-Gen….

– Moore's Law is alive and fueling the “Compute Continuum” revolution

– Packaging is a key enabler of the Si scaling & Computing User experience

• Significant Opportunities Enabled by Next Generation Packaging

– Industry wide investment and innovations required

– Require total Assembly solution – Equipment, process, Material & Total Cost of Ownership

– Need Direct Collaboration across the supply chain


Agenda Technology Drivers


Industry Challenges

First Level / Second Level Interconnect Pitch Scaling

2.5D / 3D Packaging


IoT/Wearable Packaging

Closing Remarks


Hi-K Metal Gate

Strained Silicon

3D Transistors

65 nm

45 nm

32 nm

22 nm

14 nm

10 nm

7 nm

90 nm

Enabling new devices with higher

functionality and complexity while

controlling power, cost, and size

6

Executing to Moore’s Law A Predictable Silicon Track Record


Packaging Evolves As Scaling Creates New Markets

1970’s A) Wirebond B) Leadframe C) Plastic & Ceramic D) Low Pincount DIPs

1990’s A) Wirebond & Flipchip B) Laminate C) Ceramic & Organic D) High Pincount PGA Thermally Enhanced

2010’s A) Pb-Free Flipchip B) Very Thin Laminate C) Organic D) High Pincount LGA & BGA

Ultra-Small Form Factors

Early CPU Memory

Servers Tablets & Phones

Desktop Workstation Mobile

Client PC


Conflict-Free Processors

8

8


A New World of Personalized Computing Cost Effective Processing Available Everywhere

2020: 31Billion Connected Devices & 4 Billion Connected People Source : IDC

Kinya Ichikawa iNEMI Substrate & Package Technology Workshop 2014 10 Kinya Ichikawa iNEMI Substrate & Package Technology Workshop 2014

Incredible Growth in Data Consumption Growth in mobile devices is having a tremendous impact on data traffic


Industry Trends in Computing Packages Expanding Portfolio of Solutions

50

500

5000

1 2 3 4 5

I/O

Co

un

t

Chip to Package Area Ratio

WLP/ DCA

FC-CSP

FC-BGA PoP

FC-LGA

FC-BGA

Data Center Client Ultra-Mobile Wearables/IoT

Pitch Scaling 2.5D/3D integration Ultra-thin and small Low Cost WLP/DCA

IoT: Internet of Things


Technology Driver & Challenges

1. The first level interconnect (chip to package) and the second level interconnect (package to board) Pitch Scaling are the essential to decrease the gap with the relentless silicon technology scaling

2. Increasing bandwidth density within the package drives innovation including logic and memory interconnects with 2.5D and 3D Integration

3. Meeting the push for Ultra-Thin form factors will require advances in thin wafer handling, thin die assembly, thin substrate manufacturing, and package warpage controls

4. System densification in Wearable/IoT drives innovations in Wafer Level Packaging / Direct Chip Attach and Low Cost Flip Chip technology to enable further reduction in cost, size and power


Agenda Technology Driver


Industry Challenges

First Level / Second Level Interconnect Pitch Scaling

2.5D / 3D Packaging



Closing Remarks




Industry Challenges

First Level & Second Level Interconnect Pitch Scaling

2.5D & 3D Packaging

Ultra thin Packaging


Closing Remarks



Driver #1

The first level interconnect (chip to package) and the second level interconnect (package to board) pitch scaling are the essential to decrease the gap with the relentless silicon technology scaling

First Level Interconnect (FLI)

Second Level Interconnect (SLI) Intel Scaling Trend


45 nm45 nm175um Pitch175um Pitch



Pb Bump

Package

Pb/Sn Solder

Chip

Cu Bump

Pb/Sn Solder

Package

Chip

Cu Bump

Sn/Ag/Cu Solder

Package

Chip




Pb Bump

Package

Pb/Sn Solder

Chip

Cu Bump

Pb/Sn Solder

Package

Chip

Cu Bump

Sn/Ag/Cu Solder

Package

Chip




Pb Bump

Package

Pb/Sn Solder

Chip

Cu Bump

Pb/Sn Solder

Package

Chip

Cu Bump

Sn/Ag/Cu Solder

Package

Chip




Pb Bump

Package

Pb/Sn Solder

Chip

Cu Bump

Pb/Sn Solder

Package

Chip

Cu Bump

Sn/Ag/Cu Solder

Package

Chip

32 nm145 um Pitch




Pb Bump

Package

Pb/Sn Solder

Chip

Cu Bump

Pb/Sn Solder

Package

Chip

Cu Bump

Sn/Ag/Cu Solder

Package

Chip




Pb Bump

Package

Pb/Sn Solder

Chip

Cu Bump

Pb/Sn Solder

Package

Chip

Cu Bump

Sn/Ag/Cu Solder

Package

Chip

22 nm130 um Pitch

Sn/Ag/Cu Solder

Cu Bump

Sn/Cu Solder

Cu Bump

Chip-to-Package Interconnect Trend in Minimum Flip Chip Bump Pitch at Intel

Bu

mp

Pit

ch (μ

)

Bump pitch scaling challenges include chip attach, Chip-Package-Interaction & substrate advancement


Key Industry Challenges for FLI Scaling Creating a Robust Flip Chip Interconnect

Chip-Package-Interaction - Low K ILD Integration

Assembly Process Yields - Solder collapse vs. Warpage

Joint Fatigue Current Carrying Capability

Flip chip Metallurgy

- Cu bump with Pf free solder, Cu-Cu Chip Attach Process

- Reflow, TCB and die embedded Underfill

- Capillary, Mold and Pre-applied

Warpage > Collapse

Electro Migration Bump Crack Assembly Yield Chip-Package-Interaction


Thermal Compression Bonding Process for Fine

Pitch Chip Joint (less than 100um pitch)

X/Y & Z Placement Accuracy

Precision temp control

Process Cost

Require Integration of Fluxing and Underfill

0 200 400 600 800 Die Thickness (um)

0

50

100

Ass

em

bly

Yie

ld (

%)

Small die Middle

die Large die

Die warpage= function of die diagonal length and thickness

Substrate Dynamic warpage

Si Die Dynamic warpage

Warpage > Collapse

Non Contact Open

Solder Collapse Chip Attach Fine Pitch & Smaller Solder Bumps Limited by Die & Substrate Dynamic Warpage

Mass Reflow Flip Chip

TCB Flip Chip


60 60

48 48 45

40 35

30 30 25 25

22 22 20 20 20

Routing Line Pitch, μm

60 50 50

40 40 35 35

30 30 25 25 25

67 67 64 64 64 60 60 60 60 60 50 50

Micro-via Diameter; μm ITRS Roadmap Industry Average

Substrate and Board Technologies Scaling Required to take full advantage of Si-scaling

Advanced, alternate technologies to achieve a low cost solution to enabling finer L/S (<10 μm) pitch

Alternate technology needed to shrink via size and tolerance Low CTE materials needed for

improved via reliability

60 μm via diameter


Second Level Interconnect Challenges Overcoming Warpage to Solder the SOC Package to the PCB

Key Challenge: Managing Package Warpage to Enable Fine Pitch BGA Surface Mount

Difficulties Compounded By Finer Ball Pitches With Less BGA Collapse

Higher Pitch Bigger Solder Ball More Collapse

Shorter Pitch Smaller Solder Ball Less Collapse

Reduced Allowable Warpage

1.0

0.9

0.3

mm

0.2

mm

0.4

mm

0.5

mm

0.6

mm

0.8

0.7

0.6

0.5

No

rma

lize

d A

llo

wa

ble

P

ack

ag

e W

arp

ag

e W

ind

ow

fo

r S

ucc

ess

ful

SM

T

Second Level BGA Pitch

0.5mm

0.4mm

0.3mm

0.2mm

0.1mm

Typical Fine Pitch BGA Mobile Products

2012 2015 2018+

Se

con

d L

ev

el B

GA

Pit

ch


FLI Scaling Flip Chip Interconnect Scaling Industry Challenges

Technology FLI Pitch Technical Challenges

Mass Reflow >100um • X/Y Placement Accuracy • Solder Collapse vs Warpage Control • Managing Post Reflow Mechanical Stress on Package or on PCB

Thermo-compression Bonding

>10um • X/Y & Z Placement Accuracy • Precision Temperature Control • Process Cost

Embedded Die >10um • Materials Mismatch in Planar Structure • Yield • TPT

Cu to Cu >1um • X/Y Alignment • Planarity • Bond Time


FLI Scaling Flip Chip Interconnect Scaling Industry Challenges

Technology FLI Pitch Application Technical Challenges

Capillary Underfill >100um Large die FCBGA

• Flow voids • Large die / Narrow stand off • Material and process optimization

Mold Underfill • Transfer mold • Compression mold

>100um Low cost Strip Assembly

• Thin mold cap / die exposed mold • Flow voids • Mold design • Material and process optimization

Pre-apply Underfill • Paste / Film format

>40um 3D Memory Integration

• Implement with Thermo-compression bonding • Filler entrapment / Reliability • TPT

Wafer level Underfill Still in research




Industry Challenges

First level & second level Interconnect Pitch Scaling

2.5D & 3D Packaging



Closing Remarks



Driver 2

Increasing bandwidth density within the package drives innovation including logic and memory interconnects with 2.5D and 3D integration

2.5D Silicon Interposer with TSV

Source: Intel Technology Journal 2007 Tera-scale computing

3D TSV stack for

High-end

for Mobile

Industry Challenge:

Meet Product performance targets with affordable costs


Demanding Increasing CPU to Memory Bandwidth

CAPACITY (MB)

PE

RF

OR

MA

NC

E (B

W -

GB

/s) SRAM

10MB 100 MB 1 GB 10 GB 100 GB

NAND

10 GB/s

100 GB/s

50GB/s

500GB/s

1000 GB/s

Capacity

TPT Increasing BW Flat Capacity

Increasing Capacity Increasing BW

Graphics/ Gaming

Mobile Client

Smart Phones

Performance Tablets

Cloud Servers

SuperComputing

LPDDR4

LPDDR3

HMC

GDDR5

WIO2

HBM

Compute density becoming key in Phones/Tablets/ IDC servers/ Supercomputing


SOC Memory Bandwidth Requirements A Key Element of Device Performance

New Packaging Architectures Are Required To Take Full Advantage Of

Increasing Memory Bandwidth In Handheld Devices

Memory Technology Continues to Evolve to

Support SOC Requirements

Apple Memory Bandwidth Increasing with

Generation to Improve Performance Source: Samsung Source: http://www.anandtech.com/

‘07 ‘09 ‘11 ‘12


Mobile and High Performance Wide IO Applications

Source: JEDEC Server Memory Forum 2011

High Band-width : data transfer between chips

High Density : Transistor & Interconnect

Low-Power: smaller/no buffer, slow & wide interconnect

Small Form-factor

3D Stacked

Package

Drivers


2.5 D interposer Solutions Bandwidth Requirements Create New Challenges

28

2.5D Interposer

•WI/O 2: 40um pitch

•HBM : 55um pitch

•L/S : 2um

2.5D

Si Interposer

2.5D Glass Interposer

2.3 D

Adv Org Interposer

2.3 D Adv Org Pkg

Source: Amkor

Source: JEDEC

Industry Cost Target

1.0 cent /mm2 >

Source: Qualcomm


2.5D Interposer Industry Challenges

Technology Design Rule (L/S & Via

Diameter)

Technical Challenges

Si interposer L/S 2um > via 10um >

• Cost for large interposer

• Power delivery through TSV

Glass interposer

L/S 10um via 30um

• Under development • Looser design rule ? • Low cost via drilling/ filling

Organic

Interposer L/S 2um – 5 um

via 10 um-18 um • Under development

• Low cost process and materials ( Dry vs. Wet process fungibility) • Looser design rule / increased layers • Low CTE core and co-planarity • micro via reliability

Organic Interposer

Source: SEMCO 2012 MEPTEC

Si interposer 30um via / 90um pitch

Glass interposer

Source: ITRI


Mobile Wide I/O DRAM 3D Assembly Challenges

• Chip Attach

• Chip placement accuracy and Low-force capability

• Material Dispense Integration

• Equipment Throughput

• Significant Opportunities Driven by 3D Stack Packaging

• Investment and innovations required

• Require turn key solution: Equipment, process & Material

• Need Direct Collaboration with Materials Suppliers




Industry Challenges


2.5D & 3D Packaging



Closing Remarks


Substrate Panel Level

FLI Bump Level

SLI Package Level

Technology Driver & Challenges Driver 3

Meeting the push for ultra-thin form factors will require advances in thin wafer handling, thin die assembly, thin substrate manufacturing, and package warpage controls

Material Handling During Manufacturing

Room Temperature Reflow Temperature


Thin Is In! Packaging Must Support Consumer’s Preference For Thinner, Sleeker Devices

Thin Packaging Generates A New Set Of Thermo-mechanical Challenges Compared To Traditional PC Components!

Memory SoC

Cross-section of iPhone 5

Package (SOC with Stacked Memory)

is a significant contributor

to overall phone thickness

Substrate


SOC Packaging Supporting Thinner and Smaller Devices

Standard Core

Thin Core

Coreless

Embedded

Key Challenge: Solving the Thermo-mechanical Issues That Arise As Packages Become Thinner And Interconnect Pitches Scale

1.5 mm

1.1 mm

0.7 mm

0.3 mm

Total Package Thickness

Std

. Co

re

Th

in C

ore

Co

rele

ss

Em

be

dd

ed


Smartphone Package Package-on-Package technology

Source: Intel 2012 ECTC

Interposer top surface remains flat through reflow, allowing the memory

package to properly attach

Coreless

Substrate

Interposer

The range of warpage on the interposer surface is very narrow


TMV base PoP has become the de-facto package at OSAT for application processers

Mold material (thermo-mechanical/ shrinkage) properties are the key to manage warpage

Industry Mobile Computing Package

Warpage profiles over the reflow profile

Through mold via shape

Through mold via base Flip Chip PoP

Wire-bond Pop

Source: Amkor 2008 ECTC


Solution Space for Warpage Control Warpage Solution Space consists of Geometry, Materials and Process

Key Challenge: Research Needs to Focus on New Materials which Provide Warpage Control to Enable Thinner Packaging

• Package Dimensions

• Die/substrate/mold thickness

• BGA Size and Depopulation Geometry

• Low Temperature Solder

• Low Tg Underfill

• Low CTE & High Modulus Substrate

• Improved Board Paste

Materials

• Molding ( High modules and shrinkage)

• Stencil Optimization

• Variable SRO Process




Industry Challenges


2.5D & 3D Packaging


IoT &Wearable Packaging

Closing Remarks


Smart Devices Platforms for Creators

Technology Driver & Challenges Driver 4

System densification in Wearable/IoT drives innovations in Wafer Level Packaging / Direct Chip Attach and Low Cost Flip Chip technology to enable further reduction in cost, size and power


Flip Chip on HDI PCB

Strong Smartphones, tablets demand drives the growth of the HDI / Type 4 PCB market

Future High End PCB’s will support pitches that enable Logic Direct Chip Attach

.5mm

.4mm

.3mm

.2mm

.1mm

Typical Fine Pitch BGA

Mobile Products

2009 2012 2015 2018+

Flip Chip Substrate to WLP Compatibility

APPLE iPhone 5 PCB

HDI PCB enable 0.4 mm pitch / 1326 balls CPU

Ten-Layer Construction •720μm thick •50μm L/S Source: Prismark •50μm diameter •23 – 25μm copper thickness •35 – 50μm dielectric thickness

50μm L/S

40μm L/S

25μm> L/S

30μm L/S

DCA


WLP to address future DCA needs

WLPによる機械的保Mechanical protection by WLP

Wafer

Dress lightly

WLP

DCA Mother

Board

Enables thinner system and lower package cost

Enables robust board assembly with advanced semiconductor generation

Die Edge coat

Die Back side coat

Die front side coat

Source: Intel 2012 ICEP

Solder bump

Si Chip


Low Cost Flip Chip Package

Industry has developed single-layer or two layer low cost substrate technologies that simplify the substrate fabrication

process as a way to provide a cost-effective advantage compared with existing solutions

Cross section of an embedded

trace 2 layer Flip Chip Package

Source : SPIL

1 Layer RDL single chip

Fan out WLP

Source : Infineon

WLP/DCA Test Chip

5.7 x 5.7 mm

200um ball pitch

620 balls




Industry Challenges

First level / second level Interconnect Pitch Scaling

2.5D / 3D Packaging



Closing Remarks


Closing Remarks • Growing portfolio of packaging solutions driven by new device use

models and need for higher performance & form factor

• Significant Opportunities Driven by Next Generation Packaging

• Need increased level of investment & collaboration across the supply chain on developing total assembly solutions to overcome challenges associated with Pitch Scaling, 2.5D/3D integration, ultra-thin and Low Cost Packaging


Collaborative Development Example - Virtual Pathfinding Line with Partners -

- Intel Lab: Quick turn analysis and feedbacks -

- External Labs: Virtual Full Process Capability -

A B C D E

• Able to run some early units for the early leanings

• Development work before the system is available

Intel Tsukuba Technology Center

Process

Module B

Process

Module A

Process

Module C A B

C

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