L U I S J E R O M E J . S E V I L L A N O

OBJECTIVETo use my skills, experience and adaptability to obtain a supplier quality engineering or slider targeting process engineering position where I am constantly challenged. My greatest strength is my ability to walk into a new environment and be functional immediately. I am quick to learn and adapt to new situations, systems, processes and technologies.

PROFESSIONAL EXPERIENCEHGST Phils Corporation, Laguna Technopark SEPZ, Biñan, Laguna

Technology Specialist I (September 2014 to present)Design of Experiment (DOE) Manages the forecasting, planning and logistics for DOE teams – planning, executions, test

plan (slider test, Guzik test) and input.

Laguna Daiichi Inc., Laguna Technopark SEPZ, Biñan, LagunaQA MANEGER (July 7, 2014 to September 2014) Oversee the overall of Quality department – plastic injection molding, connector insert,

assembly and shipment. Introduces new quality assurance and control techniques. Ensures application of SPC technique is performed accordingly.

TDK Philippines Corporation, Laguna Technopark SEPZ, Biñan, Laguna

PRINCIPAL ENGINEER 1 - Slider Engineering (May 2013 to June 2014) (lateral transfer) Oversee the overall activities of Slider Lapping Targeting team. Targeting team is

responsible for establishing the desired lapping parameter values for optimum MWW & reader requirements after lapping.

Determines methods for lapping operation which would translate to optimum level of magnetic writer width (MWW) value – wafer writer parameter.

Evaluates new wafer writer or reader parameters dimensional change, for any significance to MWW and reader performance from lapping to DP. Strongly collaborated with Product and Process Engineering teams.

Ensures that targeting activities are well administered, correct formula and approaches are used accordingly.

Provides techniques, new methodologies and approaches in executing the targeting. Performs data analysis on sensitivity values for engineers’ reference and baseline. Coach and conducts trainings for engineers and technicians.

Accomplishment/s:

Level of magnetic writer width (MWW) sigma gradually improved, from 5nm to 3nm level (target: 2.5nm).

Fluctuation of MWW mean was reduced (30% ave. to 10% ave per day), after the application of multi-step technique.

PRINCIPAL ENGINEER 1 – CQE (WD) (November 2011 to April 2013) Communicates to customer on all items that the customer requested and requirements,

specially on wafer performance from slider fab to HGA. Collaborates with Product and Process Engineering (slider fab and HGA) for wafer quality

issues informed by customer – be it at HGA level or HDD performance level. Oversee the overall activities of CQE (Customer Quality Engineering). Trains CQE personnel on methodologies and techniques. Establishes targets and objectives for the IQC/SQE group.

Accomplishment/s: Customer satisfactory rating (quality perspective) went up, from 86% to 92% and

continuously improving. Established the Global 8-Discipline (G8D) system, to align with customer’s existing system.

MANAGER (July 2007 to October 2011) Oversee the overall activities of IQC-SQE section – material evaluation, incoming

inspection, and material quality issues resolution. Resolves argued material related problem raised by internal customers. Ensures that suppliers are following the company standards and criteria. Ensures that suppliers provide corrective and preventive actions on material problems and

concerns. Trains IQC/Supplier Quality Engineer/s personnel on methodologies, techniques and SPC

relating to supplier quality management activities and incoming quality control. Establishes targets and objectives for the IQC/SQE group. Interacts with related groups (internal) for the speedy resolution of material related

problems. Trains SQE Engineer and IQC inspectors. Ensures that suppliers are following the company standards and criteria. Ensures that suppliers provide corrective and preventive actions on material problems and

concerns.

SENIOR SUPPLIER QUALITY ENGINEER (Feb 2003 to Sept 2009) Handled wafer material and establishes incoming inspection criteria (visual) and inspection

methods for quality control. Collaborates well with wafer supplier/s for quality issues and performance results of wafer

design change/parameter optimizations made at wafer fab side. Performs evaluation and verification of wafer quality issues --- from slider fab to HGA

manufacturing, in coordination with Product and Process Engineering teams. Ensures that suppliers provide corrective and preventive actions on material problems and

concerns. Requirement: within 24-HR period, containment action and action plans are provided.

Accomplishment/s: Established visual inspection criteria for wafer material. Established a system for wafer quality issues verification and evaluation.

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QA ENGINEER 3 (HGA/Slider Fab) (March 1999 to Jan 2003) Performs quality issue investigation/failure analysis and validation. Parameters includes,

solder ball bonding (JSBB & SBB), flying height (FH), dynamic performance (DP), rho-H and material analysis (SEM, AFM, TOFSIMS).

Conducts wafer performance verification when there are new wafer design or optimization features informed by wafer fab team. Such as, MWW/OW improvements on writer dimensional change or reader material change.

Conducts first article evaluation, new process/tooling/equipment qualification and material in collaboration with Product and Process Engineering team.

Support engineering team for the yield improvement and line sustenance. Conducts line training and specs review for fellow engineers and inspectors.

Accomplishment/s: Spearheaded a void defect reliability risk assessment, which resulted to ~0.5% yield impact. A member of a core group that resolved the high chemical consumption rate, which resulted

to ~10% reduction. Trained inspectors values by which, they became more responsible to what they – and not

mandated by numerical quotas. Created the zero-defect program within HGA-QA group, which resulted to high lot

acceptance rate (>98%). Improved inspectors’ turn-around time on lot inspection, by 5%.

Veteran’s Electronics and Communication, Inc. (Vetronix), Fort Bonifacio, Makati City. April 1994 to September 1998

SECTION HEAD (QE and IQC) (Feb 1995 to Sept 1998) Settles conflicts on marginal criteria through proper coordination with Production and

Engineering group, maintaining correlation units/standards, initiating correlation exercises and analyzing the result thereafter.

Initiates vendor corrective action request issuance, for material related problems – detected at line or at incoming inspection.

Performs after sales service on supplied radios. Oversees the overall activities of QA line engineering and incoming quality control.

Accomplishment/s: Conducted an on-site field radio-check and reliability tests assessment. Using HP Signal

Generator, Oscilloscope, Field Strength meter, frequency meter and other related radio test equipment that helped me carry out the activity outside plant. This is aimed to verify product quality and performance after shipment or delivery to customer.

Studied Product performance by subjecting to reliability tests (i.e. burn-in check, submerge check). The study was aimed to determine the optimal depth level and temperature range the product can withstand without damage.

QA TECHNICIAN (April 1994 to Jan 1995) Initiates fixtures creation, test/inspection procedures, limits samples which will be used by

inspectors in carrying out incoming inspection operation. Creates new techniques for better incoming inspection operations.

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Communicates to related groups (i.e. Warehouse, Production and Process Engineering) any quality issues relating to material aspect.

Ensures that all components passed company’s specs and standards.

Accomplishment/s: Set a system for timely equipment calibration that showed a 30% improvement. Conceptualized a jig that helped operators’ and inspectors’ inspection operation, which

eventually resulted to a 10% yield increase.

EDUCATION November 2012 to April 2015 -- Graduate program Technological University of the Philippines (TUP), Manila Master in Technology (MT)

1988 to 1993 Saint Louis University (SLU), Baguio City, Philippines Bachelor of Science in Electrical Engineering (BSEE).

TRAININGS/SEMINARS Six Sigma (Greenbelt trained) Slider lapping targeting Crisis Management System Global 8D system Dimension Metrology with Tolerance & Fits Wafer fabrication training (in Headway Technologies, CA, USA) HDD basic principle and application Internal Auditing Skills & Effective Presentation Skills Seminar Advance Problem Solving Technique - Taguchi method, Basic & Advance SPC SPC (Basic, Probability & Interference, ANOVA) FMEA Training Advance ESD Training Behavioral Based Safety Training OHSAS 18001 Occupational Health & Safety Assessment Series ISO 9001:2000 Quality System ISO 14001 Environmental Management System

SKILLS Computer Literate, knowledgeable in MS Windows / NT, MS Office and its applications.

Knowledgeable on the use of the internet. Knowledgeable in FMEA, DOE & G8D process system, ISO9002, ISO14001, OHSAS18001

system, advance problem solving by Taguchi/ANOVA method. Skilled in the operation of machines and equipment for testing of electronic components (i.e.

oscilloscope, signal generator, spectrum analyzer, audio generator, calibrator, multi-meter, frequency meter & electronic component curve tracer, LCR meter, etc.)

OTHER INFORMATION ABOUT ME

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I am presently residing at U201 MC23 BCDA PH2, Diego Silang Village, Taguig City, Philippines. Born on September 29, 1971 in Manila. 42 years of age, a Filipino citizen, a Roman Catholic by religion, and a married man. I stand 1.7334 meters and weigh about 65 kilograms.

Tel no. 63-2-836-88-42 Mobile: 63-918-901-1221 ; 63-905-252-1456

E-mail: luis.sevillano@yahoo.com; luis44.sevillano@gmail.com

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