isis next generation router

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ISIS Next Generation Router. Shahzad Ali Xia Chen Brendan Howell Yu Zhong. Motivation. Anybody can make a router. Key is to make one with High speed (OC-48 and up) High port densities Better performance (throughput, delay, latency) Cheap etc. But we always forget some requirements. - PowerPoint PPT Presentation

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No Slide TitleKey is to make one with
High speed (OC-48 and up)
High port densities
Cheap
etc.
Guaranteed bandwidth/latency (QoS)
Broadband Networks, 2000
Aggregation point for large data centers
Backbone router at a major peering point
Backbone router for carrier facilities
Core router for IP transit providers
High bandwidth
Design a router that meets the minimum specifications
Maximize switch throughput
Provide support for strong QoS in the switch with realistic assumptions
Build an extensible simulator
Make the design realistic!
Result: ISIS
Buffers
Provides perfect QoS.
Can order outgoing cells according to their priorities using FQ (WFQ, WF2Q+, etc)
Use fast sorting techniques to speedup the process*.
But, requires a speedup of N for switching fabric
Not scaleable for high bandwidth switches.
Not cheap either.
*“A simple and Fast Hardware Implementation Architecture for WFQ Algorithms”,
Nen-Fu Huang and Chi-An Su
Broadband Networks, 2000
Difficult to maximize switch throughput while providing these guarantees.
But, simple to implement, with minimal speedup and maximum throughput.
Make scheduling decisions using a smart scheduling algorithm.
Use iSlip or similar algorithms to achieve high throughput
Switching Fabric
Too Expensive
Input Queuing
Maybe a third option?
QoS with Input Queuing
The only way we can imagine this happening is with buffered crossbars
The buffers are provided at each cross-point
Number of buffers are bounded (between 3-5 cells)
Use FQ servers at Input, crossbar buffers and output to achieve QoS
The solution is hard to implement
Plus it only provides probabilistic guarantees
Plus we don’t even know if it actually works
Broadband Networks, 2000
“Implementing Distributed Packet fair Queuing in a Scalable Switch Architecture”, D. C. Stephens
“A Distributed Scheduling Architecture for Scalable Packet Switches”, F. M. Chiussi and A. Francini
Is that the best we can do?
Broadband Networks, 2000
CIOQ
Combined Input output queuing: combines the benefits of both Input and Output queuing.
Input queuing is speedup of 1
Output queuing is speedup of N.
CIOQ is between 1 and N, need to buffer at input and output.
Requires a speedup of only 2 to simulate an output queuing switch completely.
Reasonable given the difficulty of our initial goal.
Guarantees the exact same output as a OQ switch.
Broadband Networks, 2000
CIOQ
Assigns a value called slackness to each VOQ at the input.
Slackness is the urgency of a packet. Slackness of 0 means high urgency.
Inputs and outputs select ports based on a priority calculated by the FQ discipline used.
For FCFS, high priority for packet that came earlier.
Uses Gale-Shapely algorithm to do a stable matching of inputs to outputs after they have been selected in Phase I.
No analysis has been done on the throughput of a CIOQ switch, just an analytical bound on its proximity to OQ switch.
Broadband Networks, 2000
“Delay-Bound Guarantee in CIOQ Switches”, H. Chao, L. Shen Chen
“Matching Output Queuing with CIOQ Switch”, S. Chaung, A. Goel, N. McKeown, B. Prabhakar.
“College Admissions and the stability of marriage”, D. Gale, L. Shapely.
Broadband Networks, 2000
ngrSim follows a modular design approach.
All components are coded as modules that can be plugged in place of others.
Allows for easy mix-and-match of various schemes.
It is event driven … completely.
Everything is driven by the event queue.
Broadband Networks, 2000
An abstract class handler is defined.
A class event is described which consists of an object of type handler.
The handler is supposed to be the component that is responsible for the event.
When the event is run, the handle function of the handler is called.
Event are enqueued into an event queue.
class handler {
void set_next_handler(handler * h)
Efficient event handling capability.
Events are queued in a structure called a Skip-list, developed by William Pugh at University of Maryland*.
A probabilistic list which allows for O(1) inserts, deletes and searches.
Simulation time is kept track of in the event queue.
The event at the head of the event queue is run (handle function called) and the simulation time is updated.
*http://www.cs.umd.edu/~pugh
((crossbar*)fab)->start();
((tgen*)tg)->start();
// print Stats
Initialize the switch and declare various components. ALL READ FROM A CONFIGURATION FILE
Start the periodic fabric pull and the traffic generation events.
Main Loop
Get the event of the head of the queue. This updates the system time as well
Call the handle function.
Check if simulation ended
Broadband Networks, 2000
Design of ngrSim
The design follows exactly from the design we had in the earlier design review.
Broadband Networks, 2000
(Variable Length)
OPP
Use FQ here as well
simpleOPP
cioqOPP
Description of the components
Packets are generated in TGEN module and are passed as events to IPP, Framer and Scheduler.
Framer breaks packets into cells.
Cells are 64 bytes with 6 bytes of header.
2 input + output port number = 4 bytes
1 byte for cell ID
1 byte for flag + priority
Scheduler is an abstract class. All schedulers that are implemented derive from this base class.
We have FCFS, iSlip and CIOQ implemented.
The scheduler does not pass the packets on to the fabric. The fabric is running at a fixed time slot which is determined by the cell size and line speed.
Broadband Networks, 2000
Description of the components
The fabric pulls cells from the scheduler at these regular intervals.
Fabric is also an abstract class. All fabrics will derive form this class.
We currently have a crossbar fabric implemented.
The fabric sends the cells to the reframer.
Reframer reassemble cells into packets.
If some cell is not received in a certain time limit, the partial packet is discarded.
The reframer passes the reassembled packets to the OPP.
The OPP queues the packets and sends them out at the link rate.
We have simpleOPP and cioqOPP implemented.
Broadband Networks, 2000
We keep track of
cell and packet count
We ran experiments for 100 million clock ticks.
Each data point is a result of 10 runs of the same experiment with different random seeds.
The values were only collected after steady-state.
Due to time-constraint, we could only run for 16 ports.
Broadband Networks, 2000
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0.0000155391
7.93164
7.93131
0.999958
6094.71
0.9
0.0000827305
8.93191
8.93127
0.999929
10523.3
1
0.00199422
9.9235
9.90506
0.998142
230319
cioq-overall
0.1
0.0000835003
0.97945
0.978677
0.999211
23988.8
0.2
-0.000061459
1.99164
1.99135
0.999858
14282.5
0.3
0
3.01255
3.0124
0.999948
11549
0.4
-0.0000933649
3.95003
3.95061
1.00015
10494.7
0.45
-0.0000274811
4.45827
4.45849
1.00005
10235.7
0.5
-0.0000082895
4.94322
4.94325
1.00001
10267
0.55
-0.000037788
5.43482
5.43504
1.00004
10325
0.6
0
5.97275
5.9729
1.00003
10622.2
0.7
0.0000177253
6.93154
6.93123
0.999956
11563.4
0.8
0.0000670048
7.94624
7.94555
0.999913
13616.5
0.9
0.0000275184
8.92928
8.92907
0.999977
19795.2
1
0.0047988
9.92348
9.86024
0.993627
120982
Sheet1
islip-overall
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Sheet3
To make ISIS a reality …
Physical Specifications of base design
Chassis Height: 10 in. Includes power module shelf (AC or DC)
Chassis Width: 17.25 in. not including rack mount flanges. can be rack mounted in 19 or 22 in.
Chassis Depth: 18 in. not including cable management system
Chassis Weight: approximately 50 lbs. depending on configuration
Standards compliance
Safety: UL1950,IEC60950,IEC60825,TS001,AS/NZS 3260
Electromagnetic Emissions: FCC Class A, ICES-003 Class A, EN55022 Class B, VCCI Class B, AS/NZS 3548 Class B
NEBS: SR-3580 Level 3 Compliant
Broadband Networks, 2000
Modular Design separates Line card module from Switch fabric module.
Redundant Power supplies and fabrics can be used to ensure robustness.
Compact design allows flexibility in rack placement.
The modules are connected through proprietary fiber interconnect using LCS protocol*.
*http://www.pmcsierra.com/products/details/pm9311/
That’s cute … but show me something big!
The PMC9113 has 10 Gb/s channels that can be used to connect to other switching modules or line cards through fiber and LCS protocol.
So instead of using one 320 Gb/s switch, we can use more than one.
We can extend the capacity of the switch by connecting many switch modules in a structure.
The easiest structure we can think of is a mesh.
Other possibilities include a hyper-cube.
Broadband Networks, 2000
Switching module with 320 Gb/s capacity
16 such switches connected in a mesh through 10 Gb/s channels of fiber.
10 Gp/s channel
Full mesh of 16 equals 1024 OC-48 ports (2.5 Tb/s)
Line card Module
Broadband Networks, 2000
Based on source and destination address, line cards route to
ports on the card itself (through the line card)
Other line cards on same module (through the fabric)
Other switching modules (through the interconnect)
Routing between switching modules based on modified hot-potato routing with queue lengths
Queues only monitor bandwidth utilization of channels between modules.
Built into the chip-set.
Send to the recipient directly if queue is not loaded.
Send to the least loaded queue recipient, otherwise.
Broadband Networks, 2000
Only more intelligent
Controls delays
For QoS,
Some bandwidth is reserved for guaranteed traffic (max 10 Gb/s between two modules)
If such traffic arrives, send directly to the recipient (one link) using this reserved bandwidth.
If no such traffic, then use the bandwidth for normal traffic.
Requires modification to the scheduler (which is programmable)
Addressing has to be universal.
Routing between modules has to be added.
Broadband Networks, 2000
Plan to follow-up on the scalability options.
Get statistical significance for the results.
Long-term
FIFO Drop Rate with different Speedups
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0
0.1
0.2
0.3
0.4
0.5
0.6
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00.20.40.60.811.2
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0
100000
200000
300000
400000
500000
600000
700000
800000
900000
00.20.40.60.811.2
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0
0.2
0.4
0.6
0.8
1
1.2
00.20.40.60.81
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-100000
0
100000
200000
300000
400000
500000
600000
700000
800000
00.20.40.60.81
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-200000
0
200000
400000
600000
800000
1000000
1200000
1400000
00.20.40.60.811.2
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buffer1000
buffer5000
-500000
0
500000
1000000
1500000
2000000
2500000
3000000
00.20.40.60.81
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