I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 1 Lecture 17 I/O Interfaces and I/O Busses

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<ul><li>Slide 1</li></ul> <p>I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 1 Lecture 17 I/O Interfaces and I/O Busses Slide 2 I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 2 Storage System Issues Historical Context of Storage I/O Storage I/O Performance Measures Secondary and Tertiary Storage Devices Processor Interface Issues I/O Buses Redundant Arrays of Inexpensive Disks (RAID) Slide 3 I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 3 Disk Time Example Disk Parameters: Transfer size is 8K bytes Advertised average seek is 12 ms Disk spins at 7200 RPM Transfer rate is 4 MB/sec Controller overhead is 2 ms Assume that disk is idle so no queuing delay What is Average Disk Access Time for a Sector? Ave seek + ave rot delay + transfer time + controller overhead 12 ms + 0.5/(7200 RPM/60) + 8 KB/4 MB/s + 2 ms 12 + 4.15 + 2 + 2 = 20 ms Advertised seek time assumes no locality: typically 1/4 to 1/3 advertised seek time Average Disk Access Time for a Sector: 20 ms =&gt; 12 ms Slide 4 I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 4 Processor Interface Issues Interconnections Busses Processor interface Interrupts Memory mapped I/O I/O Control Structures Polling Interrupts DMA I/O Controllers I/O Processors Capacity, Access Time, Bandwidth Slide 5 I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 5 I/O Interface Seperate I/O instructions (in,out) Lines distinguish between I/O and memory transfers VME bus Multibus-II Nubus 40 Mbytes/sec optimistically 10 MIPS processor completely saturates the bus! CPU Interface Peripheral Memory memory bus Independent I/O Bus Common Memory &amp; I/O bus CPU Interface Peripheral Memory Slide 6 I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 6 Memory Mapped I/O Single Memory &amp; I/O Bus No Separate I/O Instructions CPU Interface Peripheral Memory L2 $ Memory Bus MemoryBus Adapter I/O bus $ CPU ROM RAM I/O Slide 7 I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 7 Programmed I/O (Polling) CPU IOC device Memory not an efficient way to use the CPU, unless the device is very fast! but checks for I/O completion can be dispersed among computationally intensive code busy on wait loop Is data ready? read data store data yes no done? no yes Slide 8 I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 8 Interrupt Driven Data Transfer (2) save PC (3) interrupt service addr (4) 1000 transfers/second: 1000 interrupts @ 2 sec per interrupt=&gt; 2 msec 1000 interrupt service @ 98 sec each=&gt; 98 msec 100 msec = 0.1 CPU seconds CPU IOC device Memory User program halts only during actual transfer memory user program interrupt service routine read store... rti add sub and or nop (1) I/O interrupt Slide 9 I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 9 Direct Memory Access 0 ROM RAM Peripherals DMAC n Memory Mapped I/O Time to do 1000 xfers in 1 msec: 1 DMA set-up sequence: @ 50 sec 1 interrupt: @ 2 sec 1 interrupt service sequence: @ 48 sec 100 sec.0001 second of CPU time CPU sends a starting address, direction(R/W), and word count to DMAC. Then issues "start". DMAC provides; Peripheral controller Handshake signals Memory Addresses Handshake signals CPU IOC device Memory DMAC I/O Slide 10 I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 10 Input/Output Processors (2) (3) Device to/from memory transfers are controlled by the IOP directly. IOP steals memory cycles from CPU OP Device Address target device where cmnds are looks in memory for commands CPU IOP Mem D1 D2 Dn... main memory bus I/O bus OP Addr Cnt Other what to do where to put data how much special requests Command memory CPU IOP (1) issues instruction to IOP interrupts when done (4) Slide 11 I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 11 Relationship to Processor Architecture I/O instructions and busses have largely disappeared Interrupt vectors have been replaced by jump tables PC I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 13 Interconnect Trends &gt;1000 m10 - 100 m 1 mDistance 10 - 100 Mb/s40 - 1000 Mb/s 320 - 1000+ Mb/s Bandwidth high (&gt;ms)medium low ( I/O InterfaceCS510 Computer ArchitecturesLecture 17 - 31 I/O Data Flow I/O DeviceHead/Disk Assembly DMA over Peripheral Bus OS Buf fers (&gt;10 MByte) Xfer over Serial Interface Track Buffers (32K - 256KBytes) Embedded Controller Memory-to-Memory Copy ApplicationAddress Space Host Processor Xfer over Disk Channel HBA Buffers (1 M - 4 MBytes)I/O Controller Impediment to high performance: multiple copies, complex hierarchy </p>

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