Introduction toIntegrated Systems Design Automation

Outline

• Why Do You Care?

• Technology Trends

• Process and Device Technology

• Logic Technology

• Memory Technology

• Packaging Technology

• Effect on Processor Design

Hank Walker

http://courses.cs.tamu.edu/cpsc661/walker

Why Do You Care About Technology?

IC design is often technology driven• try building a 1 GHz, low-power uP with vacuum tubes• designers say what they need• but technologists tell them what they get

Competitive designs must balance utility and cost• use available technology to balance:

- speed- standards- weight- form factor- power consumption - now the most critical issue- reliability- cost

You usually have to shove 10 lb. into a 5 lb. bag

Good Technology Trends

More Transistors at Lower Cost• bigger chips - at introduction

• smaller geometries

• ~250M transistors common in 2005

Higher Speed• faster transistors

• shorter distances

Smaller Size and Weight• higher packing densities

• packaging advances

Merger of IC and Packaging Technology• chip is the package

Bad Technology TrendsAbstractions Break Down

• must “listen to the silicon” to achieve optimal designs

• concurrent circuit-layout-device design

• concurrent electrical-packaging design

• technology-dependent architectural, RTL, logic design

=> except when design is simple and slow and boring

Law of Large Numbers Stops Working• number of atoms now matters

• transistors don’t shut off - lots of wasted leakage power

• you've got to remember your quantum mechanics

Diverging Requirements• desktop - high speed, low cost, power limits

• portable - low power, low weight, small size, low voltage, low cost

• embedded - low cost, harsh environment, high reliability

Process Technology

Geometries• lateral: ~65 nm today, ~4 nm demonstrated

• vertical: ~15 nm today, ~ 3 atoms demonstrated

• shrinking ~15%/year

• limited by deposition, etch, implant, lithography equipment

• limited by $$$ - new fab cost $3B+

Die Size (big chips)• ~2 cm2 at introduction, ~1 cm2 in volume

• growing ~20%/year

• limited by yield

=> ~2x transistors/chip every 1.5 years

System on a Chip (SoC)

2005

Bladeserver

Volume

Intro

Process TechnologyInterconnect

• TiN, poly, 8-9 layers of copper

• more metal layers in future

• minimum resistance

- copper is it, silver no good

• lower capacitance

- low-K dielectrics

• on-chip transmission lines

- controlled impedance

- crosstalk elimination

• optical waveguides?

• superconductors don’t help much - still LC

Interconnect delays not scaling with technology

Device TechnologyCurrent

• CMOS

- strained Si channel

- elevated source/drain soon

• BiCMOS - CMOS + NPN, maybe PNP

• thin-film MOS transistors

- replace resistors as SRAM pullups

- LCD displays

• GaAs MESFETs

- RF, high temperature applications

• SiGE BJTs, MOSFETs

- RF

Future• 3D devices - FinFET, trigate

fieldoxide

metal

fieldoxide

metal

Systems are Getting Faster

• Must scale VTH and VDD to increase speed– Causes more

leakage

– P4 leaks ~20A, ~1/3 of its power!

Motorola BiCMOS Technology

• 100 ps ECL gate delay

• 0.5 µm channel length

• 3 layer metal

• silicides

• dual well

Still used in RF, high power circuits

Process and Device IssuesBJT, MOSFET R.I.P.?

• fundamental limits reached in ~10 years- but it has always been ~10 years away

• delay some by going vertical

Supply voltage -> 0V• limit electric fields• reduce hot carriers

Increased variability• number of atoms in a region is now countable

Technology CAD• process and device simulation• a key limit to progress

Growing fabrication line cost• $3B+ for new Intel fabs

Logic Technology

Bipolar/BiCMOS– Still used for analog circuits– Fewer circuit compromises– Does not scale well– Still excellent for high power, high voltage

CMOS– Used for all logic– Used for most analog due to lower cost– Now increasing RF usage

» TI one-chip cell phoneZ

Z

Logic Technology

Design Styles• standard cells - library of functions

• sea of gates - big bag of gates, routing on top

• full custom - very high volume only

• mixed custom/semi-custom – on all large chips

• mixed analog/digital - common in consumer products

Trends• time-to-market dominates over manufacturing cost

- product life of 1-2 years

• increasing percentage of designs are ASIC/FPGA

- maybe volume too

• semicustom logic surrounding standard core

- e.g µP with custom I/O interfaces

- Xilinx Virtex II Pro – PowerPC on FPGA

MemoryDensity

– 2x every 1.5 years

Cost– Declines 30%/year – most important metric

SRAM– Usually mixed with logic on same chip

EEPROM (flash)– Lower programming voltages for integration with logic

– Scaling problems

ROM– Declining importance

– Time to market, field programmability

Memory

I/O• asynchronous => synchronous

• memory-interface bus => memory-CPU bus

- DDR, RAMBUS

Increasing Specialization• VRAM

• cache RAM

• mixed DRAM/SRAM

• synchronous DRAM

Memory Issues

Density Limits• traditional DRAM beyond ~Gb unlikely

• electric fields

• radiation

• delayed some with deep trenches, new dielectrics

• already close to area of two wires crossing

• MRAM – SRAM w/magnet

DRAM speed lagging logic- Must amplify small charge

- More bits => longer I/O path

- Higher speed => higher cost, lower density

Memory vs. Logic Speed

Packaging

Power• distribute power with low IR drop

• constant power, lower supply voltage => higher current

• large numbers of pins to supply current – 1000s of pins

Signal Delay and Integrity• controlled impedance to control delays

• shielding to reduce cross-talk

=> transmission lines

I/Os• Rent's Rule: I/O count ~

• 64-bit addr, 64-bit data, instr and data caches => 256 pins

• TAB or flip-chip on glass for flat panel displays

N0.6

PackagingCooling

• fin tower and low-speed fan near its limit

- ~130W for P4, check heat sinks on Apple desktop

• higher fan speed too noisy for office environment

=> air impingement – manifolds in current PCs

=> heat pipe to larger heat sink – some laptops

• chilled air - requires A/C in cabinet

• liquid impingement - plumbing, big package

=> liquid microchannels - small, low flow, 800-1000W/cm2!

• portables limited to conduction, some natural convection

LAPTOP TOO HOT FOR YOUR LAP!

Size, Weight• eliminate pins

• eliminate package - glop of epoxy covering chip

Packaging

Multi-Chip Modules (MCMs)• IC processing to pattern interconnect layers on substrate

• Put L3 cache close to processor

Pin Grid Arrays (PGAs)• fallen from favor - area, lead length

Leadless Chip Carriers (LCCs)• continues as mainline solution

• multiple rows to increase pinouts without area increase

Dual In-line Package (DIP)• only for small chips

ExoticaProcess and Device

• HEMT (high electron mobility transistor)

• high Tc superconductors - interconnect and devices

• quantum well devices (particle in a box)

Packaging• LN2 cooling

- 2x speed improvement with optimized process

- small geometry devices require it to work

- refrigeration is expensive, noisy, unreliable

- thermoelectric cooling might be solution

• wafer scale integration

- system on monolithic substrate

- Cost competition w/regular ICs

May see specialized use over next 10 years

Effect on Architectural Design

Problems• isochronic regions shrinking rapidly

- speed < c, it's the law

• takes multiple clock cycles to go across chip

• global knowledge is expensive, or stale

• memory speeds not keeping up with logic speeds

- A return to the bad old days of core?

- Do memory fetch, then go get a cup of coffee

• portable systems - maybe no power or disk

Solutions• small memories close to logic – cache hierarchy

• loosely coupled components – multiple cores on a chip

• yesterday's supercomputer problems in today’s desktops

• (flash) EEPROM for nonvolatile programmability w/o battery or disk

Effect on Logic Design

Problems• delays across packages and boards

• limited I/O count

• power dissipation balance

• clocking

Solutions• simultaneous partitioning across package levels

• more knowledge of circuit-layout-package

• iterate if necessary

- possible with automatic synthesis

• self-timed logic?

Effect on Circuit DesignMore device options

• bipolar, CMOS, thin-film devices• optimized for both logic and memory

Everything is sort of analog• I-V curves and logic transitions degrade• more current-mode operation

Device variability increases• simpler circuits• fewer matched timing chains=> must use physically-based statistical design=> self-timed logic?

More complex simulation• mixed circuit/device• interconnect parasitics=> use characterized cell library as much as possible

Effect on Layout Design

Global routing• critical to performance

• simultaneous place and route

Delay and Crosstalk Control• selective use of on-chip transmission lines

2.5D => 3D topology• complex design rules

• parasitic extraction

• tight loop back to circuit design

Effect on Package Design

Packaging as important to uPs as supercomputers• system cost

• system performance

• system weight

• system form factor

• environmental limitations

Can't throw design over wall to MechEs• concurrent package and electrical design

• constraints of packaging on electrical design

• electrical and thermal behavior of packaging on circuit

- within package as well as on MCM or board

=> ECEs must learn some ME

package dominates in portables

Bad Market Trends

• Competitive pressure– decreasing time to market

– decreasing market window

– falling system price

• Result– build more complex systems in less time with fewer people

– shove 10 lb into a 5 lb bag

Time

Timeto

Market

Time

SystemPrice

The Problem

• Electronic systems are most complex artifacts built– ~1B transistors in dual-core Itanium

– ~25M transistors in Power4 CPU core – now a “commodity”

• We’re only human– best humans can design 10s of transistors per day by hand

– 1000 person-years for original Pentium

– $100M design cost (~$200M in today’s dollars)

– 2-3 year design time => 300-500 designers - barely doable

– cannot keep on that trend

• Product failure == corporate death– IC fab cost $3B in 2003 (TI Richardson fab)

» $493k/day interest @ 6% interest rate

– chip-in-product sales >$20M/day

– delay == death

Conclusion

• Design automation is crucial for economic survival

• Design automation must:– improve our productivity faster than technology curve

– achieve greater optimality

– achieve higher-quality results

– handle additional physical effects

– and do it all on larger designs

• DA tools are primary limiting factor in IC design– a race between EDA and technology

– “solving yesterday’s problem tomorrow” - Mark Pinto

EDA Tools

Product-Level Design• synthesis across boards and chips

• multi-level optimization

• focus on meeting user-level specs

• humans mostly out of tool loop

Product engineers are primary tool users• other engineers act as consultants

• tool users and developers in same location

Design for Manufacturability/Profitability• CAD tools will know manufacturing process

• statistical design

• merger of design and manufacturing engineering

Two Visions of Computer Design*

1. Team of design experts aided by CAD tool gurus.- gurus fix tools when they break

2. Team of CAD tool gurus aided by design experts.- experts supply knowledge tools don't have

* Dave Ditzel, then at Sun

Homework

• Skim the Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS)

• http://public.itrs.net

• The industry consensus on technology needs to stay on technology trends

• Read chapters on design and test