introduction to chapter 12 digital information is easily stored commonly used memory devices and...

Introduction to Chapter 12 Digital information is easily stored Commonly used memory devices and systems

will be examined Flip flops Registers VLSI and LSI memory devices

The difference between main memory and auxiliary memory

Ronald Tocci/Neal Widmer/Gregory MossDigital Systems: Principles and Applications, 10e

Copyright ©2007 by Pearson Education, Inc.Columbus, OH 43235

All rights reserved..

12-1 Memory Terminology Memory cell Memory word Byte Capacity Density Address Read operation Write operation




12-1 Memory Terminology Access time Volatile memory Random access memory (RAM) Sequential access memory (SAM) Read write memory (RWM) Read only memory (ROM) Static memory devices Dynamic memory devices Main memory Auxiliary memory




12-2 General Memory Operation Every memory system requires I/O lines to

provide the following functions Select memory address being accessed for R or W

operation Select either a R or W operation Supply input data to be stored during a W Hold output data from memory during a R Enable or disable memory so that it will or will

not respond to read/write commandsRonald Tocci/Neal Widmer/Gregory MossDigital Systems: Principles and Applications, 10e



12-2 General Memory Operation Address inputs R/W input Memory enable




12-3 CPU Memory Connections Main memory is interfaced to the CPU through:

address bus data bus control bus

Write operation process: CPU places the memory location address on the address

bus CPU places data to be stored on the data bus CPU activates the control signal for the W operation




12-3 CPU Memory Connections Memory ICs determine location for memory storage by

decoding the binary address Data on the data bus is transferred to selected memory

location Read operation process:

CPU places address of memory location for data retrieval on the address bus

CPU activates the control signal lines for the R operation Memory ICs determine location of data being retrieved Memory IC places data from the memory location onto the

data bus




12-3 CPU Memory Connections System bus functions:

Address bus – unidirectional, carries address outputs from CPU to memory

Data bus – bi-directional, carries data between CPU and memory ICs

Control bus – carries controls signals (such as R/W) from CPU to memory




12-4 Read Only memories Holds data that does not change, or changes

only infrequently Nonvolatile Applications include: cash registers,

appliances, and security systems




12-4 Read Only memories Address inputs Data outputs Control input(s) The read operation



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12-5 ROM Architecture Four basic parts (Figure 12-7)

Register array – stores data programmed into the ROM Address decoders – determines which register will be

enabled by row and column Output buffers - pass data to the external data outputs




12-6 ROM Timing Typical timing for a ROM read operation:




12-7 Types of ROMs Mask programmed ROM (MROM)

Photographic “mask” establishes electrical interconnections

Economical only in high volume applications Programmable ROMs (PROMs)

Fusible links allow end users to program the device Can only be programmed once Economical for small volume applications




12-7 Types of ROMs Erasable programmable ROM (EPROM)

Can be erased and reprogrammed by user UV light is used to clear the device Entire device is cleared

Electrically erasable PROM (EEPROM) Voltage is used to clear memory Individual bytes can be erased

CD ROM Light is used to stores binary data Large quantities of data are economically stored




12-8 Flash Memory Allow rapid in-circuit reprogramming of individual

bytes The 28F256A CMOS flash memory IC

Control inputs determine what operation takes place Read command Setup erase/erase commands Erase verify command Setup program/program commands Program verify command




12-9 ROM Applications Embedded microcontroller program memory Data transfer and portability Bootstrap memory Data tables Data converter Function generator Auxiliary storage




12-10 Semiconductor RAM Random access memory – all memory

locations are equally accessible Used for temporary storage Fast read and write times are necessary RAM is volatile Many basic concepts that apply to ROM

apply to RAM as well




12-11 RAM Architecture Consider RAM as a number of registers, each

storing a single word and having a unique address

Read operation Write operation Chip select Common I/O pins




12-12 Static RAM (SRAM) Stores data as long as power is applied Available in bipolar, MOS and BiCMOS

variations Static RAM timing Read cycle Write cycle Actual SRAM chip – the MCM6264C




12-13 Dynamic RAM (DRAM) High capacity Low power requirement Moderate speed Small capacitors are used to store data Must be periodically refreshed Used for main internal memory in PCs or

MacsRonald Tocci/Neal Widmer/Gregory MossDigital Systems: Principles and Applications, 10e



12-14 Dynamic RAM Structure and Operation

An array of cells with unique row and column positions

Analysis of read and write operations using the simplified representation below:




12-14 Dynamic RAM Structure and Operation

Address multiplexing – each address pin can accommodate two different address bits

Operation of the TMS44100 4M X DRAM Address of memory by the CPU must be modified

for DRAM multiplexed addressing




12-15 DRAM Read/Write Cycles




12-16 DRAM Refreshing When a read operation is performed on a cell, all of

the cells in the row will be refreshed Refresh control logic is used to make sure that each

row is refreshed within the time limit Refresh modes

Burst Distributed

Most common method used is RAS only refresh The DRAM controller




12-17 DRAM Technology Memory modules:

SIMM DIMM SODIMM RIMM

FPM DRAM EDO DRAM




12-17 DRAM Technology SDRAM DDRSDRAM SLDRAM DRDRAM




12-18 Expanding Word Size and Capacity Expanding word size Combining RAMs

At right two 16X4 RAMs are combined for a 16X8 module




12-18 Expanding Word Size and Capacity Expanding capacity Combining RAMs

At right two 16X4 chips are combined for a 32X4 memory




12-18 Expanding Word Size and Capacity Incomplete address decoding – useful when different

memory devices are used in the same system Combining DRAM chips – DRAM ICs with word

sizes of 1-4 bits must be combined to form larger word size modules

Figure 12-40 illustrates combining eight TMS44100 DRAM chips to form a 4M X 8 module




12-19 Special Memory Functions Special functions performed by memory

devices in various applications Power down storage

Critical operating parameters that will be applied when a system is powered up

Industrial process control systems that must retain memory of where they are in a process under all conditions.


Copyright ©2004 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

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12-19 Special Memory Functions Cache memory

High speed memory that communicates directly with the CPU

Level 1 cache is on CPU Level 2 cache is SRAM external to CPU

First in first out (FIFO) memory Useful as a buffer between systems with different data

rates Circular buffers

Allow data to “wrap around” when the buffer is full




12-20 Troubleshooting RAM Systems Faults in RAM can cause unreliable system

performance or “crashes” In order to determine if RAM is working properly

you must know how it normally operates The decoding logic can be tested using signal

injection, or by forcing a certain address onto the bus to obtain a known decoder output



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12-20 Troubleshooting RAM Systems In order to test the complete RAM system, patterns

of 1s and 0s are written and read from each memory location

By alternating the patterns each bit can be checked for R/W of both 1s and 0s

Pattern checking does not catch all errors. There may be errors that occur only in certain patterns

A memory check is commonly run when a system is powered up




12-21 Testing ROM Test options include:

Printing out a listing of the memory contents Memory contents are compared to a reference

ROM Checksums may be used

A code based on the sum of the data words to be stored is checked against the actual value of the sum

This will not catch all errors, but if the checksums match, there is a high probability that the device is good




introduction to chapter 12 digital information is easily stored commonly used memory devices and...

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