intel ethernet controller x550 general ... intel® ethernet controller x550 datasheet—contents 6...

Revision 2.2July 2017

333369-004

Intel Ethernet Controller X550Datasheet

Ethernet Networking Division (ND)

PRODUCT FEATURES

General Serial Flash interface Configurable LED operation for software or customizing OEM

LED displays Device disable capability Package size - 25 mm x 25 mm (X550-BT2) Package size - 17 mm x 17 mm (X550-AT2)

Networking 10 GbE/1 GbE/100 Mb/s copper PHYs integrated on-chip Support for jumbo frames of up to 15.5 KB Flow control support: send/receive pause frames and receive

FIFO thresholds Statistics for management and RMON 802.1q VLAN support TCP segmentation offload: up to 256 KB IPv6 support for IP/TCP and IP/UDP receive checksum

offload Fragmented UDP checksum offload for packet reassembly Message Signaled Interrupts (MSI) Message Signaled Interrupts (MSI-X) Interrupt throttling control to limit maximum interrupt rate

and improve CPU usage Flow Director (16 x 8 and 32 x 4) 128 transmit queues Receive packet split header Receive header replication Dynamic interrupt moderation TCP timer interrupts Relaxed ordering Support for 64 virtual machines per port (64 VMs x 2

queues) Support for Data Center Bridging (DCB);(802.1Qaz,

802.1Qbb, 802.1p)

Host Interface PCIe 3.0 Base Specification Bus width x1, x4, x8 64-bit address support for systems using more than 4 GB of

physical memory

MAC FUNCTIONS Descriptor ring management hardware for transmit and

receive ACPI register set and power down functionality supporting

D0 and D3 states A mechanism for delaying/reducing transmit interrupts Software-controlled global reset bit (resets everything

except the configuration registers) Four Software-Definable Pins (SDP) per port Wake up IPv6 wake-up filters Configurable flexible filter (through NVM) LAN function disable capability Programmable memory transmit buffers (160 KB/port) Default configuration by NVM for all LEDs for pre-driver

functionality

Manageability SR-IOV support Eight VLAN L2 filters 16 Flex L3 port filters Four Flexible TCO filters Four L3 address filters (IPv4) Advanced pass through-compatible management packet

transmit/receive support SMBus interface to an external Manageability Controller (MC) NC-SI interface to an external MC Four L3 address filters (IPv6) Four L2 address filters

Intel Ethernet Controller X550 DatasheetRevision History

2 333369-004

Revision History

Revision Date Notes

2.2 July 21, 2017 Updates include the following: Added Section 2.2.8.1, Pin Differences in the X550-AT Single Port Device. Section 11.7.6.1.3 Added reference to list of support message types. Section 11.7.6.1.3 Modified verbiage in Value column for Bytes 3:5 in Table 11-44. Section 12.3.9 Added new table for X550-AT power consumption. Section 12.3.10.1 Updated values in associate table.

2.1 May 10, 2016 Updates include the following: Removed EEC.FLUPD bit. No longer used for triggering Shadow RAM dump. Removed FLUPDATE register (0x00015F54). Table 3-25 Updated description for SDP1. Section 9.2.3.6.7, Link Capabilities Register (0xAC; RO) Changed default value for

ASPM support (bits 11:10) to 10b. Section 11.8.3.1, Driver Info Host Command Updated Table 11-49. Table 12-3 and Table 12-4 Changed Device Total Power units from mW to W. Table 12-20 Updated thermal diode typical ESR value to 2.77 . Table 15-2 Updated ID Code values. Other miscellaneous updates.

2.0 January 8, 2016 Updates include the following: Updated PHY Registers section. Changed Max temperature in NVM mode to 102 (Tjunction max changed 107). Added NBASE-T information. Removed 10BASE-T information. Removed x2 lane width. Updated power numbers. Updated heat sink and other thermal information.

1.91

1. There were no previous versions of this document released.

October 27, 2015 Initial release (Intel public)

333369-004 3

ContentsIntel Ethernet Controller X550 Datasheet

Contents

1.0 Introduction ......................................................................................................... 191.1 Scope .................................................................................................................................. 191.2 Product Overview .................................................................................................................. 19

1.2.1 System Configurations ..................................................................................................... 191.3 External Interfaces ................................................................................................................ 20

1.3.1 PCIe Interface ................................................................................................................ 211.3.2 Network Interfaces.......................................................................................................... 211.3.3 Serial Flash Interface....................................................................................................... 211.3.4 SMBus Interface ............................................................................................................. 211.3.5 NC-SI Interface .............................................................................................................. 211.3.6 Software-Definable Pins (SDP) Interface (General-Purpose I/O)............................................. 221.3.7 LED Interface ................................................................................................................. 22

1.4 Feature Summary ................................................................................................................. 221.5 Overview: New Capabilities Beyond the X540 ............................................................................ 27

1.5.1 NBASE-T Support ............................................................................................................ 271.5.2 Filtering Capabilities ........................................................................................................ 271.5.3 IEEE 1588 Improvements................................................................................................. 271.5.4 Manageability ................................................................................................................. 28

1.6 Conventions ......................................................................................................................... 281.6.1 Terminology and Acronyms .............................................................................................. 281.6.2 Byte Ordering ................................................................................................................. 28

1.7 References ........................................................................................................................... 291.8 Architecture and Basic Operation ............................................................................................. 31

1.8.1 Transmit (Tx) Data Flow................................................................................................... 311.8.2 Receive (Rx) Data Flow.................................................................................................... 32

2.0 Pin Interface ......................................................................................................... 332.1 Signal Type Definition ............................................................................................................ 332.2 Pin Assignments ................................................................................................................... 34

2.2.1 PCIe.............................................................................................................................. 342.2.2 MDI............................................................................................................................... 352.2.3 Serial Flash .................................................................................................................... 362.2.4 SMBus ........................................................................................................................... 372.2.5 NC-SI ............................................................................................................................ 372.2.6 Software Defined Pins (SDPs) ........................................................................................... 382.2.7 LEDs ............................................................................................................................. 382.2.8 RSVD and No-Connect Pins............................................................................................... 392.2.9 Miscellaneous ................................................................................................................. 412.2.10 JTAG ............................................................................................................................. 422.2.11 Power Supplies ............................................................................................................... 43

2.3 Pull-Up/Pull-Down Information ................................................................................................ 452.3.1 External Pull-Ups............................................................................................................. 45

2.4 Strapping Options ................................................................................................................. 452.5 Ball Out Top View Through Package ..................................................................................... 46

3.0 Interconnects ....................................................................................................... 493.1 PCI Express (PCIe) ................................................................................................................ 49

3.1.1 General Overview............................................................................................................ 493.1.2 Transaction Layer............................................................................................................ 50

Intel Ethernet Controller X550 DatasheetContents

4 333369-004

3.1.3 Link Layer ...................................................................................................................... 583.1.4 Physical Layer................................................................................................................. 603.1.5 Error Events and Error Reporting....................................................................................... 643.1.6 Performance and Statistics Counters.................................................................................. 70

3.2 Management Interfaces ......................................................................................................... 783.2.1 SMBus ........................................................................................................................... 78

3.3 Network Controller Sideband Interface (NC-SI) ..................................................................... 783.3.1 Electrical Characteristics .................................................................................................. 783.3.2 NC-SI Transactions ......................................................................................................... 783.3.3 MCTP (Over PCIe or SMBus) ............................................................................................. 79

3.4 Non-Volatile Memory (NVM) ................................................................................................... 793.4.1 General Overview............................................................................................................ 793.4.2 Shadow RAM .................................................................................................................. 803.4.3 NVM Clients and Interfaces............................................................................................... 813.4.4 Flash Access Contention................................................................................................... 833.4.5 Signature Field ............................................................................................................... 843.4.6 VPD Support................................................................................................................... 843.4.7 NVM Read, Write, and Erase Sequences ............................................................................. 863.4.8 Extended NVM Flows ....................................................................................................... 893.4.9 NVM Authentication Procedure .......................................................................................... 91

3.5 Configurable I/O Pins Software-Definable Pins (SDPs) ............................................................ 933.5.1 I2C Over SDP ................................................................................................................. 95

3.6 LEDs ................................................................................................................................... 973.7 Network Interface ................................................................................................................. 98

3.7.1 Overview ....................................................................................................................... 983.7.2 Internal MDIO Interface ................................................................................................... 993.7.3 Integrated Copper PHY Functionality ................................................................................ 1003.7.4 Ethernet Flow Control (FC) ............................................................................................. 1083.7.5 Inter Packet Gap (IPG) Control and Pacing........................................................................ 119

4.0 Initialization ....................................................................................................... 1214.1 Power Up ........................................................................................................................... 121

4.1.1 Power-Up Sequence ...................................................................................................... 1214.1.2 Power-Up Timing Diagram.............................................................................................. 1224.1.3 Main-Power/Aux-Power Operation ................................................................................... 125

4.2 Reset Operation .................................................................................................................. 1264.2.1 Reset Sources............................................................................................................... 1264.2.2 Reset in PCI-IOV Environment ........................................................................................ 1314.2.3 Reset Effects ................................................................................................................ 132

4.3 Queue Disable .................................................................................................................... 1354.4 Function Disable ................................................................................................................. 136

4.4.1 General ....................................................................................................................... 1364.4.2 Overview ..................................................................................................................... 1364.4.3 Control Options............................................................................................................. 1374.4.4 Event Flow for Enable/Disable Functions........................................................................... 138

4.5 Device Disable .................................................................................................................... 1394.5.1 Overview ..................................................................................................................... 1394.5.2 BIOS Disable of the Device at Boot Time by Using the Strapping Option ............................... 140

4.6 Software Initialization and Diagnostics ................................................................................... 1404.6.1 Introduction ................................................................................................................. 1404.6.2 Power-Up State ............................................................................................................ 140

333369-004 5


4.6.3 Initialization Sequence................................................................................................... 1414.6.4 100 Mb/s, 1 GbE, and 10 GbE Link Initialization ................................................................ 1424.6.5 Initialization of Statistics ................................................................................................ 1424.6.6 Interrupt Initialization.................................................................................................... 1434.6.7 Receive Initialization...................................................................................................... 1434.6.8 Transmit Initialization .................................................................................................... 1464.6.9 FCoE Initialization Flow .................................................................................................. 1484.6.10 Virtualization Initialization Flow ....................................................................................... 1484.6.11 DCB Configuration......................................................................................................... 1514.6.12 Security Initialization ..................................................................................................... 1614.6.13 Alternate MAC Address Support....................................................................................... 162

4.7 Access to Shared Resources ................................................................................................. 163

5.0 Power Management and Delivery ........................................................................ 1655.1 Power Targets and Power Delivery ......................................................................................... 1655.2 Power Management ............................................................................................................. 165

5.2.1 Introduction to X550 Power States .................................................................................. 1655.2.2 Auxiliary Power Usage ................................................................................................... 1665.2.3 PCIe Link Power Management ......................................................................................... 1665.2.4 Power States ................................................................................................................ 1675.2.5 Timing of Power-State Transitions ................................................................................... 172

5.3 Network Interfaces Power Management .................................................................................. 1765.3.1 PHY Power-Down State .................................................................................................. 1765.3.2 PHY Power-Down via the PHY Register ............................................................................. 1775.3.3 Smart Power-Down (SPD) .............................................................................................. 1775.3.4 Disable 10GBASE-T and/or 1000BASE-T Speeds................................................................ 1795.3.5 Low Power Link Up (LPLU) .............................................................................................. 1795.3.6 Energy Efficient Ethernet (EEE) ....................................................................................... 184

5.4 Wake-Up ........................................................................................................................... 1875.4.1 Advanced Power Management Wake-Up ........................................................................... 1875.4.2 ACPI Power Management Wake-Up.................................................................................. 1875.4.3 Wake-Up Packets .......................................................................................................... 1885.4.4 Wake-Up and Virtualization ............................................................................................ 192

5.5 DMA Coalescing .................................................................................................................. 1935.5.1 DMA Coalescing Activation.............................................................................................. 1935.5.2 DMA Coalescing Operating Mode ..................................................................................... 1945.5.3 DMA Coalescing Recommended Settings........................................................................... 195

5.6 LTR ................................................................................................................................... 1965.6.1 LTR Algorithm............................................................................................................... 1965.6.2 LTR Initialization Flow.................................................................................................... 197

5.7 Thermal Management .......................................................................................................... 1975.7.1 General ....................................................................................................................... 1975.7.2 MC-Based Mode ............................................................................................................ 1985.7.3 NVM-Based Mode .......................................................................................................... 1985.7.4 Thermal Sensor Control ................................................................................................. 1995.7.5 Thermal Sensor Characteristics ....................................................................................... 199

6.0 Non-Volatile Memory Map ................................................................................... 2016.1 NVM Organization ............................................................................................................... 201

6.1.1 Protected Areas ............................................................................................................ 2046.2 NVM Header ....................................................................................................................... 2056.3 Software Sections ............................................................................................................... 207


6 333369-004

6.3.1 Software Compatibility Module Word Address 0x10-0x14 ................................................ 2076.3.2 PBA Number Module Word Address 0x15-0x16 .............................................................. 2086.3.3 Boot Configuration Block Word Address 0x17 ................................................................ 2096.3.4 Software Reserved Words 0x18-0x2E........................................................................... 2116.3.5 VPD Module Pointer Word Address 0x2F ....................................................................... 2146.3.6 PXE Configuration Words Word Address 0x30-0x36........................................................ 2156.3.7 Alternate Ethernet MAC Address Pointer Word Address 0x37 ........................................... 2186.3.8 FCoE Scratch Pad Pointer Word Address 0x39................................................................ 219

6.4 Hardware Sections .............................................................................................................. 2206.4.1 Hardware Section Auto-Load Sequence ........................................................................ 2206.4.2 NVM Init Module ........................................................................................................... 2206.4.3 PCIe Analog Configuration Module ................................................................................... 2236.4.4 PCIe Link Configuration Module ....................................................................................... 2236.4.5 PCIe General Configuration Module.................................................................................. 2246.4.6 PCIe Configuration Space 0/1 Modules ............................................................................. 2256.4.7 LAN Core 0/1 Modules ................................................................................................... 2266.4.8 CSR 0/1 Auto Configuration Modules................................................................................ 2296.4.9 PHY Auto Configuration Module ....................................................................................... 230

6.5 Firmware Sections ............................................................................................................... 2336.5.1 Firmware Module Header................................................................................................ 2336.5.2 Common Firmware Parameters Module Global MNG Offset 0x2 ........................................ 2346.5.3 Pass-Through LAN 0/1 Configuration Modules Global MNG Offsets 0x03 and 0x06 .............. 2356.5.4 Sideband Configuration Module Global MNG Offset 0x04 ................................................. 2426.5.5 Flexible TCO Filter Configuration Module Global MNG Offset 0x05..................................... 2486.5.6 Mini Loader Module ....................................................................................................... 2496.5.7 Firmware Image Module................................................................................................. 249

6.6 PCIe Expansion/Option ROM ................................................................................................. 2526.7 PHY Module ........................................................................................................................ 253

6.7.1 Register Provisional Table............................................................................................... 255

7.0 Inline Functions .................................................................................................. 2577.1 Receive Functionality ........................................................................................................... 257

7.1.1 MAC Layer - Receive...................................................................................................... 2577.1.2 Packet Filtering ............................................................................................................. 2587.1.3 Rx Queues Assignment .................................................................................................. 2637.1.4 Receive Data Storage in System Memory ......................................................................... 2897.1.5 Receive Descriptors ....................................................................................................... 2897.1.6 Receive Offloads ........................................................................................................... 3047.1.7 Receive Statistics .......................................................................................................... 309

7.2 Transmit Functionality ......................................................................................................... 3117.2.1 Packet Transmission ...................................................................................................... 3117.2.2 Transmit Contexts......................................................................................................... 3207.2.3 Transmit Descriptors ..................................................................................................... 3207.2.4 TCP and UDP Segmentation............................................................................................ 3357.2.5 Transmit Checksum Offloading in Non-Segmentation Mode ................................................. 3427.2.6 Transmit Statistics ........................................................................................................ 345

7.3 Interrupts .......................................................................................................................... 3477.3.1 Interrupt Registers ........................................................................................................ 3477.3.2 Interrupt Moderation ..................................................................................................... 3507.3.3 TCP Timer Interrupt....................................................................................................... 3527.3.4 Mapping of Interrupt Causes........................................................................................... 352

333369-004 7


7.4 802.1q VLAN Support .......................................................................................................... 3597.4.1 802.1q VLAN Packet Format ........................................................................................... 3597.4.2 802.1q Tagged Frames .................................................................................................. 3597.4.3 Transmitting and Receiving 802.1q Packets ...................................................................... 3607.4.4 802.1q VLAN Packet Filtering .......................................................................................... 3607.4.5 Double VLAN and Single VLAN Support ............................................................................ 3617.4.6 E-tag and VLAN ............................................................................................................ 363

7.5 TLP Processing Hints (TPH) ................................................................................................... 3657.5.1 Steering Tag and Processing Hint Programming................................................................. 365

7.6 Data Center Bridging (DCB) .................................................................................................. 3667.6.1 Overview ..................................................................................................................... 3667.6.2 Transmit-Side Capabilities .............................................................................................. 3687.6.3 Receive-Side Capabilities................................................................................................ 380

7.7 Time SYNC (IEEE1588 and 802.1AS) ..................................................................................... 3847.7.1 Overview ..................................................................................................................... 3847.7.2 Flow and Hardware/Software Responsibilities .................................................................... 3847.7.3 Hardware Time Sync Elements ........................................................................................ 3867.7.4 Hardware Time Sync Elements ........................................................................................ 3887.7.5 Time Sync Interrupts ..................................................................................................... 3917.7.6 PTP Packet Structure ..................................................................................................... 391

7.8 Virtualization ...................................................................................................................... 3957.8.1 Overview ..................................................................................................................... 3957.8.2 PCI-SIG SR-IOV Support ................................................................................................ 3997.8.3 Packet Switching........................................................................................................... 4097.8.4 Security Features .......................................................................................................... 4197.8.5 Virtualization of Hardware .............................................................................................. 424

7.9 Tunneling Support ............................................................................................................... 4247.10 Receive Side Coalescing (RSC) .............................................................................................. 425

7.10.1 Packet Candidacy for RSC .............................................................................................. 4277.10.2 Flow Identification and RSC Context Matching ................................................................... 4297.10.3 Processing New RSC ...................................................................................................... 4307.10.4 Processing Active RSC ................................................................................................... 4307.10.5 Packet DMA and Descriptor Write Back............................................................................. 4327.10.6 RSC Completion and Aging ............................................................................................. 434

7.11 Fibre Channel over Ethernet (FCoE) ....................................................................................... 4367.11.1 Introduction ................................................................................................................. 4367.11.2 FCoE Transmit Operation................................................................................................ 4377.11.3 FCoE Receive Operation ................................................................................................. 443

7.12 Reliability ........................................................................................................................... 4587.12.1 Memory Integrity Protection ........................................................................................... 4587.12.2 PCIe Error Handling....................................................................................................... 458

7.13 IPsec Support ..................................................................................................................... 4597.13.1 Overview ..................................................................................................................... 4597.13.2 Hardware Features List .................................................................................................. 4597.13.3 Software/Hardware Demarcation..................................................................................... 4627.13.4 IPsec Formats Exchanged Between Hardware and Software ................................................ 4637.13.5 Tx SA Table.................................................................................................................. 4677.13.6 Tx Hardware Flow ......................................................................................................... 4687.13.7 AES-128 Operation in Tx ................................................................................................ 4707.13.8 Rx Descriptors .............................................................................................................. 471


8 333369-004

7.13.9 Rx SA Tables ................................................................................................................ 4717.13.10 Rx Hardware Flow without TCP/UDP Checksum Offload....................................................... 4737.13.11 Rx Hardware Flow with TCP/UDP Checksum Offload ........................................................... 4747.13.12 AES-128 Operation in Rx................................................................................................ 475

8.0 Programming Interface ....................................................................................... 4778.1 General ............................................................................................................................. 477

8.1.1 Memory-Mapped Access................................................................................................. 4778.1.2 I/O-Mapped Access ....................................................................................................... 4788.1.3 Configuration Access to Internal Registers and Memories.................................................... 4798.1.4 Register Terminology..................................................................................................... 4818.1.5 VF Registers Allocated per Queue .................................................................................... 4818.1.6 Non-Queue VF Registers ................................................................................................ 482

8.2 Device Registers - PF ........................................................................................................... 4838.2.1 BAR0 Registers Summary............................................................................................... 4838.2.2 Detailed Register Description - PF BAR0 ........................................................................... 498

8.2.2.2 NVM Registers ....................................................................................................... 5118.2.2.3 Flow Control Registers ............................................................................................ 5178.2.2.4 PCIe Registers ....................................................................................................... 5208.2.2.5 PCIe Configuration Space Setting Registers................................................................ 5278.2.2.6 Interrupt Registers ................................................................................................. 5348.2.2.7 MSI-X Table Registers............................................................................................. 5428.2.2.8 Receive Registers ................................................................................................... 5438.2.2.9 Receive DMA Registers............................................................................................ 5568.2.2.10 Transmit Registers ................................................................................................. 5618.2.2.11 DCB Registers........................................................................................................ 5678.2.2.12 TPH Registers ........................................................................................................ 5748.2.2.13 Timers Registers .................................................................................................... 5768.2.2.14 FCoE Registers....................................................................................................... 5778.2.2.15 Flow Director Registers ........................................................................................... 5828.2.2.16 MAC Registers ....................................................................................................... 5928.2.2.17 Statistic Registers .................................................................................................. 5978.2.2.18 Wake-Up and Proxy Control Registers ....................................................................... 6208.2.2.19 Management Filters Registers .................................................................................. 6278.2.2.20 Manageability (ARC Subsystem) HOST Interface Registers ........................................... 6348.2.2.21 Time Sync (IEEE 1588) Registers ............................................................................. 6388.2.2.22 Virtualization PF Registers ....................................................................................... 6478.2.2.23 Power Management Registers .................................................................................. 6588.2.2.24 Security Registers .................................................................................................. 6648.2.2.25 IPsec Registers ...................................................................................................... 6678.2.2.26 VF Registers Mapping in the PF Space ....................................................................... 671

8.2.3 BAR3 Registers Summary............................................................................................... 6748.2.4 Detailed Register Description - PF BAR3 ........................................................................... 674

8.3 Device Registers - VF .......................................................................................................... 6768.3.1 BAR0 Registers Summary............................................................................................... 6768.3.2 Detailed Register Description - VF BAR0 ........................................................................... 6788.3.3 BAR3 Registers Summary............................................................................................... 6878.3.4 Detailed Register Description - VF BAR3 ........................................................................... 687

9.0 PCIe Programming Interface .............................................................................. 6899.1 Overview ........................................................................................................................... 689

9.1.1 Register Attributes ........................................................................................................ 690

333369-004 9


9.2 PCIe Register Map ............................................................................................................... 6919.2.1 PCIe Configuration Space Summary................................................................................. 6919.2.2 Mandatory PCI Configuration Registers............................................................................. 6939.2.3 PCI Capabilities............................................................................................................. 7009.2.4 PCIe Extended Configuration Space ................................................................................. 7249.2.5 Driver Forward Compatibility Register (0x94; RO).............................................................. 7459.2.6 CSR Access Via Configuration Address Space .................................................................... 745

9.3 Virtual Functions Configuration Space .................................................................................... 7469.3.1 Mandatory Configuration Space....................................................................................... 7489.3.2 PCI Capabilities............................................................................................................. 7499.3.3 PCIe Extended Capabilities ............................................................................................. 751

10.0 PHY Registers ..................................................................................................... 75310.1 Introduction ....................................................................................................................... 753

10.1.1 PHY Register Structure................................................................................................... 75310.1.2 Format and Nomenclature .............................................................................................. 75410.1.3 Structure ..................................................................................................................... 75510.1.4 PHY Registers and Documentation ................................................................................... 756

10.2 PMA Registers .................................................................................................................... 75710.2.1 PMA Standard Control 1: Address 1.0 .............................................................................. 75710.2.2 PMA Standard Status 1: Address 1.1................................................................................ 75710.2.3 PMA Standard Device Identifier 1: Address 1.2.................................................................. 75810.2.4 PMA Standard Device Identifier 2: Address 1.3.................................................................. 75810.2.5 PMA Standard Speed Ability: Address 1.4 ......................................................................... 75810.2.6 PMA Standard Devices in Package 1: Address 1.5 .............................................................. 75910.2.7 PMA Standard Devices in Package 2: Address 1.6 .............................................................. 76010.2.8 PMA Standard Control 2: Address 1.7 .............................................................................. 76010.2.9 PMA Standard Status 2: Address 1.8................................................................................ 76010.2.10 PMD Standard Transmit Disable Control: Address 1.9......................................................... 76210.2.11 PMD Standard Signal Detect: Address 1.A ........................................................................ 76210.2.12 PMD Standard 10G Extended Ability Register: Address 1.B ................................................. 76310.2.13 PMA Standard Package Identifier 1: Address 1.E ............................................................... 76310.2.14 PMA Standard Package Identifier 2: Address 1.F................................................................ 76310.2.15 PMA 10GBASE-T Status: Address 1.81 ............................................................................. 76310.2.16 PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82 ............................................. 76410.2.17 PMA 10GBASE-T Tx Power Backoff Setting: Address 1.83 ................................................... 76410.2.18 PMA 10GBASE-T Test Modes: Address 1.84 ...................................................................... 76510.2.19 PMA 10GBASE-T SNR Operating Margin Channel A: Address 1.85 ........................................ 76510.2.20 PMA 10GBASE-T SNR Operating Margin Channel B: Address 1.86 ........................................ 76510.2.21 PMA 10GBASE-T SNR Operating Margin Channel C: Address 1.87 ........................................ 76610.2.22 PMA 10GBASE-T SNR Operating Margin Channel D: Address 1.88 ........................................ 76610.2.23 PMA 10GBASE-T SNR Minimum Operating Margin Channel A: Address 1.89........................... 76610.2.24 PMA 10GBASE-T SNR Minimum Operating Margin Channel B: Address 1.8A........................... 76610.2.25 PMA 10GBASE-T SNR Minimum Operating Margin Channel C: Address 1.8B........................... 76710.2.26 PMA 10GBASE-T SNR Minimum Operating Margin Channel D: Address 1.8C .......................... 76710.2.27 PMA 10GBASE-T Receive Signal Power Channel A: Address 1.8D ......................................... 76710.2.28 PMA 10GBASE-T Receive Signal Power Channel B: Address 1.8E.......................................... 76710.2.29 PMA 10GBASE-T Receive Signal Power Channel C: Address 1.8F.......................................... 76810.2.30 PMA 10GBASE-T Receive Signal Power Channel D: Address 1.90 ......................................... 76810.2.31 PMA 10GBASE-T Skew Delay 1: Address 1.91 ................................................................... 76810.2.32 PMA 10GBASE-T Skew Delay 2: Address 1.92 ................................................................... 768


10 333369-004

10.2.33 PMA 10GBASE-T Fast Retrain Status and Control: Address 1.93........................................... 76910.2.34 PMA TimeSync Capability: Address 1.1800 ....................................................................... 76910.2.35 PMA TimeSync Transmit Path Data Delay 1: Address 1.1801............................................... 77010.2.36 PMA TimeSync Transmit Path Data Delay 2: Address 1.1802............................................... 77010.2.37 PMA TimeSync Transmit Path Data Delay 3: Address 1.1803............................................... 77010.2.38 PMA TimeSync Transmit Path Data Delay 4: Address 1.1804............................................... 77010.2.39 PMA TimeSync Receive Path Data Delay 1: Address 1.1805 ................................................ 77010.2.40 PMA TimeSync Receive Path Data Delay 2: Address 1.1806 ................................................ 77110.2.41 PMA TimeSync Receive Path Data Delay 3: Address 1.1807 ................................................ 77110.2.42 PMA TimeSync Receive Path Data Delay 4: Address 1.1808 ................................................ 77110.2.43 PMA Transmit Standard Interrupt Mask 1: Address 1.D000 ................................................. 77110.2.44 PMA Transmit Standard Interrupt Mask 2: Address 1.D001 ................................................. 77210.2.45 PMA Receive Reserved Vendor Provisioning 1: Address 1.E400 ............................................ 77210.2.46 PMA Receive Vendor State 1: Address 1.E800 ................................................................... 77310.2.47 PMA Receive Vendor State 2: Address 1.E811 ................................................................... 77310.2.48 PMA Vendor Global Interrupt Flags 1: Address 1.FC00........................................................ 773

10.3 PCS Registers ..................................................................................................................... 77410.3.1 PCS Standard Control 1: Address 3.0............................................................................... 77410.3.2 PCS Standard Status 1: Address 3.1 ................................................................................ 77410.3.3 PCS Standard Device Identifier 1: Address 3.2 .................................................................. 77510.3.4 PCS Standard Device Identifier 2: Address 3.3 .................................................................. 77510.3.5 PCS Standard Speed Ability: Address 3.4 ......................................................................... 77610.3.6 PCS Standard Devices in Package 1: Address 3.5 .............................................................. 77610.3.7 PCS Standard Devices in Package 2: Address 3.6 .............................................................. 77710.3.8 PCS Standard Control 2: Address 3.7............................................................................... 77710.3.9 PCS Standard Status 2: Address 3.8 ................................................................................ 77710.3.10 PCS Standard Package Identifier 1: Address 3.E ................................................................ 77810.3.11 PCS Standard Package Identifier 2: Address 3.F ................................................................ 77810.3.12 PCS 10GBASE-T Status 1: Address 3.20........................................................................... 77810.3.13 PCS 10GBASE-T Status 2: Address 3.21........................................................................... 77910.3.14 PCS TimeSync Capability: Address 3.1800........................................................................ 77910.3.15 PCS TimeSync Transmit Path Data Delay 1: Address 3.1801 ............................................... 78010.3.16 PCS TimeSync Transmit Path Data Delay 2: Address 3.1802 ............................................... 78010.3.17 PCS TimeSync Transmit Path Data Delay 3: Address 3.1803 ............................................... 78010.3.18 PCS TimeSync Transmit Path Data Delay 4: Address 3.1804 ............................................... 78010.3.19 PCS TimeSync Receive Path Data Delay 1: Address 3.1805................................................. 78010.3.20 PCS TimeSync Receive Path Data Delay 2: Address 3.1806................................................. 78110.3.21 PCS TimeSync Receive Path Data Delay 3: Address 3.1807................................................. 78110.3.22 PCS TimeSync Receive Path Data Delay 4: Address 3.1808................................................. 78110.3.23 PCS Transmit Vendor Provisioning 1: Address 3.C400 ........................................................ 78110.3.24 PCS Transmit Reserved Vendor Provisioning 1: Address 3.C410........................................... 78110.3.25 PCS Standard Interrupt Mask 1: Address 3.D000............................................................... 78210.3.26 PCS Standard Interrupt Mask 2: Address 3.D001............................................................... 78210.3.27 PCS Standard Interrupt Mask 3: Address 3.D002............................................................... 78210.3.28 PCS Receive Vendor State 1: Address 3.E800 ................................................................... 78310.3.29 PCS Receive Vendor Alarms 1: Address 3.EC00 ................................................................. 78310.3.30 PCS Receive Vendor Alarms 10: Address 3.EC09 ............................................................... 78410.3.31 PCS Vendor Global Interrupt Flags 1: Address 3.FC00 ........................................................ 78510.3.32 PCS Vendor Global Interrupt Flags 3: Address 3.FC02 ........................................................ 785

10.4 Auto-Negotiation Registers ................................................................................................... 786

333369-004 11


10.4.1 Auto-Negotiation Standard Control 1: Address 7.0............................................................. 78610.4.2 Auto-Negotiation Standard Status 1: Address 7.1 .............................................................. 78610.4.3 Auto-Negotiation Standard Device Identifier 1: Address 7.2 ................................................ 78710.4.4 Auto-Negotiation Standard Device Identifier 2: Address 7.3 ................................................ 78710.4.5 Auto-Negotiation Standard Devices in Package 1: Address 7.5 ............................................ 78810.4.6 Auto-Negotiation Standard Devices in Package 2: Address 7.6 ............................................ 78810.4.7 Auto-Negotiation Standard Status 2: Address 7.8 .............................................................. 78910.4.8 Auto-Negotiation Standard Package Identifier 1: Address 7.E .............................................. 78910.4.9 Auto-Negotiation Standard Package Identifier 2: Address 7.F .............................................. 78910.4.10 Auto-Negotiation Advertisement Register: Address 7.10 ..................................................... 79010.4.11 Auto-Negotiation Link Partner Base Page Ability Register: Address 7.13................................ 79110.4.12 Auto-Negotiation Extended Next Page Transmit Register: Address 7.16 ................................ 79210.4.13 Auto-Negotiation Extended Next Page Unformatted Code Register 1: Address 7.17 ................ 79210.4.14 Auto-Negotiation Extended Next Page Unformatted Code Register 2: Address 7.18 ................ 79310.4.15 Auto-Negotiation Link Partner Extended Next Page Ability Register: Address 7.19 .................. 79310.4.16 Auto-Negotiation Link Partner Extended Next Page Unformatted Code Register 1: Address 7.1A 79410.4.17 Auto-Negotiation Link Partner Extended Next Page Unformatted Code Register 2: Address 7.1B 79410.4.18 Auto-Negotiation 10GBASE-T Control Register: Address 7.20 .............................................. 79410.4.19 Auto-Negotiation 10GBASE-T Status Register: Address 7.21 ............................................... 79510.4.20 Auto-Negotiation Vendor Provisioning 1: Address 7.C400.................................................... 79510.4.21 Auto-Negotiation Reserved Vendor Provisioning 1: Address 7.C410...................................... 79610.4.22 Auto-Negotiation Reserved Vendor Provisioning 2: Address 7.C411...................................... 79710.4.23 Auto-Negotiation Vendor Status 1: Address 7.C800 ........................................................... 79810.4.24 Auto-Negotiation Reserved Vendor Status 1: Address 7.C810.............................................. 79810.4.25 Auto-Negotiation Reserved Vendor Status 2: Address 7.C811.............................................. 79910.4.26 Auto-Negotiation Reserved Vendor Status 3: Address 7.C812.............................................. 80010.4.27 Auto-Negotiation Reserved Vendor Status 4: Address 7.C813.............................................. 80010.4.28 Auto-Negotiation Reserved Vendor Status 5: Address 7.C814.............................................. 80010.4.29 Auto-Negotiation Transmit Vendor Alarms 1: Address 7.CC00 ............................................. 80010.4.30 Auto-Negotiation Transmit Vendor Alarms 2: Address 7.CC01 ............................................. 80110.4.31 Auto-Negotiation Standard Interrupt Mask 1: Address 7.D000............................................. 80110.4.32 Auto-Negotiation Standard Interrupt Mask 2: Address 7.D001............................................. 80210.4.33 Auto-Negotiation Transmit Vendor Interrupt Mask 1: Address 7.D400 .................................. 80210.4.34 Auto-Negotiation Transmit Vendor Interrupt Mask 2: Address 7.D401 .................................. 80210.4.35 Auto-Negotiation Transmit Vendor Interrupt Mask 3: Address 7.D402 .................................. 80310.4.36 Auto-Negotiation Receive Link Partner Status 1: Address 7.E820 ......................................... 80310.4.37 Auto-Negotiation Receive Link Partner Status 4: Address 7.E823 ......................................... 80310.4.38 Auto-Negotiation Receive Vendor Alarms 1: Address 7.EC00 ............................................... 80410.4.39 Auto-Negotiation Receive Vendor Alarms 2: Address 7.EC01 ............................................... 80410.4.40 Auto-Negotiation Receive Vendor Alarms 3: Address 7.EC02 ............................................... 80410.4.41 Auto-Negotiation Receive Vendor Alarms 4: Address 7.EC03 ............................................... 80410.4.42 Auto-Negotiation Receive Vendor Interrupt Mask 1: Address 7.F400..................................... 80510.4.43 Auto-Negotiation Receive Vendor Interrupt Mask 2: Address 7.F401..................................... 80510.4.44 Auto-Negotiation Receive Vendor Interrupt Mask 3: Address 7.F402..................................... 80510.4.45 Auto-Negotiation Receive Vendor Interrupt Mask 4: Address 7.F403..................................... 80510.4.46 Auto-Negotiation Vendor Global Interrupt Flags 1: Address 7.FC00 ...................................... 806

10.5 100BASE-TX and 1000BASE-T Registers ................................................................................. 80710.5.1 GbE Standard Device Identifier 1: Address 1D.2................................................................ 80710.5.2 GbE Standard Device Identifier 2: Address 1D.3................................................................ 80710.5.3 GbE Standard Devices in Package 1: Address 1D.5 ............................................................ 807


12 333369-004

10.5.4 GbE Standard Vendor Devices in Package 2: Address 1D.6 ................................................. 80810.5.5 GbE Standard Status 2: Address 1D.8.............................................................................. 80810.5.6 GbE Standard Package Identifier 1: Address 1D.E.............................................................. 80810.5.7 GbE Standard Package Identifier 2: Address 1D.F.............................................................. 80910.5.8 GbE Reserved Provisioning 2: Address 1D.C501 ................................................................ 809

10.6 Global Registers .................................................................................................................. 81010.6.1 Global Standard Control 1: Address 1E.0 .......................................................................... 81010.6.2 Global Standard Device Identifier 1: Address 1E.2 ............................................................. 81010.6.3 Global Standard Device Identifier 2: Address 1E.3 ............................................................. 81010.6.4 Global Standard Devices in Package 1: Address 1E.5 ......................................................... 81010.6.5 Global Standard Vendor Devices in Package 2: Address 1E.6............................................... 81110.6.6 Global Standard Status 2: Address 1E.8 ........................................................................... 81210.6.7 Global Standard Package Identifier 1: Address 1E.E ........................................................... 81210.6.8 Global Standard Package Identifier 2: Address 1E.F ........................................................... 81210.6.9 Global Firmware ID: Address 1E.20 ................................................................................. 81210.6.10 Global Diagnostic Provisioning: Address 1E.C400............................................................... 81210.6.11 Global Thermal Provisioning 2: Address 1E.C421 ............................................................... 81310.6.12 Global Thermal Provisioning 3: Address 1E.C422 ............................................................... 81310.6.13 Global Thermal Provisioning 4: Address 1E.C423 ............................................................... 81310.6.14 Global Thermal Provisioning 5: Address 1E.C424 ............................................................... 81310.6.15 Global Reserved Provisioning 1: Address 1E.C470.............................................................. 81410.6.16 Global Reserved Provisioning 3: Address 1E.C472.............................................................. 81410.6.17 Global Reserved Provisioning 5: Address 1E.C474.............................................................. 81510.6.18 Global Reserved Provisioning 6: Address 1E.C475.............................................................. 81510.6.19 Global SMBus 0 Provisioning 6: Address 1E.C485 .............................................................. 81610.6.20 Global SMBus 1 Provisioning 6: Address 1E.C495 .............................................................. 81610.6.21 Global Cable Diagnostic Status 1: Address 1E.C800 ........................................................... 81610.6.22 Global Cable Diagnostic Status 2: Address 1E.C801 ........................................................... 81710.6.23 Global Cable Diagnostic Status 3: Address 1E.C802 ........................................................... 81710.6.24 Global Cable Diagnostic Status 4: Address 1E.C803 ........................................................... 81810.6.25 Global Cable Diagnostic Status 5: Address 1E.C804 ........................................................... 81810.6.26 Global Cable Diagnostic Status 6: Address 1E.C805 ........................................................... 81810.6.27 Global Cable Diagnostic Status 7: Address 1E.C806 ........................................................... 81810.6.28 Global Cable Diagnostic Status 8: Address 1E.C807 ........................................................... 81910.6.29 Global Thermal Status 1: Address 1E.C820....................................................................... 81910.6.30 Global Thermal Status 2: Address 1E.C821....................................................................... 81910.6.31 Global General Status 1: Address 1E.C830 ....................................................................... 81910.6.32 Global Fault Message: Address 1E.C850 ........................................................................... 82010.6.33 Global Primary Status: Address 1E.C851 .......................................................................... 82010.6.34 Global Cable Diagnostic Impedance 1: Address 1E.C880..................................................... 82110.6.35 Global Cable Diagnostic Impedance 2: Address 1E.C881..................................................... 82210.6.36 Global Cable Diagnostic Impedance 3: Address 1E.C882..................................................... 82310.6.37 Global Cable Diagnostic Impedance 4: Address 1E.C883..................................................... 82410.6.38 Global Status: Address 1E.C884...................................................................................... 82410.6.39 Global Reserved Status 1: Address 1E.C885 ..................................................................... 82510.6.40 Global Reserved Status 2: Address 1E.C886 ..................................................................... 82510.6.41 Global Reserved Status 3: Address 1E.C887 ..................................................................... 82510.6.42 Global Reserved Status 4: Address 1E.C888 ..................................................................... 82610.6.43 Global Alarms 1: Address 1E.CC00 .................................................................................. 82710.6.44 Global Alarms 2: Address 1E.CC01 .................................................................................. 828

333369-004 13


10.6.45 Global Alarms 3: Address 1E.CC02 .................................................................................. 82910.6.46 Global Interrupt Mask 1: Address 1E.D400 ....................................................................... 83010.6.47 Global Interrupt Mask 2: Address 1E.D401 ....................................................................... 83110.6.48 Global Interrupt Mask 3: Address 1E.D402 ....................................................................... 83210.6.49 Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00.............................................. 83310.6.50 Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01 ................................................ 83410.6.51 Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00 .............................................. 83510.6.52 Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01................................................. 836

11.0 System Manageability ......................................................................................... 83711.1 Pass-Through (PT) Functionality ............................................................................................ 837

11.1.1 Supported Topologies .................................................................................................... 83811.1.2 Pass-Through Packet Routing.......................................................................................... 838

11.2 Components of the Sideband Interface ................................................................................... 83911.2.1 Physical Layer............................................................................................................... 83911.2.2 Logical Layer ................................................................................................................ 840

11.3 Packet Filtering ................................................................................................................... 84211.3.1 Manageability Receive Filtering ....................................................................................... 84211.3.2 L2 Filters...................................................................................................................... 84311.3.3 L3/L4 Filtering .............................................................................................................. 84411.3.4 Flexible 128 Byte Filter .................................................................................................. 84611.3.5 Configuring Manageability Filters ..................................................................................... 84711.3.6 Filtering Programming Interfaces..................................................................................... 85011.3.7 Possible Configurations .................................................................................................. 85111.3.8 Determining Manageability MAC Address .......................................................................... 852

11.4 OS-to-BMC Traffic ............................................................................................................... 85311.4.1 Overview ..................................................................................................................... 85311.4.2 Filtering ....................................................................................................................... 85411.4.3 Blocking of Network to BMC Flow..................................................................................... 85511.4.4 OS2BMC and Flow Control .............................................................................................. 85511.4.5 Statistics...................................................................................................................... 85611.4.6 OS-to-BMC Enablement ................................................................................................. 856

11.5 SMBus Pass-Through Interface .............................................................................................. 85711.5.1 General ....................................................................................................................... 85711.5.2 Pass-Through Capabilities............................................................................................... 85711.5.3 Port to SMBus Mapping .................................................................................................. 85711.5.4 Automatic Ethernet ARP Operation .................................................................................. 85811.5.5 SMBus Transactions....................................................................................................... 85811.5.6 SMBus Notification Methods............................................................................................ 86311.5.7 Receive Pass-Through Flow ............................................................................................ 86611.5.8 Transmit Pass-Through Flow ........................................................................................... 86611.5.9 SMBus Link State Control ............................................................................................... 86811.5.10 SMBus ARP Transactions ................................................................................................ 86811.5.11 SMBus Pass-Through Transactions................................................................................... 87111.5.12 Example Configuration Steps .......................................................................................... 89311.5.13 SMBus Troubleshooting.................................................................................................. 902

11.6 NC-SI Pass-Through Interface ............................................................................................... 90511.6.1 Overview ..................................................................................................................... 90511.6.2 NC-SI Standard Support ................................................................................................ 90911.6.3 NC-SI Mode Intel Specific Commands........................................................................... 91111.6.4 Asynchronous Event Notifications .................................................................................... 964


14 333369-004

11.6.5 Querying Active Parameters............................................................................................ 96411.6.6 Resets ......................................................................................................................... 96511.6.7 Advanced Workflows...................................................................................................... 96511.6.8 External Link Control via NC-SI ....................................................................................... 968

11.7 MCTP ................................................................................................................................ 97011.7.1 MCTP Overview............................................................................................................. 97011.7.2 NC-SI to MCTP Mapping ................................................................................................. 97111.7.3 MCTP Over PCIe............................................................................................................ 97611.7.4 MCTP Over SMBus......................................................................................................... 97811.7.5 NC-SI Over MCTP.......................................................................................................... 97911.7.6 MCTP Programming ....................................................................................................... 981

11.8 Manageability Host Interface ................................................................................................ 98511.8.1 HOST CSR Interface (Function 1/0) ................................................................................. 98511.8.2 Host Slave Command Interface to Manageability ............................................................... 98511.8.3 Host Interface Commands .............................................................................................. 98711.8.4 Software and Firmware Synchronization ........................................................................... 994

11.9 Host Isolate Support ............................................................................................................ 997

12.0 Electrical/Mechanical Specification ..................................................................... 99912.1 Introduction ....................................................................................................................... 99912.2 Operating Conditions ........................................................................................................... 999

12.2.1 Absolute Maximum Ratings............................................................................................. 99912.2.2 Recommended Operating Conditions.............................................................................. 1000

12.3 Power Delivery ................................................................................................................. 100012.3.1 Power Delivery Definitions ............................................................................................ 100012.3.2 Power Supply Specifications.......................................................................................... 100012.3.3 VCC3P3 External Power Supply Specification (3.3 V) ........................................................ 100112.3.4 VCC2P1 External Power Supply Specification (2.1 V) ........................................................ 100212.3.5 VCC1P2 External Power Supply Specification (1.2 V) ........................................................ 100212.3.6 VCC0P83 External Power Supply Specification (0.83 V) .................................................... 100312.3.7 Power On/Off Sequence ............................................................................................... 100312.3.8 Power On Reset .......................................................................................................... 100412.3.9 Current Consumption................................................................................................... 100512.3.10 Peak Current Consumption ........................................................................................... 1008

12.4 DC/AC Specifications ......................................................................................................... 100912.4.1 Digital Functional 3.3 V I/O DC Electrical Characteristics................................................... 100912.4.2 Open Drain I/Os.......................................................................................................... 101112.4.3 NC-SI I/O DC Specification ........................................................................................... 101212.4.4 Digital I/F AC Specifications.......................................................................................... 101312.4.5 PCIe Interface AC/DC Specification ................................................................................ 101812.4.6 Network Interface AC/DC Specification........................................................................... 1018

12.5 Thermal Diode .................................................................................................................. 101912.6 Crystal Specification .......................................................................................................... 102012.7 Package ........................................................................................................................... 1021

12.7.1 Mechanical ................................................................................................................. 102112.7.2 Thermal..................................................................................................................... 102112.7.3 Electrical.................................................................................................................... 102112.7.4 Mechanical Package Diagram ........................................................................................ 1022

13.0 Design Considerations and Guidelines ............................................................... 102513.1 Connecting the PCIe Interface ............................................................................................ 1025

13.1.1 Link Width Configuration .............................................................................................. 1025

333369-004 15


13.1.2 Polarity Inversion and Lane Reversal.............................................................................. 102513.1.3 PCIe Reference Clock................................................................................................... 102613.1.4 Bias Resistor .............................................................................................................. 102613.1.5 Miscellaneous PCIe Signals ........................................................................................... 102613.1.6 PCIe Layout Recommendations ..................................................................................... 1026

13.2 Connecting the 10GBASE-T MDI Interfaces ........................................................................... 102613.2.1 MDI Circuit Guidelines.................................................................................................. 102713.2.2 Magnetics Module........................................................................................................ 102713.2.3 5th Channel ............................................................................................................... 102713.2.4 Board Noise Cancellation.............................................................................................. 102813.2.5 MDI Layout Guidance................................................................................................... 102813.2.6 PHY MDI Lane Swap Configuration................................................................................. 103413.2.7 Center Tap Connection Via Capacitors to Ground ............................................................. 1034

13.3 Connecting the Power Supply Delivery Network ..................................................................... 103513.4 Connecting the Flash Interface ............................................................................................ 1036

13.4.1 Connecting the Flash ................................................................................................... 103613.4.2 Supported Flash Devices .............................................................................................. 1036

13.5 Connecting Manageability Interfaces .................................................................................... 103713.5.1 Connecting the SMBus Interface.................................................................................... 103713.5.2 Connecting the NC-SI Interface..................................................................................... 103713.5.3 Layout Requirements................................................................................................... 1039

13.6 Connecting the Software-Definable Pins (SDPs) ..................................................................... 104013.7 Connecting the Light Emitting Diodes (LEDs) ........................................................................ 104013.8 Connecting Miscellaneous Signals ........................................................................................ 1041

13.8.1 LAN Disable................................................................................................................ 104113.8.2 BIOS Handling of Device Disable ................................................................................... 1042

13.9 Connecting the JTAG Port ................................................................................................... 104213.10 Power On Reset (POR) ....................................................................................................... 104213.11 Crystal Design Considerations ............................................................................................. 1043

13.11.1 Quartz Crystal ............................................................................................................ 104313.11.2 Vibrational Mode ......................................................................................................... 104313.11.3 Frequency Tolerance.................................................................................................... 104313.11.4 Temperature Stability and Environmental Requirements ................................................... 104313.11.5 Calibration Mode ......................................................................................................... 104413.11.6 Reference Crystal Circuit .............................................................................................. 104413.11.7 Crystal Load Capacitance ............................................................................................. 104413.11.8 Shunt Capacitance ...................................................................................................... 104513.11.9 Equivalent Series Resistance (ESR)................................................................................ 104513.11.10 Driver Level................................................................................................................ 104513.11.11 Aging ........................................................................................................................ 104513.11.12 Reference Crystal........................................................................................................ 104513.11.13 Reference Crystal Selection .......................................................................................... 104613.11.14 Circuit Board .............................................................................................................. 104613.11.15 Temperature Changes.................................................................................................. 1046

13.12 PCB Guidelines ................................................................................................................. 104713.12.1 Board Stack-Up Example.............................................................................................. 104713.12.2 Customer Reference Board Stack-Up Example................................................................. 104813.12.3 Intel Reference Board Stack-Up Example........................................................................ 104913.12.4 Via Usage .................................................................................................................. 105013.12.5 Reference Planes......................................................................................................... 1051


16 333369-004

13.12.6 Reducing Circuit Inductance ......................................................................................... 105213.12.7 Signal Isolation........................................................................................................... 105313.12.8 Traces for Decoupling Capacitors................................................................................... 105313.12.9 Power and Ground Planes............................................................................................. 105413.12.10 Recommended Simulations........................................................................................... 1059

13.13 Bill Of Material (BOM) ........................................................................................................ 1060

14.0 Thermal Design Recommendations ................................................................... 106114.1 Introduction ..................................................................................................................... 106114.2 Intended Audience ............................................................................................................ 106214.3 Measuring Thermal Conditions ............................................................................................ 106214.4 Thermal Considerations .........................................................................

intel ethernet controller x550 general ... intel® ethernet controller x550 datasheet—contents 6...

Documents