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Instruction List S7-400 CPU 412-2 PN, 414-3 PN/DP, 414F-3 PN/DP, 416-3 PN/DP, 416F-3 PN/DP 10/2010 A5E03305792-02

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Instruction List S7-400

CPU 412-2 PN, 414-3 PN/DP, 414F-3 PN/DP, 416-3 PN/DP, 416F-3 PN/DP

10/2010 A5E03305792-02

Copyright © Siemens AG 2010 All rights reserved Disclaimer of Liability The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved.

We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed.

Siemens AG Industry Sector Postfach 4848, D-90327 Nürnberg

© Siemens AG 2010 Subject to change without prior notice.

Siemens Aktiengesellschaft Siemens Aktiengesellschaft

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 3

Contents Applicability ..................................................................................................................................................... 5 Address Identifier and Parameter Ranges.................................................................................................... 6 Constants and Ranges.................................................................................................................................... 8 Abbreviations................................................................................................................................................... 9 Registers ........................................................................................................................................................ 11 Examples of Addressing............................................................................................................................... 13 Examples of how to calculate the pointer................................................................................................... 15 Execution Times with Indirect Addressing................................................................................................. 16 Examples of Calculations ............................................................................................................................. 18 List of Instructions ........................................................................................................................................ 20

Bit Logic Instructions .............................................................................................................................................................................21 Bit Logic Instructions with Parenthetical Expressions ...........................................................................................................................24 ORing of AND Instructions ....................................................................................................................................................................26 Logic Instructions with Timers and Counters ........................................................................................................................................27 Logic Instructions with Timers and Counters, continued..................................................................Fehler! Textmarke nicht definiert. Word Logic Instructions with the Contents of Accumulator 1 ................................................................................................................29 Evaluating Conditions Using AND, OR and EXCLUSIVE OR...............................................................................................................30 Edge-Triggered Instructions ..................................................................................................................................................................32 Setting/Resetting Bit Addresses............................................................................................................................................................33 Instructions Directly Affecting the RLO..................................................................................................................................................35 Timer Instructions ..................................................................................................................................................................................36 Counter Instructions ..............................................................................................................................................................................39 Load Instructions ...................................................................................................................................................................................41 Load Instructions for Timers and Counters ...........................................................................................................................................46 Transfer Instructions..............................................................................................................................................................................47 Load and Transfer Instructions for Address Registers ..........................................................................................................................50 Load and Transfer Instructions for the Status Word..............................................................................................................................52 Load Instructions for DB Number and DB Length .................................................................................................................................53 Integer Math (16 Bits) ............................................................................................................................................................................54

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 4

Integer Math (32 Bits) ............................................................................................................................................................................55 Floating-Point Math (32 Bits) .................................................................................................................................................................56 Square Root and Square Instructions (32 Bits).....................................................................................................................................58 Logarithmic Function (32 Bits)...............................................................................................................................................................59 Trigonometrical Functions (32 Bits).......................................................................................................................................................60 Adding Constants ..................................................................................................................................................................................61 Adding Using Address Registers...........................................................................................................................................................62 Comparison Instructions (16-Bit Integers) .............................................................................................................................................63 Comparison Instructions (32-Bit Integers) .............................................................................................................................................64 Comparison Instructions (32-Bit Real Numbers) ...................................................................................................................................65 Shift Instructions ....................................................................................................................................................................................66 Rotate Instructions.................................................................................................................................................................................68 Accumulator Transfer Instructions, Incrementing and Decrementing ...................................................................................................69 Program Display and Null Operation Instructions .................................................................................................................................70 Data Type Conversion Instructions .......................................................................................................................................................71 Forming the Ones and Twos Complements..........................................................................................................................................74 Block Call Instructions ...........................................................................................................................................................................75 Block End Instructions...........................................................................................................................................................................78 Exchanging Shared Data Block and Instance Data Block.....................................................................................................................79 Jump Instructions ..................................................................................................................................................................................80 Instructions for the Master Control Relay (MCR) ..................................................................................................................................85 Organization Blocks (OB)......................................................................................................................................................................87 Function Blocks (FB) .............................................................................................................................................................................91 Functions (FC) and Data Blocks (DB) ...................................................................................................................................................92 System Functions ..................................................................................................................................................................................93 System Function Blocks ......................................................................................................................................................................121

Sublist of the System Status List (SSL) .................................................................................................... 131 Alphabetical Index of Instructions............................................................................................................. 136

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 5

Applicability

This list of instructions applies to the CPUs listed below.

Name Order number subsequently described as 1)

CPU 412-2 PN 6ES7412-2EK06-0AB0 CPU 412

CPU 414-3PN/DP 6ES7414-3EM06-0AB0 CPU 414

CPU 414F-3 PN/DP 6ES7414-3FM06-0AB0 CPU 414

CPU 416-3 PN/DP 6ES7416-3ES06-0AB0 CPU 416

CPU 416F-3 PN/DP 6ES7416-3FS06-0AB0 CPU 416

1) except in the tables, where a detailed differentiation is necessary

Address Identifier and Parameter Ranges

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 6

Address Identifier and Parameter Ranges Parameter Range Description Addr.

ID CPU 412 CPU 414 CPU 416

Q 1) 0.0 to 127.7 0.0 to 255.7 0.0 to 511.7 Output (in PIQ) QB 1) 0 to 127 0 to 255 0 to 511 Output byte (in PIQ) QW 1) 0 to 126 0 to 254 0 to 510 Output word (in PIQ) QD 1) 0 to 124 0 to 252 0 to 508 Output double word (in PIQ) DBX 0.0 to 65533.7 Data bit in data block DB 1 to 16000 2) Data block DBB 0 to 65533 Data byte in DB DBW 0 to 65532 Data word in DB DBD 0 to 65530 Data double word in DB DIX 0.0 to 65533.7 Data bit in instance DB DI 1 to 16000 2) Instance data block DIB 0 to 65533 Data byte in instance DB DIW 0 to 65532 Data word in instance DB DID 0 to 65530 Data double word instance DB

1) Default setting can be changed, see Technical Specifications 2) Number of DBs for CPU 412: 3000, for CPU 414: 6000, for CPU 416: 10000

Address Identifier and Parameter Ranges

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 7

Parameter Range Description Addr. ID CPU 412 CPU 414 CPU 416

I 1) 0.0 to 127.7 0.0 to 255.7 0.0 to 511.7 Input bit (in PII) IB 1) 0 to 127 0 to 255 0 to 511 Input byte (in PII) IW 1) 0 to 126 0 to 254 0 to 510 Input word (in PII) ID 1) 0 to 124 0 to 252 0 to 508 Input double word (in PII) L 1) 0.0 to 4095.7 0.0 to 8191.7 0.0 to 16383.7 Local data LB 1) 0 to 4095 0 to 8191 0 to 16383 Local data byte LW 1) 0 to 4094 0 to 8190 0 to 16382 Local data word LD 1) 0 to 4092 0 to 8188 0 to 16380 Local data double word M 0.0 to 4095.7 0.0 to 8191.7 0.0 to 16383.7 Bit memory MB 0 to 4095 0 to 8191 0 to 16383 memory byte MW 0 to 4094 0 to 8190 0 to 16382 memory word MD 0 to 4092 0 to 8188 0 to 16380 memory double word PQB 0 to 4095 0 to 8191 0 to 16383 Peripheral output byte (direct I/O access)

PQW 0 to 4094 0 to 8190 0 to 16382 Peripheral output word (direct I/O access)

PQD 0 to 4092 0 to 8188 0 to 16380 Peripheral output double word (direct I/O access)

PIB 0 to 4095 0 to 8191 0 to 16383 Peripheral input byte (direct I/O access)

PEW 0 to 4094 0 to 8190 0 to 16382 Peripheral input word (direct I/O access)

PID 0 to 4092 0 to 8188 0 to 16380 Peripheral output double word (direct I/O access)

T 0 to 2047 0 to 2047 0 to 2047 Timer

C 0 to 2047 0 to 2047 0 to 2047 Counter

1) Default setting can be changed, see Technical Specifications

Constants and Ranges

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 8

Constants and Ranges Constant Range Description

B(b1,b2) B(b1,b2,b3,b4)

- Constant, 2 or 4 bytes

D# Date - IEC date constant

L# Integer - 32-bit integer constant

P# Bit pointer - Pointer constant

S5T# Time value - S7 time constant 1)

T# TIme value - Time constant

TOD# Time value - IEC time constant

C# Count value - Counter constant (BCD code)

2#n - Binary constant

W#16# DW#16#

- Hexadecimal constant

1) For loading of S7 timers

Abbreviations

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 9

Abbreviations The following abbreviations and mnemonics are used in the Instruction List:

Abbrev. Description Example

k8 8-bit constant 0 to 255

32

k16 16-bit constant 256 to 32 767

28 131

k32 32-bit constant 32 768 to 999 999 999

127 624

i8 8-bit integer -128 to +127

-113

i16 16-bit integer -32768 to +32767

+6523

i32 32-bit integer -2 147 483 648 to +2 147 483 647

-2 222 222

m Pointer constant P#240.3

n Binary constant 1001 1100

p Hexadecimal constant EA12

Label Symbolic jump address (max. 4 characters) DEST

a Byte address

Abbreviations

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 10

Abbrev. Description Example

b Bit address

c Address area I, Q, M, L, DBX, DIX

d Address in: MD, DBD, DID or LD

e Number in: MW, DBW, DIW or LW

f Timer/counter No.

g Address area IB, QB, PIB, PQB, MB, LB, DBB, DIB

h Address area IW, QW, PIW, PQW, MW, LW, DBW, DIW

i Address area ID, QD, PID, PQD, MD, LD, DBD, DID

q Block No.

Registers

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 11

Registers

ACCU1 to ACCU4 (32 Bit) The accumulators are registers for processing bytes, words or double words. The address identifiers are loaded into the accumulators, where they are logically gated. The result of the logic Instr. (RLO) is in ACCU1 and can be transferred from there to a memory cell. The accumulators are 32 bits long.

Accumulator designations:

ACCU Bit

ACCUx (x = 1 to 4) Bit 0 to 31

ACCUx-L Bit 0 to 15

ACCUx-H Bit 16 to 31

ACCUx-LL Bit 0 to 7

ACCUx-LH Bit 8 to 15

ACCUx-HL Bit 16 to 23

ACCUx-HH Bit 24 to 31

Registers

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 12

Adress Registers AR1 and AR2 (32 Bit) The address registers contain the area-internal or area-crossing pointers for instructions using indirect addressing. The address registers are 32 bits long. Die The area-internal and/or area-crossing pointers have the following syntax:

Area-internal pointer: 00000000 00000bbb bbbbbbbb bbbbbxxx

Area-crossing pointer: yyyyyyyy 00000bbb bbbbbbbb bbbbbxxx

Legend: b Byte address x Bit number y Area identifier (see “Examples of Addressing”)

Status word (16 Bits) The status word bits are evaluated or set by the instructions.

The status word is 16 bits long.

Bit Assignment Description

0 /FC First check bit

1 RLO Result of logic Instr.

2 STA Status

3 OR Or (AND before OR)

4 OS Stored overflow

5 OV Overflow

6 CC 0 Condition code 0

7 CC 1 Condition code 1

8 BR Binary result

9 to 15 Unassigned -

Examples of Addressing

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 13

Examples of Addressing

Addressing Examples Description

Immediate Addressing

L +27 Load 16-bit integer constant “27” into ACCU1 L L#-1 Load 32-bit integer constant “-1” into ACCU1

L 2#1010101010101010 Load binary constant into ACCU1 L DW#16#A0F0BCFD Load hexadecimal constant into ACCU1 L ’ENDE’ Load ASCII character into ACCU1

L T#500 ms Load time value into ACCU1 L C#100 Load count value into ACCU1 L B#(100,12) Load 2-byte constant

L B#(100,12,50,8) Load 4-byte constant L P#10.0 Load area-internal pointer into ACCU1 L P#E20.6 Load area-crossing pointer into ACCU1

L -2.5 Load real number into ACCU1 L D# 1995-01-20 Load date L TOD 13:20:33.125 Load time of day

Direct Addressing1

A I 0.0 ANDing of input bit 0.0 L IB 1 Load input byte 1 into ACCU1 L IW 0 Load input word 0 into ACCU1 L ID 0 Load input double word 0 into ACCU1

Indirect Addressing of Timers/Counters

SP T [LW 8] Start timer; the timer number is in local data word 8 CU C [LW 10] Count upwards; the counter number is in local data word 10

Examples of Addressing

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 14

Addressing Examples Description

Area-Internal Memory-Indirect Addressing

A I [LD 12] Example: L P#22.2 T LD 12 A I [LD 12]

AND Instr.: The address of the input is in local data double word 12 as pointer

A I [DBD 1] AND Instr.: The address of the input is in data double word 1 of the open DB as pointer

A Q [DID 12] AND Instr.: The address of the output is in data double word 12 of the open instance DB as pointer A Q [MD 12] AND Instr.: The address of the output is in memory double word 12 as pointer

Area-Internal Register-Indirect Addressing

A I [AR1,P#12.2] AND Instr.: The address of the input is calculated from the “pointer value in AR 1 + P#12.2”

Area-Internal Register-Indirect Addressing

For area-crossing register-indirect addressing, the address must also contain an area identifier. The address is in the address register. The area identifiers are as follows: Area identifier Coding (binary) hex. Area P 1000 0000 80 I/O area I 1000 0001 81 Input area Q 1000 0010 82 Output area M 1000 0011 83 Bit memory area DB 1000 0100 84 Data area DI 1000 0101 85 Instance data area L 1000 0110 86 Local data area VL 1000 0111 87 Predecessor local data area (access to local data of invoking block)

L B [AR1,P#8.0] Load byte into ACCU1: The address is calculated from the “pointer value in AR 1 + P#8.0” A [AR1,P#32.3] AND Instr.: The address of the operand is calculated from the “pointer value in AR 1 + P#32.3”

Addressing Via Parameters

A Parameter Addressing via parameters

Examples of how to calculate the pointer

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 15

Examples of how to calculate the pointer Example for sum of bit addresses ≤7:

LAR1 P#8.2

U E [AR1,P#10.2]

Result: Input 18.4 is addressed (by adding the byte and bit addresses)

Example for sum of bit addresses >7:

L P#10.5

LAR1

U E [AR1,P#10.7]

Result: Input 21.4 is addressed (by adding the byte and bit addresses with carry over)

Execution Times with Indirect Addressing

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 16

Execution Times with Indirect Addressing When using indirect addresses statement consists of two parts:

Part 1: Load the address of the instruction

Part 2: Execute the instruction

In other words, when working with indirect addresses, you must calculate the execution time of an instruction from these two parts.

Calculating the Execution Time The total execution time is calculated as follows:

Time required for loading the address

+ execution time of the instruction

= Total execution time of the instruction

The execution times listed in the chapter entitled “List of Instructions” apply to the execution times of the second part of an instruction, i.e. for the actual execution of an instruction.

You must then add the time required for loading the address of the instruction to this execution time (see following Table).

Execution Times with Indirect Addressing

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 17

The execution time for loading the address of the instruction from the various areas is shown in the following table.

Execution Time in ns Address is in ... CPU 412 CPU 414 CPU 416

Bit memory area M Word Double word

150 150

90 90

60 60

Data block DB/DX Word Double word

175 175

105 105

70 70

Local data area L Word Double word

150 150

90 90

60 60

AR1/AR2 (area-internal) 0 1) 0 1) 0 1)

AR1/AR2 (area-crossing) 0 1) 0 1) 0 1)

Parameter (word) ... for: Timers Counters Block calls

175 175 175

105 105 105

70 70 70

Parameter (double word) ... for Bits, bytes, words and double words

175

105

70

The pages that follow contain examples for calculating the instruction run time for the various indirectly addressed instructions.

1) Address registers AR1/AR2 do not need to be loaded in separate cycles for addressing.

Examples of Calculations

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 18

Examples of Calculations You will find a few examples here for calculating the execution times for the various methods of indirect addressing.

Calculating the Execution Times for Area-Internal Memory-Indirect Addressing

Example: A I [DBD 12] with CPU 414

Step 1: Load the contents of DBD 12 (time required is listed in the table on page 16)

Address is in ... Execution Time in ns

Bit memory area M Word Double word

90 90

Data block DB/DX Word Double word

105

105

Step 2: AND the input addressed in this way (you will find the execution time in the tables in the chapter entitled “List of Instructions” on page 21)

Typical Execution Time in ns

Direct Addressing indirecte Adressing

45 :

45+:

Time for A I

Total execution time

105 ns

+ 45 ns

150 ns

Examples of Calculations

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 19

Execution Time for Area-Crossing Register-Indirect Addressing

Example: U [AR1, P#23.1] ... with I 1.0 in AR1 with CPU 416

1. Step: Load the contents of AR1, and increment them by the offset 23.1 (the time required is in the table on page 16)

Address is in ... Execution Time in ns

: :

AR1/AR2 (Area-crossing ) 0

: :

2. Step: AND link of the input addressed this way (see page 21 for the execution time 24)

Execution Time in ns

Direct Addressing Indirect Addressing

30 :

30+:

Time for A I

Total execution time 0 ns + 30 ns 30 ns

List of Instructions Bit Logic Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 20

List of Instructions

This chapter contains the complete list of instructions for the S7-400 CPUs. The descriptions have been kept as concise as possible. You will find a detailed functional description in the various STEP 7 reference manuals.

Please note that, in the case of indirect addressing (examples see page Fehler! Textmarke nicht definiert.), you must add the time required for loading the address of the particular instruction to the execution times listed (see page 17).

List of Instructions Bit Logic Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 21

Bit Logic Instructions

All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state scanned. The subsequent logic instructions generate the new RLO from the signal state scanned and the old RLO. The logic string ends with an instruction which limits the RLO (e.g. a memory instruction); that is, the /FC bit is set to zero

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

A/AN I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter

Input/output Bit memory Local data bit Data bit Instanz Data bit Memory-indirect, area-internal 1)

Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR2) 1) Area-crossing (AR1) 1) Area-crossing (AR2) 1) Via parameter 1)

1 2) /2 1 3) /2

2 2 2 2 2 2 2 2 2

75 75 75

100 100

75/100 75/100 75/100 75/100 75/100 75/100

45 45 45 60 60

45/60 45/60 45/60 45/60 45/60 45/60

30 30 30 40 40

30/40 30/40 30/40 30/40 30/40 30/40

Status word for: A, AN, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - Yes - Yes Yes

Instruction affects: - - - - - Yes Yes Yes 1

1 I, Q, M, L, DB, DI 2 With direct instruction addressing; Address area 0 to 127 3 With direct instruction addressing; Address area 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Bit Logic Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 22

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

O/ON I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter

OR/OR-NOT Input/output Bit memory Local data bit Data bit Instanz data bit Memory-indirect, area-internal 1) Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR2) 1) Area-crossing (AR1) 1) Area-crossing (AR2) 1) Via parameter 1)

1 2)/2 1 3)/2

2 2 2 2 2 2 2 2 2

75 75 75

100 100

75/100

75/100

75/100

75/100

75/100

75/100

45 45 45 60 60

45/60

45/60

45/60

45/60

45/60

45/60

30 30 30 40 40

30/40

30/40

30/40

30/40

30/40

30/40

Status word for: O, ON, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes Yes

Instruction affects: - - - - - 0 Yes Yes 1

1) I, Q, M, L, DB, DI 2) With direct instruction addressing;Address area 0 to 127 3) With direct instruction addressing;Address area 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Bit Logic Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 23

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

X/XN I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter

EXKLUSIV-OR/ EXKLUSIV-OR-NOT Input/output Bit memory Local data bit Data bit Instanz Data bit Memory-indirect, area-internal. 1) Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR2) 1) Area-crossing (AR1) 1) Area-crossing (AR2) 1) Via parameter 1)

2 2 2 2 2 2 2 2 2 2 2

75 75 75

100 100

75/100

75/100

75/100

75/100

75/100

75/100

45 45 45 60 60

45/60

45/60

45/60

45/60

45/60

45/60

30 30 30 40 40

30/40

30/40

30/40

30/40

30/40

30/40

Status word for: X, XN, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes Yes

Instruction affects: - - - - - 0 Yes Yes 1

1) I, Q, M, L, DB, DI Plus time required for loading the address of the instruction (see page 17)

List of Instructions Bit Logic Instructions with Parenthetical Expressions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 24

Bit Logic Instructions with Parenthetical Expressions

Saving the RLO and OR bits and the relevant function identifier (A, AN, ...) to the nesting stack. Seven nesting levels are possible per block. After the right parenthesis, the logic operation indicated by the function identifier is performed on the saved RLO and the current RLO; the current OR is overwritten with the saved OR.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

A( AND left parenthesis 1 75 45 30

AN( AND NOT left parenthesis 1 75 45 30

O( OR left parenthesis 1 75 45 30

ON( OR NOT left parenthesis 1 75 45 30

X( EXCLUSIVE OR left parenthesis 1 75 45 30

XN( EXCLUSIVE OR NOT left parenthesis 1 75 45 30

Status word for: A(, AN(, O(, ON(, X(, XN(, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - Yes - Yes Yes

Instruction affects: - - - - - 0 1 - 0

List of Instructions Bit Logic Instructions with Parenthetical Expressions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 25

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

) Right parenthesis, removing an entry from the nesting stack.

1 75 45 30

Status word for: ), BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: - - - - - Yes 1 Yes 1

List of Instructions ORing of AND Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 26

ORing of AND Instructions

The ORing of AND instructions is implemented according to the rule: AND before OR

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

O ORing of AND operations according to the rule: AND before OR

1 75 45 30

Status word for: O, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes Yes

Instruction affects: - - - - - Yes 1 - Yes

List of Instructions Logic Instructions with Timers and Counters

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 27

Logic Instructions with Timers and Counters

Examining the status of the addressed timer/counter and gating the result with the RLO according to the appropriate logic function.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

A/AN

T f T [e] C f C [e]

AND/AND NOT Timer Timer, memory-indirect addressing Counter Counter, memory-indirect addressing

11)/2

2 11)/2

2

75

75 75

75

45

45 45

45

30

30 30

30

Timerpara. Counter para.

Timer/counter (addressing via parameter) 2 75

75

45

45

30

30

Status word for: A, AN, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - Yes - Yes Yes

Instruction affects: - - - - - Yes Yes Yes 1

1 With direct instruction addressing;Address area 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Logic Instructions with Timers and Counters

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 28

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

O/ON

T f T [e] C f C [e]

Timer Timer, memory-indirect addr. Counter Counter, memory-indirect addressing

11)/2

2 11)/2

2

75

75 75

75

45

45 45

45

30

30 30

30

Timerpara. Counterpara.

Timer/counter (addressing via parameter) 2 75

75

45

45

30

30 X/XN

T f T [e] C f C [e]

EXCLUSIVE OR/EXCLUSIVE OR NOT Timer Timer, memory-indirect addr. Counter Counter, mem.-indirect addr.

2 2 2 2

75

75 75

75

45

45 45

45

30

30 30

30 Timerpara.

Counterpara. EXCLUSIVE OR timer/counter (addressing via parameter)

2 75

75

45

45

30

30

Status word for: O, ON, X, XN, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes Yes

Instruction affects: - - - - - 0 Yes Yes 1

1) With direct instruction addressing;Address area 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Word Logic Instructions with the Contents of Accumulator 1

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 29

Word Logic Instructions with the Contents of Accumulator 1

Gating the contents of ACCU1 and/or ACCU1-L with a word or double word according to the appropriate function. The word or double word is either specified in the instruction as an address or is in ACCU2. The result is in ACCU1 and/or ACCU1-L.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

AW AND ACCU2-L 1 75 45 30 AW W#16#p AND 16-bit constant 2 75 45 30 OW OR ACCU2-L 1 75 45 30 OW W#16#p OR 16-bit constant 2 75 45 30 XOW EXCLUSIVE OR ACCU2-L 1 75 45 30 XOW W#16#p EXCLUSIVE OR 16-bit constant 2 75 45 30

AD AND ACCU2 1 75 45 30

AD DW#16#p AND 32-bit constant 3 113 68 45

OD OR ACCU2 1 75 45 30

OD DW#16#p OR 32-bit constant 3 113 68 45

XOD EXCLUSIVE OR ACCU2 1 75 45 30

XOD DW#16#p EXCLUSIVE OR 32-bit constant 3 113 68 45

Status word for: AW, OW, XOW, AU, OD, XOD, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes 0 0 - - - - -

List of Instructions Evaluating Conditions Using AND, OR and EXCLUSIVE OR

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 30

Evaluating Conditions Using AND, OR and EXCLUSIVE OR

All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state scanned. The subsequent logic instructions generate the new RL from the signal state scanned and the old RLO. The logic string ends with an instruction which limits the RLO (e.g. a memory instruction); that is, the FC bit is set to zero.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

==0

AND/AND NOT OR/OR-NOT EXCLUSIVE OR/ EXCLUSIVE-OR-NOT Result=0 (CC1=0 and CC0=0)

1

75

45

30

>0 Result>0 (CC1=1 and CC0=0)

1 75 45 30

<0 Result<0 (CC1=0 and CC0=1)

1 75 45 30

<>0 Result≠0 ((CC1=0 and CC0=1) or (CC1=1 and CC0=0))

1 75 45 30

<=0 Result<=0 ((CC1=0 and CC0=1) or (CC1=0 and CC0=0))

1 75 45 30

A/AN O/ON X/XN

>=0 Result>=0 ((CC1=1 and CC0=0) or (CC1=0 and CC0=0))

1 75 45 30

Status word for: A, AN, O, ON, X, XN, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - Yes Yes - - Yes - Yes Yes

Instruction affects: - - - - - Yes Yes Yes 1

List of Instructions Evaluating Conditions Using AND, OR and EXCLUSIVE OR

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 31

Execution Time in ns Instr. Address ID Description Length in Words CPU 412 CPU 414 CPU 416

UO

AND/AND-NOT OR/OR-NOT EXCLUSIVE-OR/ EXCLUSIVE-OR-NOT Unordered math instruction (CC1=1 and CC0=1)

1

75

45

30

OS AND OS=1 1 75 45 30 BR AND BR=1 1 75 45 30

A/AN O/ON X/XN

OV AND OV=1 1 75 45 30

Status word for: A, AN, O, ON, X, XN, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - Yes Yes - - Yes - Yes Yes

Instruction affects: - - - - - Yes Yes Yes 1

List of Instructions Edge-Triggered Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 32

Edge-Triggered Instructions

The current RLO is compared with the status of the instruction or “edge bit memory”. FP detects a change from “0” to “1”; FN detects a change from “1” to “0”.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

FP/FN I/Q a.b M a.b L a.b 1) DBX a.b DIX a.b c [d] 2) c [AR1,m] 2) c [AR2,m] 2) [AR1,m] 2) [AR2,m] 2) Parameter 2)

The positive/negative edge is indicated by RLO = 1. The bit addressed in the instruction is the auxiliary edge bit memory.

2 2 2 2 2 2 2 2 2 2 2

75 75 75

200 200

75/200

75/200

75/200

75/200

75/200

75/200

45 45 45

120 120

45/120

45/120

45/120

45/120

45/120

45/120

30 30 30 80 80

30/80

30/80

30/80

30/80

30/80

30/80 Status word for: FP, FN, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: - - - - - 0 Yes Yes 1

1 Unnecessary if the bit being monitored is in the process image (local data of a block are only valid while the block is running). 2 I, Q, M, L, DB, DI Plus time required for loading the address of the instruction (see page 17)

List of Instructions Setting/Resetting Bit Addresses

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 33

Setting/Resetting Bit Addresses

Assigning the value “1” or “0” to the addressed instruction when RLO = 1. The instructions can be dependent on the MCR (see page 86).

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

S R

I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter

Set addressed bit to “1” Set addressed bit to “0” Input/output Bit memory Local data bit Data bit Instanz Data bit Memory-indirect, area-internal 1) Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR2) 1) Area-crossing (AR1) 1) Area-crossing (AR2) 1) Via parameter 1)

12)/2 13)/2

2 2 2 2 2 2 2 2 2

75 75 75 200 200

75/200 75/200 75/200 75/200 75/200 75/200

45 45 45 120 120

45/120 45/120 45/120 45/120 45/120 45/120

30 30 30 80 80

30/80 30/80 30/80 30/80 30/80 30/80

Status word for: S, R, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes - Instruction affects: - - - - - 0 Yes - 0

1 I, Q, M, L, DB, DI 2 With direct instruction addressing; Address area 0 to 127 3 With direct instruction addressing; Address area 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Setting/Resetting Bit Addresses

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 34

The RLO is written to the address of the instruction. The instructions can be dependent on the MCR (see page 86).

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

= I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter

Assign RLO to Input/output to Bit memory to Local data bit to DData bit to Instanz Data bit Memory-indirect, area-internal 1) Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR2) 1) Area-crossing (AR1) 1) Area-crossing (AR2) 1) Via parameter 1)

12)2 13)/2

2 2 2 2 2 2 2 2 2

75 75 75 200 200

75/200

75/200

75/200

75/200

75/200

75/200

45 45 45 120 120

45/120

45/120

45/120

45/120

45/120

45/120

30 30 30 80 80

30/80

30/80

30/80

30/80

30/80

30/80

Status word for: =, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: - - - - - 0 Yes - 0

1 I, Q, M, L, DB, DI 2 With direct instruction addressing;Address area 0 to 127 3 With direct instruction addressing;Address area 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Instructions Directly Affecting the RLO

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 35

Instructions Directly Affecting the RLO

The following instructions have a direct effect on the RLO.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

CLR Set RLO to ”0” 1 75 45 30 Status word for: CLR, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - - 0 0 0 0 SET Set RLO to ”1” 1 75 45 30 Status word for: SET, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - - 0 1 1 0 NOT Negate RLO 1 75 45 30 Status word for: NOT, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - Yes - Yes -

Instruction affects: - - - - - - 1 Yes - SAVE Save RLO to the BR bit 1 75 45 30 Status word for: SAVE, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: Yes - - - - - - - -

List of Instructions Timer Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 36

Timer Instructions

Starting or resetting a timer. The time value must be in ACCU1-L. The instructions are triggered by an edge transition in the RLO; that is, when the status of the RLO has changed between two calls.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

T f T [e]

11)/2

150

150

90

90

60

60

SP

Timer para.

Start timer as pulse on edge change from “0” to “1”

2 150 90 60

T f T [e]

11)/2

150

150

90

90

60

60

SE

Timer para.

Start timer as extended pulse on edge change from “0” to “1”

2 150 90 60

T f T [e]

11)/2

150

150

90

90

60

60

SD

Timer para.

Start timer as ON delay on edge change from “0” to “1”

2 150 90 60

Status word for: SP, SE, SD, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: - - - - - 0 - - 0

1 With direct instruction addressing Timer-No.: 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Timer Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 37

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

T f T [e]

11)/2

150

150

90

90

60

60

SS

Timerpara.

Start timer as retentive ON delay on edge change from “0” to “1”

2 150 90 60

T f T [e]

11)/2

150

150

90

90

60

60

SF

Timerpara.

Start timer as OFF delay on edge change from “0” to “1”

2 150 90 60

T f T [e]

11)/2

150 150+

90 90Fehler! Textmarke

nicht definiert.

60 60Fehler! Textmarke

nicht definiert.

FR

Timer para.

Enable timer for restarting on edge change from “0” to “1” (reset edge bit memory for starting timer)

2 150Fehler! Textmarke

nicht definiert. 90Fehler! Textmarke

nicht definiert. 60Fehler! Textmarke

nicht definiert.

T f T [e]

1Fehler! Textmarke

nicht definiert.)/2 150

150Fehler! Textmarke

nicht definiert.

90 90Fehler! Textmarke

nicht definiert.

60 60Fehler! Textmarke

nicht definiert.

R

Timer para.

Reset timer

2 150Fehler! Textmarke

nicht definiert. 90Fehler! Textmarke

nicht definiert. 60Fehler! Textmarke

nicht definiert.

Status word for: SS, SF, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: - - - - - 0 - - 0

1 With direct instruction addressing Timer-No.: 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Timer Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 38

List of Instructions Counter Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 39

Counter Instructions

The count value must be in ACCU1-L in the form of a BCD number (0 - 999).

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

C f C [e]

Presetting of counter on edge change from “0” to “1”

11)/2 150

150

90

90

60

60

S

Counter para. 2 150 90 60

C f C [e]

Reset counter to “0” when RLO = “1”

11)/2 150

150

90

90

60

60

R

Counter para. 2 150 90 60

C f C [e]

Increment counter by 1 on edge change from “0” to “1”

11)/2 150

150

90

90

60

60

CU

Counter para. 2 150 90 60

Status word for: S, R, ZV, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: - - - - - 0 - - 0

1 With direct instruction addressing Counter-No.: 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Counter Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 40

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

C f C [e]

Decrement counter by 1 on edge change from “0” to “1”

11)/2 150

150

90

90

60

60

CD

Counter para. 2 150 90 60

C f C [e]

Enable counter on edge change from “0” to “1” (reset edge bit memory for up and down counting and setting the counter)

11)/2

150

150

90

90

60

60

FR

Counter para. 2 150 90 60

Status word for: ZR, FR, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: - - - - - 0 - - 0

1 With direct instruction addressing Counter-No.: 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Load Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 41

Load Instructions

Loading address identifiers into ACCU1. The contents of ACCU1 are first saved to ACCU2. The status word is not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

IB a QB a PIB a

Load ... Input byte Output byte Peripheral input byte 1)

12)/2 12)/2 12)/2

75 75 75

45 45 45

30 30 30

MB a LB a

Bit memorybyte Local data byte

13)/2 2

75 75

45 45

30 30

DBB a DIB a

Data byte Instance data byte ... into ACCU1

2 2

100 100

60 60

40 40

L

g [d] g [AR1,m] g [AR2,m] B[AR1,m] B[AR2,m] Parameter

Memory-indirect, area-internal. 4) Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR2) 4) Area-crossing (AR1) 4) Area-crossing (AR2) 4) Via parameter 4)

2 2 2 2 2 2

75/100

75/100

75/100

75/100

75/100

75/100

45/60

45/60

45/60

45/60

45/60

45/60

30/40

30/40

30/40

30/40

30/40

30/40

1 With indirect instruction addressing; Address area 0 to 127 2 plus reaction time of the I/O module (> 1 µs) 3 With direct instruction addressing; Address area 0 to 255 4 I, Q, P, M, L, DB, DI Plus time required for loading the address of the instruction (see page 17)

List of Instructions Load Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 42

If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this page are doubled.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

IW a QW PIW a

Load ... Input byte Output byte Peripheral input byte 1)

12)/2 12)/2 12)/2

75 75 75

45 45 45

30 30 30

MW a LW a

Bit memory byte Local data byte

13)/2 2

75 75

45 45

30 30

DBW a DIW a

Data byte Instance data byte ... into ACCU1-L

2 2

100 100

60 60

40 40

L

h [d] h [AR1,m] h [AR2,m] W[AR1,m] W[AR2,m] Parameter

Memory-indirect, area-internal 4) Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR2) 4) Area-crossing (AR1) 4) Area-crossing (AR2) 4) Via parameter 4)

2 2 2 2 2 2

75/100

75/100

75/100

75/100

75/100

75/100

45/60

45/60

45/60

45/60

45/60

45/60

30/40

30/40

30/40

30/40

30/40

30/40

1 plus reaction time of the I/O module (> 1 µs) 2 With indirect instruction addressing; Address area 0 to 127 3 With direct instruction addressing; Address area 0 to 255 4 I, Q, P, M, L, DB, DI Plus time required for loading the address of the instruction (see page 17)

List of Instructions Load Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 43

The used address is divisible by 4without a remainder, the execution times for instructions specified on this page is doubled.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

ID a QD a PID a

Load ... Input double word Output double word Peripheral-Input double word 1)

12)/2 12)/2

2

75 75 75

45 45 45

30 30 30

MD a LD a

Bit memory double word Lokaldaten double word

13)/2 2

75 75

45 45

30 30

DBD a DID a

Data double word Instance data double word ... into ACCU1

2 2

100 100

60 60

40 40

L

i [d] i [AR1,m] i [AR2,m] D[AR1,m] D[AR2,m] Parameter

Memory-indirect, area-internal 4) Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR2) 4) Area-crossing (AR1) 4) Area-crossing (AR2) 4) Via parameter 4)

2 2 2 2 2 2

75/100

75/100

75/100

75/100

75/100

75/100

45/60

45/60

45/60

45/60

45/60

45/60

30/40

30/40

30/40

30/40

30/40

30/40

1 plus reaction time of the I/O module (> 1 µs) 2 With indirect instruction addressing; Address area 0 to 127 3 With direct instruction addressing;Address area 0 to 255 4 I, Q, P, M, L, DB, DI Plus time required for loading the address of the instruction (see page 17)

List of Instructions Load Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 44

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

k8 k16 k32

Load ... 8-bit constant into ACCU 1-LL 16-bit constant into ACCU 1-L 32-bit constant into ACCU 1

2 2 3

75 75

113

45 45 68

30 30 45

L

Parameter Load constant into ACCU1 (addressed via parameter)

2 100 60 40

2#n Load 16-bit binary constant into ACCU1-L 2 75 45 30

Load 32-bit binary constant into ACCU1 3 113 68 45

L

B#16#p Load 8-bit-hexadecimal constant into ACCU1-L 1 75 45 30 W#16#p

Load 16-bit hexadecimal constant into ACCU1-L 2 75 45 30 L

DW#16#p Load 32-bit hexadecimal constant into ACCU1 3 113 68 45

Plus time required for loading the address of the instruction (see page 17)

List of Instructions Load Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 45

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

’x’ Load 1 character 2 75 45 30 ’xx’ Load 2 characters 2 75 45 30 ’xxx’ Load 3 characters 3 113 68 45

L

’xxxx’ Load 4 characters 3 113 68 45

L D# time value Load IEC date 3 113 68 45 L S5T# time value Load S7 time constant (16 bits) 2 75 45 30 L TOD# time value Load IEC time constant 3 113 68 45

Load 16-bit time constant 2 75 45 30 L T# time value Load 32-bit time constant 3 113 68 45

L C# Count value Load counter constant (BCD code) 2 75 45 30

B# (b1, b2) Load constant as byte (b1, b2) 2 75 45 30 L B# (b1, b2, b3, b4)

Load constant as 4 bytes (b1, b2, b3, b4) 3 113 68 45

L P# bit pointer Load bit pointer 3 113 68 45 L L# integer Load 32-bit integer constant 3 113 68 45 L Real number Load floating-point number 3 113 68 45

List of Instructions Load Instructions for Timers and Counters

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 46

Load Instructions for Timers and Counters Loading a time value or count value into ACCU1. The contents of ACCU1 are first saved to ACCU2. The bits of the status word are not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

T f T [e]

Load time value 11)/2 2

75

75

45

45

30

30

L

Timer para. Load time value (addressed via parameter) 2 75 45 30

Z f Z [e]

Load count value 11)/2 2

75

75

45

45

30

30

L

Counter para. Load count value (addressed via parameter) 2 75 45 30

T f T [e]

Load time value in BCD 11)/2 2

75

75

45

45

30

30

LC

Timer para. Load time value in BCD (addressed via parameter)

2 75 45 30

Z f Z [e]

Load count value in BCD 11)/2 2

75

75

45

45

30

30

LC

Counter para. Load count value in BCD (addressed via parameter)

2 75 45 30

1 With direct instruction addressing;Address area; Timer-/Counter-No.: 0 to 255 Plus time required for loading the address of the instruction (see page 17)

List of Instructions Transfer Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 47

Transfer Instructions

Transferring the contents of ACCU1 to the addressed operand. Note that some instructions are affected by the MCR (see page 85). The status word is not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

IB a QB a PQB a

Transfer contents of ACCU1-LL to ... input byte output byte peripheral output byte2)

11)/2 11)/2 11)/2

75 75 75

45 45 45

30 30 30

MB a LB a

bit memory byte local data byte

12)/2 2

75 75

45 45

30 30

DBB a DIB a

data byte instance data byte

2 2

100 100

60 60

40 40

T

g [d] g [AR1,m] g [AR2,m] B[AR1,m] B[AR2,m] Parameter

Memory-indirect, area internal 3) Register-ind., area-internal (AR1) 3) Register-ind., area-internal (AR2) 3) Area-crossing (AR1) 3) Area-crossing (AR2) 3) Via parameter 3)

2 2 2 2 2 2

75/100

75/100

75/100

75/100

75/100

75/100

45/60

45/60

45/60

45/60

45/60

45/60

30/40

30/40

30/40

30/40

30/40

30/40

1 With indirect instruction addressing; Address area 0 to 127 2 With direct instruction addressing; Address area 0 to 255 3 I, Q, P, M, L, DB, DI Plus time required for loading the address of the instruction (see page 17)

List of Instructions Transfer Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 48

If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this page are doubled.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

IW a QW a PQW a

Transfer contents of ACCU1-L to ... input word output word peripheral output word 1)

12)/2 12)/2 12)/2

75 75 75

45 45 45

30 30 30

MW a LW a

bit memory word Local data word

13)/2 2

75 75

45 45

30 30

DBW a DIW a

Data word Instance data word

2 2

100 100

60 60

40 40

T

h [d] h [AR1,m] h [AR2,m] W[AR1,m] W[AR2,m] Parameter

Memory-indirect, area internal 4) Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR2) 4) Area-crossing (AR1) 4) Area-crossing (AR2) 4) Via parameter 4)

2 2 2 2 2 2

75/100

75/100

75/100

75/100

75/100

75/100

45/60

45/60

45/60

45/60

45/60

45/60

30/40

30/40

30/40

30/40

30/40

30/40

1 I/O acknomledgement time has to be taken into account 2 With direct instruction addressing; Address area 0 to 127 3 With direct instruction addressing; Address area 0 to 255 4 I, Q, P, M, L, DB, DI Plus time required for loading the address of the instruction (see page 17)

List of Instructions Transfer Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 49

If the used address is divisible by 4 without a remainder, the execution times for instructions specified on this page is doubled.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

ID a QD a PQD a

Transfer contents of ACCU1 to ... Input double word Output double word periph. output double word 1)

12)/2 12)/2

2

75 75 75

45 45 45

30 30 30

MD a LD a

Bit memory double word Local data double word

13)/2 2

75 75

45 45

30 30

T

DBD a DID a

Data double word Instance data double word

2 2

100 100

60 60

40 40

T

i [d] i [AR1,m] i [AR2,m] D[AR1,m] D[AR2,m] Parameter

Memory-indirect, area internal 4) Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR2) 4) Area-crossing (AR1) 4) Area-crossing (AR2) 4) Via parameter 4)

2 2 2 2 2 2

75/100

75/100

75/100

75/100

75/100

75/100

45/60

45/60

45/60

45/60

45/60

45/60

30/40

30/40

30/40

30/40

30/40

30/40

1 I/O acknomledgement time has to be taken into account 2 With direct instruction addressing; Address area 0 to 127 3 With direct instruction addressing; Address area 0 to 255 4 I, Q, P, M, L, DB, DI Plus time required for loading the address of the instruction (see page 17)

List of Instructions Load and Transfer Instructions for Address Registers

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 50

Load and Transfer Instructions for Address Registers

Loading a double word from a memory area or register into address register 1 (AR1) or address register 2 (AR2). The status word is not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

LAR1

- AR2 DBD a DID a m LD a MD a

Load contents from ... ACCU1 Address register 2 Data double word Instance data double word 32-bit constant as pointer Local data double word Bit memory double word ... into AR1

1 1 2 2 3 2 2

150 150 175 175 150 150 150

90 90 105 105 90 90 90

60 60 70 70 60 60 60

LAR2

- DBD a DID a m LD a MD a

Load contents from ... ACCU1 Data double word Instance data double word 32-bit constant as pointer Local data double word Bit memory double word ... into AR2

1 2 2 3 2 2

150 175 175 150 150 150

90 105 105 90 90 90

60 70 70 60 60 60

List of Instructions Load and Transfer Instructions for Address Registers

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 51

Transferring a double word from address register 1 (AR1) or address register 2 (AR2) to a memory area or register. The contents of ACCU1 are first saved to ACCU2. The status word is not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

TAR1 - AR2 DBD a DID a LD a MD a

Transfer contents from AR1 in ... ACCU1 Address register 2 Data double word Instance data double word Local data double word Bit memory double word

1 1 2 2 2 2

75

150 100 100 75 75

45 90 60 60 45 45

30 60 40 40 30 30

TAR2 - DBD a DID a LD a MD a

Transfer contents from AR2 in ... ACCU1 Data double word Instance data double word Local data double word Bit memory double word

1 2 2 2 2

75

100 100 75 75

45 60 60 45 45

30 40 40 30 30

CAR Exchange the contents of AR1 and AR2 1 150 90 60

List of Instructions Load and Transfer Instructions for the Status Word

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 52

Load and Transfer Instructions for the Status Word

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

L STW Load status word into ACCU1 1 75 45 30

Status word for: L, STW, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: Yes Yes Yes Yes Yes Yes Yes Yes Yes

Instruction affects: - - - - - - - - -

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

T STW Transfer ACCU1 (bits 0 to 8) to the status word

1 75 45 30

Status word for: T, STW, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: Yes Yes Yes Yes Yes Yes Yes Yes Yes

List of Instructions Load Instructions for DB Number and DB Length

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 53

Load Instructions for DB Number and DB Length

Loading the number/length of a data block into ACCU1. The old contents of ACCU1 are saved to ACCU2. The status word is not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

L DBNO Load number of data block 1 75 45 30 L DINO Load number of instance data block 1 75 45 30 L DBLG Load length of data block into byte 1 75 45 30

L DILG Load length of instance data block into byte 1 75 45 30

List of Instructions Integer Math (16 Bits)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 54

Integer Math (16 Bits)

Math instructions on two 16-bit words. The result is written to ACCU1 and/or ACCU1-L. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

+I Add 2 integers (16 bits) (ACCU1-L)=(ACCU1-L)+(ACCU2-L)

1 75 45 30

-I Subtract 1 integer from another (16 bits) (ACCU1-L)=(ACCU2-L)-(ACCU1-L)

1 75 45 30

*I Multiply 1 integer by another (16 bits) (ACCU1)=(ACCU2-L)*(ACCU1-L)

1 75 45 30

/I Divide 1 integer by another (16 bits) (ACCU1-L)=(ACCU2-L):(ACCU1-L) The remainder is in ACCU1-H

1 300 180 120

Status word for: +I, -I, *I, /I, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes Yes Yes Yes - - - -

List of Instructions Integer Math (32 Bits)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 55

Integer Math (32 Bits)

Math instructions on two 32-bit words. The result is written to ACCU1. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

+D Add 2 integers (32-bit) (ACCU1)=(ACCU2)+(ACCU1)

1 75 45 30

-D Subtract 2 integer from another (32 bits) (ACCU1)=(ACCU2)-(ACCU1)

1 75 45 30

*D Multiply 2 integer by another (32 bits) (ACCU1)=(ACCU2)*(ACCU1)

1 75 45 30

/D Divide 2 integer by another (32 bits) (ACCU1)=(ACCU2):(ACCU1)

1 450 270 180

MOD Divide 2 integer by another (32 bits) and load the remainder into ACCU1: (ACCU1)=remainder of [(ACCU2):(ACCU1)]

1 450 270 180

Status word for: +D, -D, *D, /D, MOD BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes Yes Yes Yes - - - -

List of Instructions Floating-Point Math (32 Bits)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 56

Floating-Point Math (32 Bits)

The result of the math instruction is in ACCU1. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

+R Add 2 real numbers (32 bits) (ACCU1)=(ACCU2)+(ACCU1)

1 150 90 60

-R Subtract 1 real number from another (32 bits) (ACCU1)=(ACCU2)-(ACCU1)

1 150 90 60

*R Multiply 1 real number by another (32 bits) (ACCU1)=(ACCU2)*(ACCU1)

1 150 90 60

/R Divide 1 real number by another (32 bits) (ACCU1)=(ACCU2):(ACCU1)

1 450 270 180

Status word for: +R, -R, *R, /R, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes Yes Yes Yes - - - -

List of Instructions Floating-Point Math (32 Bits)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 57

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

NEGR Negate the real number in ACCU1 1 75 45 30 ABS Form the absolute value of the real number

in ACCU1 1 75 45 30

Status word for: NEGR, ABS, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - - - - - -

List of Instructions Square Root and Square Instructions (32 Bits)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 58

Square Root and Square Instructions (32 Bits)

The result of the instruction is in ACCU1. The SQRT instruction can be interrupted.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

SQRT Calculate the square root of a real number in ACCU1

1 600 360 240

SQR Form the square of the real number in ACCU1

1 150 90 60

Status word for: SQRT, SQR, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes Yes Yes Yes - - - -

List of Instructions Logarithmic Function (32 Bits)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 59

Logarithmic Function (32 Bits)

The result of the logarithmic function is in ACCU1. The instructions can be interrupted.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

LN Form the natural logarithm of a real number in ACCU1

1 1575 945 630

EXP Calculate the exponential value of a real number in ACCU1 to the base e (= 2.71828)

1 2400 1440 960

Status word for: LN, EXP, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes Yes Yes Yes - - - -

List of Instructions Trigonometrical Functions (32 Bits)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 60

Trigonometrical Functions (32 Bits)

The result of the instruction is in ACCU1. The instructions can be interrupted.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

SIN Calculate the sine of a real number 1 1500 900 600 ASIN Calculate the arcsine of a real number 1 4875 2925 1950 COS Calculate the cosine of a real number 1 1500 900 600 ACOS Calculate the arccosine of a real number 1 4950 2970 1980

TAN Calculate the tangent of a real number 1 2400 1440 960 ATAN Calculate the arctangent of a real number 1 1425 855 570

SIN, ASIN, COS, Status word for:

ACOS, TAN, ATAN,

BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes Yes Yes Yes - - - -

List of Instructions Adding Constants

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 61

Adding Constants

Adding integer constants and storing the result in ACCU1. The status word is not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

+ i8 Add an 8-bit integer constant 1 75 45 30 + i16 Add a 16-bit integer constant 2 75 45 30 + i32 Add a 32-bit integer constant 3 113 68 45

List of Instructions Adding Using Address Registers

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 62

Adding Using Address Registers

Adding a 16-bit integer to the contents of the address register. The value is either specified as an address in the instruction or is in ACCU1-L. The status word is not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

+AR1 Add the contents of ACCU1-L to those of AR1 1 150 90 60 +AR1 m

(0 to 4095) Add a pointer constant to the contents of AR1 2 150 90 60

+AR2 Add the contents of ACCU1-L to those of AR2 1 150 90 60 +AR2 m

(0 to 4095) Add pointer constant to the contents of AR2 2 150 90 60

List of Instructions Comparison Instructions (16-Bit Integers)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 63

Comparison Instructions (16-Bit Integers)

Comparing the 16-bit integers in ACCU1-L and ACCU2-L. RLO = 1 if the condition is satisfied.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

==I ACCU2-L=ACCU1-L 1 75 45 30

<>I ACCU2-L≠ACCU1-L 1 75 45 30

<I ACCU2-L<ACCU1-L 1 75 45 30

<=I ACCU2-L<=ACCU1-L 1 75 45 30

>I ACCU2-L>ACCU1-L 1 75 45 30

>=I ACCU2-L>=ACCU1-L 1 75 45 30

Status word for: ==I, < >I, <I, <=I, >I, >=I, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes Yes 0 - 0 Yes Yes 1

List of Instructions Comparison Instructions (32-Bit Integers)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 64

Comparison Instructions (32-Bit Integers)

Comparing the 32-bit integers in ACCU1 and ACCU2. RLO = 1 if the condition is satisfied.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

==D ACCU2=ACCU1 1 75 45 30

<>D ACCU2≠ACCU1 1 75 45 30

<D ACCU2<ACCU1 1 75 45 30

<=D ACCU2<=ACCU1 1 75 45 30

>D ACCU2>ACCU1 1 75 45 30

>=D ACCU2>=ACCU1 1 75 45 30

Status word for: ==D, < >D, <D, <=D, >D, >=D, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes Yes 0 - 0 Yes Yes 1

List of Instructions Comparison Instructions (32-Bit Real Numbers)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 65

Comparison Instructions (32-Bit Real Numbers)

Comparing the 32-bit real numbers in ACCU1 and ACCU2.

RLO = 1 if the condition is satisfied.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

==R ACCU2=ACCU1 1 75 45 30 <>R ACCU2≠ACCU1 1 75 45 30 <R ACCU2<ACCU1 1 75 45 30 <=R ACCU2<=ACCU1 1 75 45 30

>R ACCU2>ACCU1 1 75 45 30 >=R ACCU2>=ACCU1 1 75 45 30

Status word for: ==R, < >R, <R, <=R, >R, >=R, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes Yes Yes Yes 0 Yes Yes 1

List of Instructions Shift Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 66

Shift Instructions

Shifting the contents of ACCU1 and ACCU1-L to the left or right by the specified number of places. If no address identifier is specified,

the contents of ACCU2-LL are used as the number of places. The last bit shifted is loaded into condition code bit CC 1.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

SLW 1) Shift the contents of ACCU1-L to the left. Positions that become free are provided with zeros.

1 75

45

30

SLW 0 ... 15 SLD Shift the contents of ACCU1 to the left.

Positions that become free are provided with zeros.

1 75

45

30

SLD 0 ... 32 SRW 1) Shift the contents of ACCU1-L to the right.

Positions that become free are provided with zeros.

1 75

45

30

SRW 0 ... 15

Status word for: SLW, SLD, SRW, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes 0 0 - - - - -

1 No. of places shifted: 0 to 16

List of Instructions Shift Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 67

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

SRD Shift the contents of ACCU1 to the right. Positions that become free are provided with zeros.

1 75

45

30

SRD 0 ... 32 SSI 1) Shift the contents of ACCU1-L with sign to

the right. Positions that become free are provided with with the sign (bit 15).

1 75

45

30

SSI 0 ... 15 SSD Shift the contents of ACCU1 with sign to the

right. Positions that become free are provided with with the sign (bit 31).

1 75

45

30

SSD 0 ... 32

Status word for: SRD, SSI, SSD, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes 0 0 - - - - -

1 No. of places shifted: 0 to 16

List of Instructions Rotate Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 68

Rotate Instructions

Rotate the contents of ACCU1 to the left or right by the specified number of places. If no address identifier is specified, the contents of

ACCU2-LL are used as the number of places. The last bit shifted is loaded into condition code bit CC1.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

RLD 1 75

45

30

RLD 0 ... 32

Rotate the contents of ACCU1 to the left

RRD 1 75

45

30

RRD 0 ... 32

Rotate the contents of ACCU1 to the right

RLDA Rotate the contents of ACCU1 one bit

position to the left through condition code bit CC 1

1 75 45 30

RRDA Rotate the contents of ACCU1 one bit position to the right through condition code bit CC 1

1 75 45 30

Status word for: RLD, RRD, RLDA, RRDA, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes 0 0 - - - - -

List of Instructions Accumulator Transfer Instructions, Incrementing and Decrementing

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 69

Accumulator Transfer Instructions, Incrementing and Decrementing

The status word is not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

CAW Reverse the order of the bytes in ACCU1-L. 1 75 45 30 CAD Reverse the order of the bytes in ACCU1. 1 75 45 30 TAK Swap the contents of ACCU1 and ACCU2 1 75 45 30 ENT The contents of ACCU2 and ACCU3 are

transferred to ACCU3 and ACCU4. 1 75 45 30

LEAVE The contents of ACCU3 and ACCU4 are transferred to ACCU2 and ACCU3.

1 75 45 30

PUSH The contents of ACCU1, ACCU2 and ACCU3 are transferred to ACCU2, ACCU3 and ACCU4

1 75 45 30

POP The contents of ACCU2, ACCU3 and ACCU4 are transferred to ACCU1, ACCU2 and ACCU3

1 75 45 30

INC k8 Increment ACCU1-LL 1 75 45 30 DEC k8 Decrement ACCU1-LL 1 75 45 30

List of Instructions Program Display and Null Operation Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 70

Program Display and Null Operation Instructions

The status word is not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

BLD k8 Program display instruction: Is treated by the CPU as a null operation instruction.

1 38 23 15

NOP 0 1

Null operation instruction 1

38

23

15

List of Instructions Data Type Conversion Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 71

Data Type Conversion Instructions

The results of the conversion are in ACCU1.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

BTI Convert contents of ACCU1-L from BCD (0 to +/- 999) to integer (16 bits) (BCD To Int)

1 75 45 30

BTD Convert contents of ACCU1 from BCD (0 to +/-9 999 999) to double integer (32 bits) (BCD To Doubleint)

1 75 45 30

DTR Convert contents of ACCU1 from double integer (32 bits) to real number (32 bits) (Doubleint To Real)

1 150 90 60

ITD Convert contents of ACCU1 from integer (16 bits) to double integer (32 bits) (Int To Doubleint)

1 75 45 30

Status word for: BTI, BTD, DTR, ITD, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - - - - - -

List of Instructions Data Type Conversion Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 72

Execution Time in ns Instr. Address ID

Description Length in

Words CPU 412 CPU 414 CPU 416

ITB Convert contents of ACCU1-L from integer (16 bits) to BCD from 0 to+/- 999 (Int To BCD)

1 75 45 30

DTB Convert contents of ACCU1 from double integer (32 bits) to BCD from 0 to +/- 9 999 999 (Doubleint To BCD)

1 75 45 30

Status word for: ITB, DTB, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - Yes Yes - - - -

List of Instructions Data Type Conversion Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 73

The real number to be converted is in ACCU1.

Execution Time in ns Instr. Address ID

Description Length in

Words CPU 412 CPU 414 CPU 416

RND Convert a real number into a 32-bit integer. 1 75 45 30 RND- Convert a real number into a 32-bit integer. The

number is rounded down to the next whole number.

1 75 45 30

RND+ Convert a real number into a 32-bit integer. The number is rounded up to the next whole number.

1 75 45 30

TRUNC Convert a real number into a 32-bit integer. The places after the decimal point are truncated.

1 75 45 30

Status word for: RND, RND- RND+ TRUNC, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - Yes Yes - - - -

List of Instructions Forming the Ones and Twos Complements

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 74

Forming the Ones and Twos Complements

Execution Time in ns Instr. Address ID

Description Length in

Words CPU 412 CPU 414 CPU 416

INVI Form the ones complement of ACCU1-L 1 75 45 30 INVD Form the ones complement of ACCU1 1 75 45 30

Status word for: INVI, INVD BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - - - - - -

NEGI Form the twos complement of ACCU1-L (integer)

1 75 45 30

NEGD Form the twos complement of ACCU1 (double integer)

1 75 45 30

Status word for: NEGI, NEGD, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - Yes Yes Yes Yes - - - -

List of Instructions Block Call Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 75

Block Call Instructions

The runtimes of the System Functions are specified in the chapter entitled “System Functions” as of page 93.

The information on the status word only relates to the block call itself and not to the commands called in this block.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

CALL FB q, DB q Unconditional call of an FB, with parameter transfer

15/171) 2425 2) 1455 2) 880 2)

CALL SFB q, DB q Unconditional call of an SFB, with parameter transfer

16/17 1) 2425 2) 1455 2) 880 2)

CALL FC q Unconditional call of a function, with parameter transfer

7/8 1) 2100 2) 1260 2) 760 2)

CALL SFC q Unconditional call of an SFC, with parameter transfer

8 2100 2) 1260 2) 760 2)

Status word for: CALL, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - 0 0 1 - 0

1 The instruction length depends on the block number from (0...255 or more). 2 Plus time required for supplying parameters

List of Instructions Block Call Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 76

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

UC FB q FC q FB [e] FC [e] Parameter

Unconditional call of blocks, without parameter transfer Memory-indirect FB call Memory-indirect FC call FB/FC call via parameter

11)/2

2 2 2

1450 1450

1450 )

1450 )

1450

870 870

870

870

870

490 490

490

490

490

CC FB q FC q FB [e] FC [e] Parameter

Conditional call of blocks, without parameter transfer Memory-indirect FB call Memory-indirect FC call FB/FC call via parameter

1 1)/2

2 2 2

1600/325 2) 1600/325 2)

1600 /325 2)

1600 /325 2)

1600 /325 2)

960/195 960/195

960 /195 2)

960 /195 2)

960 /195 2)

550/130 550/130)

550 /130 2)

550 /130 2)

550 /130 2)

Status word for: UC, CC, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - 3) -

Instruction affects: - - - - 0 0 1 - 3) 0

1 With direct instruction (DB) addressing; Block No. 0 to 255 Plus time required for loading the address of the instruction (see page 17) 2 If call is not executed 3 Instruction CC: Depending on RLO, sets RLO = 1

List of Instructions Block Call Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 77

Execution Time in ns

CPU 412 CPU 414 CPU 416

Instr. Address ID

Description Length

in Words

1. Open 2. - n. Open 1)

1. Open 2. - n. Open 1)

1. Open 2. - n. Open 1)

Select a data block

DB q DI q

Direct data block, DB Direct instance DB

12)/2 300 75 180 45 120 30

DB [e] DI [e]

Data block, indirect save Bit memory area M Local data area L Data block DB/DI

2 450 450 475

225 225 250

270 270 295

135 135 150

180 180 190

90 90

100

OPN

Param. Data block via parameters

2 475 250 295 150 190 100

Status word for: OPN, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - - - - - -

1 if the same DB or DI is already selected 2 Direct data block, DB no. 1 to 255

List of Instructions Block End Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 78

Block End Instructions

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

BE End block 1 1750 1050 700 BEU End block unconditionally 1 1750 1050 700

Status word for: BE, BEU, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - 0 0 1 - 0

BEC End block conditionally if RLO = “1” 1900/325 1) 1140/195 1) 760/130 1)

Status word for: BEC, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: - - - - Yes 0 1 1 0

1 If jump is not executed

List of Instructions Exchanging Shared Data Block and Instance Data Block

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 79

Exchanging Shared Data Block and Instance Data Block

Exchanging the two current data blocks. The current shared data block becomes the current instance data block, and vice versa. The status word is not affected.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

CDB Exchange shared data block and instance data block

1 150 90 60

List of Instructions Jump Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 80

Jump Instructions

Jumping as a function of conditions.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416 JU LABEL Jump unconditionally 2 500 300 210

Status word for: JU, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - - - - - -

JC LABEL Jump if RLO = “1” 2 500/75 1) 300/45 1) 210/30 1) JCN LABEL Jump if RLO = “0” 2 500/75 1) 300/45 1) 210/30 1)

Status word for: JC, JCN, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: - - - - - 0 1 1 0

1 If jump is not executed

List of Instructions Jump Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 81

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

JCB LABEL Jump if RLO = “1”. Save the RLO in the BR bit

2 500/75 1) 300/45 1) 210/30 1)

JNB LABEL Jump if RLO = “0”. Save the RLO in the BR bit

2 500/75 1) 300/45 1) 210/30 1)

Status word for: JCB, JNB, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: Yes - - - - 0 1 1 0

JBI LABEL Jump if BR = “1” 2 500/75 1) 300/45 1) 210/30 1)

JNBI LABEL Jump if BR = “0” 2 500/75 1) 300/45 1) 210/30 1)

Status word for: JBI, JNBI, BR CC

1 CC0

OV OS OR STA RLO /FC

Instruction depends on: Yes - - - - - - - -

Instruction affects: - - - - - 0 1 - 0

1 If jump is not executed

List of Instructions Jump Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 82

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416 JO LABEL Jump on stored overflow (OV = “1”) 2 500/75 1) 300/45 1) 210/30 1)

Status word for: JO, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - Yes - - - - -

Instruction affects: - - - - - - - - -

JOS LABEL Jump on stored overflow (OS = “1”) 2 500/75 1) 300/45 1) 210/30 1)

Status word for: JOS, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - Yes - - - -

Instruction affects: - - - - 0 - - - -

List of Instructions Jump Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 83

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

JUO LABEL Jump if “unordered math instruction” (CC1=1 and CC0=1)

2 500/75 1) 300/45 1) 210/30 1)

JZ LABEL Jump if result = 0 (CC1=0 and CC0=0)

2

500/75 1) 300/45 1) 210/30 1)

JP LABEL Jump if result > 0 (CC1=1 and CC0=0)

2

500/75 1) 300/45 1) 210/30 1)

JM LABEL Jump if result < 0 (CC1=0 and CC0=1)

2

500/75 1) 300/45 1) 210/30 1)

JN LABEL Jump if result ≠ 0 (CC1=1 and CC0=0) or (CC1=0 and CC0=1)

2

500/75 1) 300/45 1) 210/30 1)

JMZ LABEL Jump if result < 0 (CC1=0 and CC0=1) or (CC1=0 and CC0=0)

2 500/75 1) 300/45 1) 210/30 1)

JPZ LABEL Jump if result > 0 (CC1=1 and CC0=0) or (CC1=0 and CC0=0)

2 500/75 1) 300/45 1) 210/30 1)

Status word for: JUO, JZ, JP, JM, JN, JMZ, JPZ, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - Yes Yes - - - - - -

Instruction affects: - - - - - - - - -

List of Instructions Jump Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 84

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416 JL LABEL Jump distributor

This instruction is followed by a list of jump instructions. The address identifier is a jump label to subsequent instructions in this list. ACCU1-LL contains the number of the jump instruction to be executed (max. 254). The number of the first jump instruction is 0.

2 575 345 240

LOOP LABEL Decrement ACCU1-L and jump if ACCU1-L ≥ 0 (loop programming)

2 400/75 1) 240/45 1) 160/30 1)

Status word for: JL, LOOP, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - - - - - -

List of Instructions Instructions for the Master Control Relay (MCR)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 85

Instructions for the Master Control Relay (MCR)

MCR=1 => MCR is deactivated. MCR=0 => MCR is activated. “T” and “=” instructions write zeros to the corresponding address identifiers if RLO = “0”; “S” and ”R” instructions leave the memory contents unchanged. 8 MCR bracket levels per priority class are possible.

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

MCR( Open an MCR zone.

Save the RLO to the MCR stack.

1 75 45 30

Status word for: MCR(, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - Yes -

Instruction affects: - - - - - 0 1 - 0

)MCR Close an MCR zone. Pop an entry off the MCR stack.

1 75 45 30

Status word for: )MCR, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - - 0 1 - 0

List of Instructions Instructions for the Master Control Relay (MCR)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 86

Execution Time in ns Instr. Address ID Description Length in

Words CPU 412 CPU 414 CPU 416

MCRA Activate the MCR 1 75 45 30

MCRD Deactivate the MCR 1 75 45 30

Status word for: MCRA, MCRD, BR CC1 CC0 OV OS OR STA RLO /FC

Instruction depends on: - - - - - - - - -

Instruction affects: - - - - - - - - -

List of Instructions Organization Blocks (OB)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 87

Organization Blocks (OB)

A user program for the S7-400 is made up of blocks containing the statements, parameters and data for the relevant CPU. The number of blocks you can create or which are provided by the operating system is different for each of the S7-400 CPUs. You will find a detailed description of the OBs and their use in the STEP 7 Programming Manual.

Organization Blocks

CPU412 CPU414 CPU416 Start Events (Hexadecimal Values)

Free cycle:

OB 1 x x x 1101, 1102, 1103, 1104, 1105

Time-of-day interrupts:

OB 10 x x x 1111

OB 11 x x x 1112

OB 12 x x 1113

OB 13 x x 1114

OB 14 x 1115

OB 15 x 1116

OB 16 x 1117

OB 17 x 1118

Time-delay interrupts:

OB 20 x x x 1121

OB 21 x x x 1122

OB 22 x x 1123

OB 23 x x 1124

List of Instructions Organization Blocks (OB)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 88

Organization Blocks

CPU412 CPU414 CPU416 Start Events (Hexadecimal Values)

Timed interrupts:

OB 30 x 1131, 113A

OB 31 x 1132, 113A

OB 32 x x x 1133, 113A

OB 33 x x 1134, 113A

OB 34 x x 1135, 113A

OB 35 x x x 1136, 113A

OB 36 x 1137, 113A

OB 37 x 1138, 113A

OB 38 x 1139, 113A

Hardware interrupts:

OB 40 x x x 1141, 1142, 1143, 1144, 1145

OB 41 x x x 1141, 1142, 1143, 1144, 1145

OB 42 x x 1141, 1142, 1143, 1144, 1145

OB 43 x x 1141, 1142, 1143, 1144, 1145

OB 44 x 1141, 1142, 1143, 1144, 1145

OB 45 x 1141, 1142, 1143, 1144, 1145

OB 46 x 1141, 1142, 1143, 1144, 1145

OB 47 x 1141, 1142, 1143, 1144, 1145

Interrupt OBs for DPV1:

OB 55 x x x 1155, 1158

OB 56 x x x 1156, 1159

OB 57 x x x 1157, 115A, 115B

List of Instructions Organization Blocks (OB)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 89

Organization Blocks

CPU412 CPU414 CPU416 Start Events (Hexadecimal Values)

Multicomputing interrupts:

OB 60 x x x 1161, 1162

Synchronous cycle interrupt:

OB 61 x x x 1164

OB 62 x x x 1165

OB 63 x x 1166

OB 64 x 1167

Asynchronous error interrupts:

OB 80 x x x 3501, 3502, 3505, 3506, 3507, 3508, 3509, 350A

OB 81 x x x 3821, 3822, 3823, 3825, 3826, 3827, 3831, 3832, 3833, 3921, 3922, 3923, 3925, 3926, 3927, 3931, 3932, 3933

OB 82 x x x 3842, 3942

OB 83 x x x 3951, 3954, 3854, 3855, 3856, 3857 3858, 3861, 3961, 3863, 3864, 3865, 3866, 3966, 3267, 3367, 3968

OB 84 x x x 3582, 3583, 3986, 3587

OB 85 x x x 35A1, 35A2, 35A3, 34A4, 35A4, 39B1, 39B2, 38B3, 39B3, 38B4, 39B4

OB 86 x x x 38C1, 38F8, 38F9, 39C1, 38C2, 39C3, 38C4, 39C4, 38C5, 39C5, 38C6, 38C7, 38C8, 39CA, 38CB, 39CB, 38CC, 39CD, 39CE, 32CF, 33CF, 39F8

OB 87 x x x 35D2, 35D3, 35D4, 35D5, 35E1, 35E2, 35E3, 35E4, 35E5, 35E6

OB 88 x x x 3573, 3575, 3576

Background:

OB 90 x x x 1191, 1192, 1193, 1195

List of Instructions Organization Blocks (OB)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 90

Organization Blocks

CPU412 CPU414 CPU416 Start Events (Hexadecimal Values)

Warm restart:

OB 100 x x x 1381, 1382, 138A, 138B

Hot restart:

OB 101 x x x 1383, 1384

Cold restart:

OB 102 x x x 1385, 1386, 1387, 1388

Synchronous error interrupts:

OB 121 x x x 2521, 2522, 2523, 2524, 2525, 2526, 2527, 2528, 2529, 2530, 2531, 2532, 2533, 2534, 2535, 253A, 253C, 253D, 253E, 253F

OB 122 x x x 2942, 2943

List of Instructions Function Blocks (FB)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 91

Function Blocks (FB)

The following tables list the quantities, numbers and maximum sizes of the function blocks you can create for the various S7-400 CPUs.

Function Blocks CPU 412-2 CPU 414 CPU 416

Quantity 1500 3000 5000

Permissible numbers 0 to 7999 0 to 7999 0 to 7999

Maximum size of a function block (code required for execution)

65534 Byte 65534 Byte 65534 Byte

List of Instructions Functions (FC) and Data Blocks (DB)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 92

Functions (FC) and Data Blocks (DB)

The following tables list the quantities, numbers and maximum sizes of the functions and data blocks you can create for the various S7-400 CPUs.

Functions CPU 412-2 CPU 414 CPU 416

Quantity 1500 3000 5000

Permissible numbers 0 to 7999 0 to 7999 0 to 7999

Maximum size of a function (code required for execution)

65534 Byte 65534 Byte 65534 Byte

Data Blocks CPU 412-2 CPU 414 CPU 416

Quantity 3000 6000 10000

Permissible numbers 1 to 16000 1 to 16000 1 to 16000

Maximum size of a data block (number of data bytes)

65534 Byte 65534 Byte 65534 Byte

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 93

System Functions

The following tables show the system functions which are provided by the operating system of the S7-400 CPUs and the execution times for the various CPUs. (X: function available, execution times not yet available before printing).

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

0 SET_CLK Set clock 99 74 49

1 READ_CLK Read clock 16 12 7

2 SET_RTM Set run-time meter 13 10 6

3 CTRL_RTM Start and stop run-time meter 11 8 5

4 READ_RTM Read run-time meter 14 11 7

Find logical address of a channel centralized I/O

19

15

10

5 GADR_LGC

internal DP 25 19 13

6 RD_SINFO Read start information of current OB 19 14 9

Trigger a process interrupt at the DP master First call

163 114 78

Intermediate call 15 10 8

7 DP_PRAL

Last call 15 10 8

Enable block-related, symbol-related, and group status messages. First call, REQ = 1

79 60 39 9 EN_MSG

Last call 21 16 10

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 94

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Disable block-related, symbol-related, and group status messages. First call, REQ = 1

79 60 39 10 DIS_MSG

Last call 20 16 10

Synchronize groups of DP Slaves First call, internal DP interface, REQ = 1

70 53 34

Intermediate call, internal DP interface, BUSY = 1 1)

20 + n* 4 16 + n* 3 10 + n* 2

11 DPSYC_FR

Last call, internal DP interface, BUSY=0 1) 21 + n* 4 16 + n* 3 10+ n* 2

First call, external DP interface, REQ=1 45 38 31

Intermediate call, external DP interface, BUSY = 1 1)

32 + n* 4 26 + n* 3 19 + n* 2

11 DPSYC_FR

Last call, external DP interface, BUSY= 0 1) 32 + n* 4 26 + n* 3 19 + n* 2

1 n = number of active jobs with the same logic address

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 95

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

12 D_ACT_DP Deactivate and activate DP slaves via integrated DP interface, MODE = 0

40 30 20

Deactivate and activate DP slaves via integrated DP interface, MODE = 1, 3 First call

153 119 83

Intermediate call 43 32 21

12 D_ACT_DP

Last call 52 40 26

Deactivate and activate DP slaves via integrated DP interface, MODE = 2, 4 First call

250 229 158

Intermediate call 43 32 21

12 D_ACT_DP

Last call 52 39 26

12 D_ACT_DP Deactivate and activate DP slaves viaexternal DP interface, MODE = 0

40 30 20

Deactivate and activate DP slaves via external DP interface, MODE = 1, 3 First call

133 119 83

Intermediate call 43 32 21

12 D_ACT_DP

Last call 53 40 26

Deactivate and activate DP slaves via external DP interface, MODE = 2, 4 First call

223 227 155

Intermediate call 42 32 21

12 D_ACT_DP

Last call 52 39 26

12 D_ACT_DP Deactivate and activate IO devices via integrated PNIO interface, MODE = 0

37 28 18

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 96

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Deactivate and activate IO devices via integrated PNIO interface, MODE = 1, 3

Fistcall

137 105 68

Intermediate call 39 29 19

12 D_ACT_DP

Last call 49 37 25

Deactivate and activate IO devices via integrated PNIO interface, MODE = 2, 4

Firstcall

452 477 319

Intermediate call 39 30 19

12 D_ACT_DP

Last call 50 37 25

12 D_ACT_DP Deactivate and activate IO devices via external PNIO interface, MODE = 0

37 28 18

Deactivate and activate IO devices via external PNIO interface, MODE = 1, 3 First call

139 105 68

Intermediate call 39 29 19

12 D_ACT_DP

Last call 50 37 25

Deactivate and activate IO devices via external PNIO interface, MODE = 2, 4 First call

524 469 313

Intermediate call 39 30 19

12 D_ACT_DP

Last call 50 37 25

Read slave diagnostics data First call

127

98

67

Intermediate call 48 37 24

13 DPNRM_DG

Last call (28 bytes) 63 48 32

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 97

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Read consistent user data (n bytes)via integrated DP interface 3 bytes

35 28 20

via integrated DP interface 32 bytes 36 29 20

via external DP interface 3 bytes 45 34 25

14 DPRD_DAT

via external DP interface 32 bytes 143 121 105

Read consistent user data (n bytes)via integrated PNIO interface 8 bytes

43 33 22

via integrated PNIO interface 32 bytes 44 33 22

via external PNIO interface 8 bytes 57 47 38

14 DPRD_DAT

via external PNIO interface 32 bytes 145 118 102

Write consistent user data (n bytes)via integrated DP interface 3 bytes

40 1) 41 2)

35 1) 36 2)

24 1) 24 2)

via integrated DP interface 32 bytes 42 1) 44 2)

36 1) 37 2)

24 1) 24 2)

via external DP interface 3 bytes 42 1) 43 2)

321) 322)

24 1) 24 2)

15 DPWR_DAT

via external DP interface 32 bytes 94 1) 95 2)

841) 852)

76 1) 76 2)

1 without data transmission to the process image 2 with data transmission to the process image

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 98

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Write consistent user data (n bytes)via integrated PNIO interface 8 bytes

42 1) 43 2)

32 1) 33 2)

22 1) 22 2)

via integrated PNIO interface 32 bytes 421) 432)

34 1) 35 2)

24 1) 24 2)

via external PNIO interface 8 bytes 46 1) 47 2)

37 1) 37 2)

30 1) 30 2)

15 DPWR_DAT

via external PNIO interface 32 bytes 93 1) 93 2)

81 1) 81 2)

73 1) 73 2)

Generate acknowledgeable block-related messages. First call, SIG = 0 -> 1

135 185 143 17 ALARM_SQ

Empty call 54 120 105

Generate unacknowledgeable block-related messages. First call, SIG = 0 -> 1

193 145 101 18 ALARM_S

Empty call 54 45 33

1 without data transmission to the process image 2 with data transmission to the process image

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 99

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

19 ALARM_SC Acknowledgment status of the last ALARM_SQ entering state message.

39 31 23

Copy variable within the work memory (n = number of bytes to be copied)

26 + n * 0,07

20 + n * 0,035

14 + n * 0,02

20 BLKMOV

Source = Load memory 290 + n * 0,6 243 +n * 0,5 202 +n * 0,3

21 FILL Set array default variables within the work memory (n = length of target variables in bytes)

24 + n * 0,03

19 + n * 0,021

12+ n * 0,014

Create data block 57 43 27 22 CREAT_DB

Occupy last free DB No. from a field of 100 DBs 248 178 117

23 DEL_DB Delete data block 58 38 24

24 TEST_DB Test data block 20 13 8

Compress user memory/load memory First call (trigger)

53

43

29

25 COMPRESS

Intermediate call (active) 11 9 6

Update process image input table (run-time entry for 1 DI 32 in the central rack)

23

19

15

26 UPDAT_PI

AI 8* 13Bit 42 39 34

Update process image output table (run-time entry for 1 DO 32 in the central rack)

21

18

14

27 UPDAT_PO

AO 8* 13Bit 39 36 31

28 SET_TINT Set time-of-day interrupt 43 34 22

29 CAN_TINT Cancel time-of-day interrupt 14 11 7

30 ACT_TINT Activate time-of-day interrupt 30 23 14

31 QRY_TINT Query time-of-day interrupt 8 7 4

32 SRT_DINT Start time-delay interrupt 24 20 13

33 CAN_DINT Cancel time-delay interrupt 16 12 8

34 QRY_DINT Query time-delay interrupt 8 7 4

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 100

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

35 MP_ALM Trigger multicomputing interrupt 170 131 90

36 MSK_FLT Mask synchronous faults 9 7 4

37 DMSK_FLT Demask synchronous faults 10 8 5

38 READ_ERR Read error register 11 8 5

Discard new events Block all events (MODE = 0)

89

69

47

Block all events of a priority class (MODE = 1)

22 17 11

39 DIS_IRT

Block one event (MODE = 2) 13 10 6

Stop discarding events Enable all events (MODE = 0)

88

67

45

Enable all events in a priority class (MODE = 1) 21 16 10

40 EN_IRT

Enable an event (MODE = 2) 12 9 6

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 101

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Delay interrupt events the first time delay is activated 1)

95 72 49 41 DIS_AIRT

If the delay is already activated 8 6 4

If other delays are present 9

7

5

42 EN_AIRT

Stop delaying interrupt eventswhen canceling the last delay 2)

181 143 103

43 RE_TRIGR Retrigger watchdog monitoring 86 64 42

44 REPL_VAL Transfer substitute value to ACCU1 10 9 5

46 STP Force CPU into STOP mode cannot be measured

-- -- --

47 WAIT Delay program execution in addition to waiting time

8 7 4

48 SNC_RTCB Synchronize slave clocks 9 7 4

49 LGC_GADR Find slot with logical address (central and PROFIBUS DP)

23 18 12

50 RD_LGADR Find all logical addresses of a block (run-time entry for 1 DI 32 in the central rack)

54 41 27

1 When activating the delay for the first time, the SFC 41 runtime depends on the priority class in which the SFC 41 is called. The specified runtime

refers to the call in OB 1. It decreases while the priority class number increases. 2 When activating the delay for the first time, the SFC 42 runtime depends on the priority class in which the SFC 42 is called. The specified runtime

refers to the call in OB 1. It decreases while the priority class number.

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 102

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

51 RDSYSST “Module identification” partial list Display one data record (0111)

66 49 33

”Module Identification” partial list Display all data records (0012)

124

93

62

Display one data record (0112) 78 59 39

51 RDSYSST

Display header information (0F12) 55 42 27

51 RDSYSST “Save” partial list Display one data record (0113)

70 52 35

“System Areas” partial list Display all data records (0014)

74

55

36

51 RDSYSST

Display header information (0F14) 55 41 27

51 RDSYSST “Block Types” partial list Display all data records (0015)

71

53

36

“Status of Module LEDs” partial list Display status of all LEDs (0019)

121

93

62

51 RDSYSST

Display header information (0F19) 77 58 38

“Component Identification” partial list Display all components (001C)

105

79

53

Display one of the components (011C) 74 56 37

51 RDSYSST

Display header information (0F1C) 61 46 30

51 RDSYSST “Interrupt status” partial list Display one data record (0222)

85 61 43

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 103

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

“TPA /CPU assignment” partial list Assignment between all process image partitions and OBs (0025)

163

123

81

Assignment between a process image partition and the corresponding OB (0125)

66 49 33

Assignment between an OB and corresponding process image partitions (0225)

130 97 65

51 RDSYSST

Display header information (0F25) 59 45 30

“Status information communication” partial list Display status information of a communication unit (0132)

78 - 129

59 - 97

39 - 65

51 RDSYSST

Display status information of a communication unit (0232)

80

60 39

51 RDSYSST “Modules LEDs” partial list Status of an LED (0174)

84 63 42

“DP master system information” partial list All known DP master systems of the CPU (0090)

125 93 62

A DP master system (0190) 68 52 34

51 RDSYSST

Header information (0F90) 58 44 29

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 104

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

“Module status information” partial list Display status information of all inserted modules (n=number of DR) (0091)

393 + n * 22 302 + n * 19 203 + n * 16

Display status information of all modules /racks with incorrect type indentification (0191)

293 + n * 70 217 + n * 60 146 + n * 40

All faulty modules (0291) 295 + n * 99 218 + n * 22 146 + n * 18

All unavailable modules (0391) 299 + n * 69 221 + n * 60 148 + n * 40

51 RDSYSST

All submodules of the host module (0591) 91 70 47

Display the status information of all submodules of the host module in the specified rack (0991)

144 + n * 12 107 + n * 7 72+ n * 5

Display the status information of a module with logical basic address Central (0C91)

109

82

55

Distributed to integrated DP interface (0C91) 133 98 66

Distributed to integrated PNIO interface (0C91) 126 89 60

51 RDSYSST

Distributed to external PNIO interface (0C91) First call Intermediate call Last call

173 121 130

129 92 89

90 63 67

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 105

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

“Module status information” partial list of a module (distributed) with logical basic address (4C91) First call Intermediate call Last call

138 88 97

106 66 73

71 44 48

Central all modules in the specified rack (n = number DR) (0D91)

140 + n* 23 102 + n* 16 70 + n* 10

Distributed all modules in the specified DP station / in the specified IO device (0D91)

122 - 142 89 - 98 60 - 71

all assigned modules (0E91) 410 306 204

51 RDSYSST

Header information (0F91) 208 187 104

“Rack/station status information” partial list Central Display setpoint status of rack 0 (0092)

71 53 35 51 RDSYSST

Distributed Display setpoint status of DP system 1 (0092)

296 220 147

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 106

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Display setpoint value of DP system1 (via external DP interface) (4092) First call Intermediate call Last call

117 71 79

88 53 59

59 35 40

Display activation status of DP master system 1 (via integrated DP interface) (0192)

305 227 151

Central Display the actual status of rack 0 (0292)

72 54 36

Distributed Display the actual status of DP system 1 (0292)

307 228 152

51 RDSYSST

Display the actual status of the stations of a DP master system (via external DP interface) (4292) First call Intermediate call Last call

119 71 80

90 53 60

59 36 40

Display the status of rack 0 battery buffer if at least one battery has failed (0392)

70 53 35

Display the status of the entire battery buffer of a CPU (0492)

71 53 35

51 RDSYSST

Display the status of the 24 V supply of all racks of a CPU (0592)

71 53 35

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 107

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Central Display the diagnostics status of the expansion devices (0692)

135 101 67

Distributed Display the diagnostics status of the DP system 1 stations (via integrated DP interface) (0692)

366 268 179

51 RDSYSST

Diagnostics status of the stations of a DP master system connected via an external DP interface (4692) First call Intermediate call Last call

118 72 80

89 54 60

59 36 40

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 108

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416 Partial list “Rack / station status information” Expected status of the central rack (0094) Expected status of the stations of an IO controller system to an integrated interface (0094)

Expected status of the stations of an IO controller system to an external interface (0094): First call Intermediate call Last call

95

717

158 114 142

71

539

119 86

107

48

375

79 56 71

51 RDSYSST

Activation status of a station of an IO controller system which is configured and disabled (0194) To integrated interface

To an external interface: First call Intermediate call Last call

826

159 113 141

617

119 85

106

436

79 75 70

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 109

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Actual status of the central rack (0294) Actual status of the stations of an IO controller system to an integrated interface (0294)

Actual status of the stations of an IO controller system to an external interface (0294): First call Intermediate call Last call

96

796

158 114 143

72

593

119 86 107

48

414

78 57 71

Diagnostics status of the central rack (0694) Diagnostics status of the stations of an IO controller system to an integrated interface (0694)

Diagnostics status of the stations of an IO controller system to an external interface (0694):First call Intermediate call Last call

193

844

160 116 144

145

628

120 87 108

99

438

79 57 71

Maintenance status of the central rack (0794) Maintenance status of the stations of an IO controller system to an integrated interface (0794)

4723 874

3542 645

2429 447

51 RDSYSST

Header information (0F94) (central and PROFINET IO)

78 58 38

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 110

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

“Advanced DP master system / PROFINET IO system information” partial list Read out the extended information via a DP master system / PROFINET IO system to an integrated 1) or external interface (0195)

73

55

36

51 RDSYSST

Header information (0F95) 56 43 28

Partial list “Module status information of all submodules to a specified module for PROFINET IO to an integrated interface (0696)

96

64

41

51 RDSYSST

Module status information of a module / submodule centrally or to a PROFIBUS DP- /PROFINET interface Central (0C96) PROFIBUS DP via integrated interface (0C96) PROFINET IO via integrated interface (0C96) PROFINET IO via external interface (0C96): First call Intermediate call Last call

94 117 89

158 105 116

69 87 66

119 77 84

47 58 45

82 52 57

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 111

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

“Diagnostics buffer” partial list Display all deliverable event information in the current operating mode (max. 21) (00A0)

77 - 151 55 - 114 35 – 77

Display the latest entries (n = 1-23) (01A0) 70 + n* 6 53 + n* 4,4 35 + n* 3

51 RDSYSST

Display the header information (0FA0) 61 46 30

Information on all tool changers and their tools in a PROFINET IO system (009C)

72 55 36

Information on all tool changers on a PROFINET IO system (019C)

70 53 35

Information on one tool changer and its tools (029C)

75 57 38

Information on a tool changer and its IO devices (039C)

75 57 38

51 RDSYSST

Only SSL partial list header information (0F9C) 73 55 37

“Diagnostics data DR 0” partial list Display via logical basic address (00B1) central

185

144

104

51 RDSYSST

PROFIBUS DP (00B1) First call Intermediate call REQ = 0 Last call

163 89 99

117 63 70

77 41 49

51 RDSYSST “Diagnostics data DR 1” partial list Read-out via physical address (00B2) Display a 16-byte long DR 1

128 96 68

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 112

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

“Diagnostics data DR 1” partial list Display via logical basic address (00B3) Display a 16-byte long DR 1 central

215 155 115 51 RDSYSST

PROFIBUS DP (00B3) First call Intermediate call Last call

165 89

107

120 69 78

79 45 54

51 RDSYSST ”Diagnostics Data DP Slave” partial list Display via configured diagnostics address (00B4) First call Intermediate call, REQ = 0 Last call (6 - 240 bytes)

144 88

135

108 66 99

76 45 70

Write user entry in diagnostics bufferwrite with message

47 35 23 52 WR_USMSG

Without message 45 34 22

Read dynamic parameterslocal AI 8*13 bits 76 58 38 54 RD_DPARM

PROFIBUS DP AI 8*12 bits (DS1 = 14 bytes)

91 68 46

Write dynamic parameterslocal AI 8*13 bits 207 165 122

PROFIBUS DP First call AI 8*12 bits (14 - 240 bytes)

161 123 83

55 WR_PARM

PROFIBUS DPIntermediate/last call, REQ = 0 65 50 33

DR = Data record

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 113

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Write predefined dynamic parameters AI 8*13 bitsLocal

248

213

161

PROFIBUS DP First call AI 8*12 bits (2 - 240 bytes)

131 100 69

56 WR_DPARM

PROFIBUS DP Intermediate/last call

65 50 33

Assign module parameters localModule/DS number/DS lengths in bytes AI 8*13 bits

420 348 276

PROFIBUS DPAO 8*12 bits First call (16 - 240 bytes)

131 100 68

57 PARM_MOD

PROFIBUS DP Intermediate/last call

65 49 32

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 114

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Write parameter data record local (n = number of bytes)

152 + n * 2,7 118 + n * 2,5 84 + n * 2,3

First call, integrated DP interface module (n = number of bytes)

145 + n * 0,1 110 + n * 0,04 75 + n * 0,03

Intermediate call, REQ = 0 integrated DP interface module

59 44 29

Last call, integrated DP interface module 60 44 29

First call, external DP interface module (n = number of bytes)

146 + n * 0,06 111 + n * 0,06 76 + n * 0,04

Intermediate call, REQ = 0 external DP interface module

59 44 29

58 WR_REC

Last call, external DP interface module 59 44 29

Read data record local (n = number of bytes)

149 + n * 2,9 118 + n * 2,7 83 + n * 2,45

First call, integrated DP interface module 139 105 74

Intermediate call, REQ = 0 integrated DP interface module

59 44 29

Last call, integrated DP interface module (n = number of bytes)

170 + n * 0,01 132 + n * 0,04 93 + n * 0,03

First call, external DP interface module 139 105 73

Intermediate call, REQ = 0 external DP interface module

59 43 28

59 RD_REC

Last call, external DP interface module (n = number of bytes)

172 + n * 0,06 136 + n * 0,06 97 + n * 0,03

Send GD packet 1 byte

104 72 47 60 GD_SND

32 bytes 282 168 107

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 115

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

61 GD_RCV Receive GD package (1 - 32 Byte)

67 52 22

62 CONTROL Check status of the connection belonging to a local communication-SFB-instance

60 42 27

64 TIME_TCK Display millisecond timer 9 7 4

Transmit data to external partner First call, establish a connection (1 - 76 bytes) REQ = 1

406 358 305

First call, connection present (1-76 bytes)

202 152 101

Intermediate call (1-76 bytes)

81 61 40

65 X_SEND

Last call, BUSY = 0 90 67 44

Receive data from external partner Test reception (1-76 bytes)

50 38 25 66 X_RCV

Read data (1-76 bytes)

146 110 72

Read data from external partner First call, establish a connection (1-76 bytes) REQ = 1

377 334 290

First call, connection present (1-76 bytes)

172 129 86

Intermediate call (1-76 bytes)

83 63 41

67 X_GET

Last call BUSY = 0 141 106 70

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 116

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Write data to external partner First call, establish a connection (1-76 bytes) REQ = 1

412 360 308

First call, connection present (1-76 bytes)

207 155 103

Intermediate call (1-76 bytes)

83 62 41

68 X_PUT

Last call, BUSY = 0 91 68 45

Abort connection to external partner First call, REQ = 1

115 85 58

Intermediate call 55 42 28

69 X_ABORT

Last call, BUSY = 0 249 237 225

70 GEO_LOG Determine the start address from the slot of a module

28 19 13

71 LOG_GEO Determine the module slot from the associated logical address

29 23 15

Read data from internal partner First call, establish a connection (1-76 bytes) REQ = 1

402 353 303

First call, connection present (1-76 bytes) 175 132 88

Intermediate call (1-76 bytes) 87 64 42

72 I_GET

Last call, BUSY = 0 145 109 73

Write data to internal partner First call, establish a connection (1-76 bytes) REQ = 1

217 – 437 162 - 380 110 - 322

First call, connection present (1-76 bytes) 212 158 107

Intermediate call (1-76 bytes) 87 65 42

73 I_PUT

Last call, BUSY = 0 94 71 46

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 117

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Abort connection to internal partner First call, REQ = 1

121 85 58

Intermediate call 65 41 27

74 I_ABORT

Last call, without / with connection BUSY = 0

64 / 248 42 / 236 32 / 225

78 OB_RT Determine OB program runtime 26 21 13

79 SET 1) Set bit array in I/O area n = number of bits to set at 1

17 + n * 0,15 14 + n * 0,13 10 + n * 0,13

80 RSET 1) Delete bit array in I/O area n = number of bits to set at 0

17 + n * 0,15 14 + n * 0,13 9 + n * 0,13

81 UBLKMOV Copy variable without interruption n = number of bytes to copy

22 + n* 0,035 14 + n* 0,02 10 + n* 0,02

Determine current connection status MODE = 0

12 9 6 87 C_DIAG

Mode = 1, 2, 3 127 123 118

99 WWW Activate or synchronize user webpages 225 213 143

1 Measured with I/O modules of the type “Binary Simulator C79459–A1002–A1, Release 1” in the central rack

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 118

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Set time-of-day and clock status MODE = 1

99 73 48

MODE = 2 50 36 24

100 SET_CLKS

MODE = 3 96 71 47

Handle operating hours counterMode = 0 Read 15 12 7

Mode = 1, 2 Start/Sop 20 15 10

101 RTM

Mode = 4, 5, 6 Set 27 20 13

Detemine bus topology in a DP master system first call, REQ = 1

136 101 70

Intermediate call 22 17 11

103 DP_TOPOL

Last call BUSY = 0 23 18 11

Controls the CiR procedure MODE = 0, information

9 7 4

MODE = 1, Enable CiR procedure 8 6 4

MODE = 2, Disable CiR procefure entirely 8 6 4

104 CIR

MODE = 3, Disable CiR procedure partially 8 7 4

Read dynamically assigned system resources MODE = 0

62 - 1437 1) 46 - 1164 1) 31 - 817 1)

MODE = 1 75 - 1650 2) 53 - 1419 2) 35 - 1259 2)

MODE = 2 70 - 1809 2) 54 - 2142 2) 36 - 3927 2)

105 READ_SI

MODE = 3 70 - 1749 3) 54 - 1427 3) 36 - 1991 3)

1 Depending on the size of the SYS_INST target area and on the number of the system resources to be read 2 Depending on the number of active messages (assigned system resources) 3 Depending on the number of active messages (assigned system resources) and on the number of assigned instances with the desired CMP_ID.

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 119

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

Enable dynamically assigned system resources MODE = 1

85 - 1432 1) 65 - 1729 1) 43 - 3011 1)

MODE = 2 86 - 1414 1) 66 - 1659 1) 43 - 2921 1)

106 DEL_SI

MODE = 3 86 - 1436 2) 65 - 1730 2) 42 - 3010 2)

Acknowledgeable block-related messages create first call, SIG = 0 -> 1

130 103 70 107 ALARM_DQ

Call (without message) 55 45 31

Not acknowledgeable block-related messages create first call, SIG = 0 -> 1

118 83 67 108 ALARM_D

Call (without message) 53 36 24

109 PROTECT Activate write protection 11 6 4

1 Depending on the number of active messages (assigned system resources) 2 Depending on the number of active messages (assigned system resources) and on the number of assigned instances with the desired CMP_ID.

List of Instructions System Functions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 120

Execution Time in µs SFC No.

SFC Name Description

CPU 412 CPU 414 CPU 416

112 PN_IN Update the inputs for the user program interface of the PROFINET CBA components

< 13850 1) < 9750 1) < 6730 1)

113 PN_OUT Update the outputs for the user program interface of the PROFINET CBA components

< 11660 1) < 8150 1) < 6050 1)

114 PN_DP Update the DP interconnections < 2924 1) < 2030 1) < 2030 1)

126 SYNC_PI Update the process image partition of the inputs in a synchronous cycle

35 25 19

127 SYNC_PO Update the process image partition of the outputs in a synchronous cycle

34 24 18

1 The execution times of these blocks depend on their interconnection configuration and the size of the interface DBs. Please also note the information in

chapter “CBA Reaction times” in the manual Automation System S7-400 CPU Specifications

List of Instructions System Function Blocks

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 121

System Function Blocks

The following table lists the system function blocks provided with the operating system of the S7-400 CPUs as well as the execution times of the individual CPUs (X: function exists, execution times were not available when manual was printed)

Execution Time in µs SFB No.

SFB Name Description

CPU 412 CPU 414 CPU 416

0 CTU Count up 3 1 1

1 CTD Count down 2 1 1

2 CTUD Count up and down 3 1 1

3 TP Generate pulse 11 8 6

4 TON Generate on-delay 11 8 5

5 TOF Generate off-delay 9 6 4

Send data without coordination (one send parameter supplied) JOB activated (1 - 440 bytes)

202 - 221 149 - 162 100 - 110

JOB checked 75 55 37

8 USEND

JOB finished (DONE = 1) 72 54 36

Receive data without coordination (one receive parameter supplied) JOB activated

62 46 31

JOB checked 67 50 33

9 URCV

JOB finished (NDR = 1; 1 - 440 bytes) 136 - 154 102 - 115 68 - 76

Send data block by block JOB activated (1 - 3000 bytes)

181 134 91

JOB checked 82 61 41

12 BSEND

JOB finished (DONE = 1) 80 59 39

List of Instructions System Function Blocks

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 122

Execution Time in µs SFB No.

SFB Name Description

CPU 412 CPU 414 CPU 416

Receive data block by block JOB activated (1 - 3000 bytes)

89 67 45

JOB checked 93 69 46

13 BRCV

JOB finished 79 63 41

Read data from remote CPU (one area specified) JOB activated

161 118 81

JOB checked 76 57 38

14 GET

JOB finished (NDR = 1; 1 - 450 bytes) 135 - 154 102 - 115 67 - 77 Write data to remote CPU JOB activated (1 - 404 bytes)

213 - 230 153 - 170 106 - 112

JOB checked 76 56 38

15 PUT

JOB finished (DONE = 1) 74 54 37 Send data to a printer JOB activated, REQ = 1

218 - 233 157 - 176 107 - 121

JOB checked 76 56 37

16 PRINT

JOB finished, DONE = 1 73 54 36 Start remote device JOB activated, REQ = 1

204 155 105

JOB checked 79 58 39

19 START

JOB finished, DONE = 1 78 57 39 Stop remote device JOB activated, REQ = 1

199 153 103

JOB checked 79 59 39

20 STOP

JOB finished, DONE = 1 77 58 39

List of Instructions System Function Blocks

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 123

Execution Time in µs SFB No.

SFB Name Description

CPU 412 CPU 414 CPU 416

Restart remote device JOB activated, REQ = 1

211 156 106

JOB checked 79 59 39

21 RESUME

JOB finished, DONE = 1 77 58 39 Query status of remote partner JOB activated, REQ = 1

127 97 66

JOB checked 76 56 38

22 STATUS

JOB finished, NDR = 1 194 145 97 Receive status of remote device without coordination JOB activated, NDR = 1

66 49 33

JOB checked 67 49 33

23 USTATUS

JOB finished 195 145 98 Generate block-related message without acknowledgment First call or JOB activated, SIG = 0-> 1 (1 - 420 bytes)

262 - 279 192 - 206 131 - 141

JOB checked 106 79 53

31 NOTIFY_8P

JOB finished, DONE = 1 108 81 53 32 DRUM Implement sequencer 17 13 9

Generate block-related message with acknowledgment First call or JOB activated, SIG = 0-> 1 (1 - 420 bytes)

259 - 261 192 - 195 131 - 133

JOB checked 107 79 53

33 ALARM

JOB finished, DONE = 1 109 80 54

List of Instructions System Function Blocks

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 124

Execution Time in µs SFB No.

SFB Name Description

CPU 412 CPU 414 CPU 416

Generate block-related message without accompanying values for 8 signals First call or JOB activated, SIG = 0-> 1 (1 - 420 bytes)

209 154 105

JOB checked 106 79 53

34 ALARM_8

JOB finished, DONE = 1 107 80 53 Generate block-related message with accompanying values for 8 signals First call or JOB activated, SIG = 0-> 1 (1 - 420 bytes)

260 - 277 193 - 205 131 - 140

JOB checked 106 79 53

35 ALARM_8P

JOB finished, DONE = 1 108 82 53 Generate block-related message without acknowledgment First call or JOB activated, SIG = 0-> 1 (1 - 420 bytes)

252 - 274 190 - 203 130 - 138

JOB checked 104 78 52

36 NOTIFY

JOB finished, DONE = 1 107 80 53 Send archive data First call or JOB activated, REQ = 1 (1 - 3000 bytes)

178 - 184 131 - 136 88 - 92

JOB checked 83 61 41

37 AR_SEND

JOB finished, DONE = 1 80 60 41

List of Instructions System Function Blocks

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 125

Execution Time in µs SFB No.

SFB Name Description

CPU 412 CPU 414 CPU 416

52 RDREC Read data record from a central module. 168 131 95 Read data record from a DP slave via integrated DP interface, First call (2-16 bytes)

155 117 79

Intermediate call 68 50 33

52 RDREC

Last call 73 53 34 Read data record from a DP slave via external DP interface,First call (4-16 bytes)

139 103 68

Intermediate call 67 49 33

52 RDREC

Last call 70 52 34 Read data record from an IO device viaintegrated PNIO interface, First call

138 102 67

Intermediate call 64 47 31

52 RDREC

Last call 66 49 33 Read data record from an IO device via external PNIO interface, First call

137 104 67

Intermediate call 67 59 33

52 RDREC

Last call 70 51 34 53 WRREC Write data record to a central module 164 128 94

Write data record in a DP slalve via integrated DP interface, First call (1-10 bytes)

162 121 81

Intermediate call 66 49 33

53 WRREC

Last call 68 51 33

List of Instructions System Function Blocks

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 126

Execution Time in µs SFB No.

SFB Name Description

CPU 412 CPU 414 CPU 416

Write data record in a DP slave via external DP interface, First call (2-14 bytes)

149 112 72

Intermediate call 66 49 32

53 WRREC

Last call 69 52 34

Write data record in an IO device via integrated PNIO interface, First call (1-10 bytes)

149 109 72

Intermediate call 64 47 31

53 WRREC

Last call 66 49 32

Write data record in an IO device via external PNIO interface, First call (2-14 bytes)

144 110 74

Intermediate call 67 49 32

53 WRREC

Last call 69 51 33

54 RALRM Receive interrupt from a DP slave or an IO device Runtime measurement for non-I/O-dependent OBs, MODE = 1, OB 1

66 49 34

List of Instructions System Function Blocks

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 127

Execution Time in µs SFB No.

SFB Name Description

CPU 412 CPU 414 CPU 416

Receive interrupt from a DP slave or an IO device. Runtime measurement at integrated DP or PROFINET interface, MODE = 1, OB 40, OB 83, OB 86

123 90 64 54 RALRM

OB 55 to OB 57, OB 82 127 92 67

Receive interrupt from a DP slave or an IO device Runtime measurement at external DP or external PROFINET interface, MODE = 1, OB 40, OB 83, OB 86

202 156 109 54 RALRM

OB 55 to OB 57, OB 82 356 274 196

Receive interrupt from a DP slave or an IO device Runtime measurement at central I/O, MODE = 1, OB 40, OB 82, OB 83, OB 86

136 79 55 54 RALRM

OB 55 to OB 57 379 287 199

List of Instructions System Function Blocks

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 128

Execution Time in µs SFB No.

SFB Name

Description CPU 412 CPU 414 CPU 416

81 RD_DPAR Read predefined parameter centrally 101 76 51

81 RD_DPAR Read predefined parameter DP 114 86 57

Read predefined parameter PNIO First call

149

117

80

Intermediate call 149 117 81

81 RD_DPAR

Last call 105 82 56

Set IP configuration

First call

77 58 39 104 IP_CONF

Last call 85 64 41

List of Instructions Function Blocks for Open Communication via Industrial Ethernet

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 129

Function Blocks for Open Communication via Industrial Ethernet

The following table lists the function blocks for open communication via Industrial Ethernet which are made available to the S7-400 CPU by the operating system and the execution times of the corresponding CPU. The execution times are only valid for data volumes up to 8 Kbyte.

Execution Time in µs FB- No. FB-Name Description

CPU 412 CPU 414 CPU 416 63 TSEND Send data CP and ISO on TCP (n bytes)

First call Intermediate call Last call

143 + n * 0,037

56 57

108 + n * 0,027

43 43

71 + n * 0,018

25 27

64 TRCV Receive data via TCP and ISO on TCP (n bytes)

104 + n * 0,02 78 + n * 0,02 51 + n * 0,02

65 TCON Establish connection First call Intermediate call Last call

129 37 37

96 28 28

65 17 18

List of Instructions Function Blocks for Open Communication via Industrial Ethernet

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 130

Execution Time in µs FB- No. FB-Name Description

CPU 412 CPU 414 CPU 416

66 TDISCON Terminate connection

First call

Intermediate call

Last call

89

34

36

61

26

27

45

17

18

Send data via UDP (n bytes)

First call

172 + n * 0,037

130 + n * 0,027

85 + n * 0,019

Intermediate call 58 44 28

67 TUSEND

Last call 59 45 29

68 TURCV Receive data via UDP (n bytes) 126 + n * 0,05 95 + n * 0,03 64 + n * 0,018

Sublist of the System Status List (SSL)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 131

Sublist of the System Status List (SSL)

SSL-ID Information Functions

Module Identification

0111 One ident. data record only

CPU Characteristics

0012 CPU features, all features

0112 Features of a group

0F12 Only SSL partial list header information

User Memory Area

0113 Data record for specified memory area

Work memory

System Areas

0014 System areas, all system areas

0F14 Only partial list header information

Block Types

0015 Block types, data records for all block types

Status Module LEDs

0019 Status of all module LEDs

0F19 Only partial list header information

Component Identification

001C Identification of all components

011C Identification of one component

0F1C Only SSL partial list header information

Sublist of the System Status List (SSL)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 132

SSL-ID Information Functions

Interrupt Status

0222 Data record for specified interrupt

Assignment between process image partitions and OBs

0025 Assignment betweeen all process image partitions and OBs within the CPU

0125 Assignment between a process image partition and the corresponding OB

0225 Assignment between an OB and the corresponding process image partitions

0F25 Only SSL partial list header information

Communication Status Data

0132 Status data for a communication unit

Diagnostics status

Target system status

0232 Status data for a communication unit

CPU protection level, operating switch positions and version ID / CRC

Status of the Module LEDs

0174 Status of one LED

DP Master System Information

0090 Information about all the DP master systems known to the CPU

0190 Information about a DP master system

0F90 Only SSL partial list header information

Sublist of the System Status List (SSL)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 133

SSL-ID Information Functions

Module Status Information (A maximum of 27 data records are supplied)

0091 Module status information of all inserted modules/submodules

0191 Status information of all modules/racks with incorrect type IDs.

0291 Module status information of all faulty modules

0391 Module status information of all unavailable modules

0591 Module status information of all submodules of the host module

0991 Status information of a DP master system

0C91 Status information of a module in the central rack or connected to an integrated DP interface module or connected to an integrated PROFINET interface module

4C91 Status information of a module connected to an external DP interface module or connected to an external PROFINET interface module

0D91 Status information of all modules in the specified rack / in the specified station (DP or PROFINET)

0E91 Status information of all assigned modules

Rack/Station Status Information

0092 Expected status of the central racks/stations of a DP master system

4092 Expected status of the stations of a DP master system which is connected via an external DP interface module

0192 Activation status of the stations of a DP master system which is connected via an external DP interface module

0292 Actual status of the central racks/stations of a DP master system

4292 Actual status of the stations of a DP master system which is connected via an external DP interface module

0392 Status of the back-up battery of a CPU rack if at least one battery fails

0492 Status of the entire back-up batteries of all racks of the a CPU

0592 Actual status of the racks in the central configuration/stations of DP master system which is connected via an external DP interface module.

0692 OK status of the expansion units in the central configuration/stations of a DP master system which is connected via an integrated DP interface module.

4692 OK status of the stations of a DP master system which is connected via an external DP interface module.

Sublist of the System Status List (SSL)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 134

SSL-ID Information Functions

Rack / station status information

0094 Expected status of the central racks / stations of an I/O controller system which is connected via an integrated interface

0194 Activation status of a station in an I/O controller system which is configured and disabled

0294 The actual status of the central racks / stations of an I/O controller system which is connected via an integrated interface

0694 Status of the expansion devices of an I/O controller system which is connected via an integrated interface

0794 Maintenance status of the central racks / stations of an I/O controler system

0F94 Only SSL partial list header information Teilistenkopfinformation

Addtional DP Master System / PROFINET IO System Information

0195 Additional information on a DP master system / PROFINET IO system

0F95 Only SSL partial list header information

Module status information PROFINET IO and PROFIBUS DP

0696 Module status information for all submodules in the specified module

0C96 Module status information for a central module / submodule or a PROFIBUS DP / PROFINET IO interface

Tool changer Information

009C Information on all tool changers and their tools in a PROFINET IO system:

019C Information on all tool changers

029C Information on one tool changer and its tools

039C Information on a tool and its IO devices

0F9C Only header information

Diagnostics Buffer (A maximum of 21 data records are supplied)

00A0 All current diagnostics entries available in current operating mode

01A0 The last entries

0FA0 Only partial list header information

Sublist of the System Status List (SSL)

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 135

SSL-ID Information Functions

Module Diagnostics Data

00B1 First four diagnostics bytes of a module (DS0)

00B2 All diagnostics data of a module (< 220 bytes, DS1) (no DP module)

00B3 All diagnostics data of a module (< 220 bytes, DS1)

00B4 Diagnostics data of a DP slave with logical base address

Alphabetical Index of Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 136

Alphabetical Index of Instructions

Instr. Page ) 25 )MCR 85 *D 55 *I 54 *R 56 /D 55 /I 54 /R 56 + 61 +AR1 62 +AR2 62 +D 55 +I 54 +R 56 <<=D 64 <<=I 63 <<=R 65 <<D 64 <<I 63 <<R 65 = 34 ==D 64 ==I 63 ==R 65 ><D 64 ><I 63 ><R 65 >=D 64 >=I 63

Instr. Page >=R 65 >D 64 >I 63 >R 65 A 27 ABS 57 ACOS 60 AD 29 AN 27 ASIN 60 ATAN 60 AUF 77 AW 29 BE 78 BEC 78 BEU 78 BLD 70 BTD 71 BTI 71 CALL 75 CC 76 CDB 79 CLR 35 COS 60 -D 55 DEC 69 DTB 72 DTR 71 ENT 69

Alphabetical Index of Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 137

Instr. Page EXP 59 FN 32 FP 32 FR 37, 40 -I 54 INC 69 INVD 74 INVI 74 ITB 72 ITD 71 JBI 81 JC 80 JCB 81 JCN 80 JL 84 JM 83 JMZ 83 JN 83 JNB 81 JNBI 81 JO 82 JOS 82 JP 83 JPZ 83 JU 80 JUO 83 JZ 83 L 41, 42, 43, 44, 45, 46, 52, 53 LAR1 50 LAR2 50 LC 46 LEAVE 69

Instr. Page LN 59 LOOP 84 MCR( 85 MCRA 86 MCRD 86 MOD 55 NEG 35 NEGD 74 NEGI 74 NEGR 57 NOP 70 O 22, 26, 28, 30, 31 O( 24 OD 29 ON 22, 28, 30, 31 ON( 24 OW 29 POP 69 PUSH 69 R 33, 37, 39 -R 56 RLD 68 RLDA 68 RND 73 RND- 73 RND+ 73 RRD 68 RRDA 68 S 33, 39 SA 37 SAVE 35 SD 36

Alphabetical Index of Instructions

Instruction List S7-400 Instruction List S7-400, 10/2010, A5E03305792-02 138

Instr. Page SE 36 SET 35 SIN 60 SLD 66 SLW 66 SP 36 SQR 58 SQRT 58 SRD 67 SRW 66 SS 37 SSD 67 SSI 67 T 47, 48, 49, 52 TAD 69 TAK 69 TAN 60 TAR 51 TAR1 51 TAR2 51 TAW 69 TRUNC 73 U 21, 30, 31 U( 24 UC 76 UN 21, 30, 31 UN( 24 X 23, 28, 30 X( 24 XN 23, 28, 30 XN( 24 XOD 29

Instr. Page XOW 29 ZR 40 ZV 39