iNEMI Project Report on

Process Development of BiSn-Based

Low-Temperature Solder Pastes

Raiyo Aspandiar

Intel Corporationraiyo.f.aspandiar@intel.com

1

Co-authors

2

Name Company

Haley Fu iNEMI, China

Jimmy Chen Flex Corp, Zhuhai, China

Shunfeng Cheng Intel Corp , Oregon, USA

Qin Chen Eunow, Suzhou, China

Richard Coyle Nokia, New Jersey, USA

Sophia Feng Celestica, Dongguan, China

Mark Krmpotich Microsoft Corp, Washington, USA

Ron Lasky Indium Corp, New Hampshire, USA

Name Company

Scott Mokler Intel Corp, Oregon, USA

Jagadeesh Radhakrishnan Intel Corp, California, USA

Morgana Ribas Alpha Assembly Systems, India

Brook Sandy-Smith Indium Corp, New York, USA

Kok Kwan Tang Intel Corp, Kulim, Malaysia

Greg Wu Wistron, Hsinchu, Taiwan

Anny Zhang Indium Corp, Washington, USA

Wilson Zhen Lenovo, Shenzhen, China

Outline

Motivation for Low Temperature Solders

iNEMI Low Temperature Solder Processing and Reliability

(LTSPR) Project Info

List of Solder Pastes Evaluated and Reasons why

Component and Board Test Vehicles

Process Evaluations

Printability / Reflow Profiles / Solder Joint Defects / Rework / SIR

Summary and Next Steps

Q & A

3

Motivation for Low Temperature Solder (LTS)

Reflow

Reduced Electricity

Saves >

$8,500/oven/year

Reduced Emissions saves

57 metric tons of CO2 per oven/year

Faster Technology Scaling Energy & Emissions Process &

Materials

Wave Solder Elimination

Solder Material Cost Reduction

0

0.5

1

1.5

2012 2014 2016 2018 2020

SKL-Y

20x16.5x0.91mm

I/O Density

Pkg X-Y

…

5

▪ Motivation spans multiple areas

LTS Enables System Manufacturing to

Keep Pace with Moore’s Law

4

Low Temperature Solder Paste’s % Share of the Total

Volume of Solder Paste Used for Board Assembly

5

Volu

me %

of S

old

er

Paste

for

Board

Assem

bly

Year

Source: iNEMI 2017 Roadmap

▪ Increasing trend forecast in Low Temperature Solder paste Usage starting 2017

Low Temperature Solder Pastes

Low Temperature Solders

Enter Text

6

Medium Temperature Solders

[SnAgCu+Bi,In]• melt in the 210 to 220C range

Low Temperature Solders

[Bi/Sn/X, X=Ag,Cu,Ni]• melt in the 139 to 175C range

➢ There are a variety of compositions and

melting ranges for Potential Low Temperature

Solders in Electronics Manufacturing

▪ Bi-Sn system solders selected for LTSPR Project

o Significantly larger processing and economic benefits than Medium

Temperature Solders

iNEMI LTSPR Project Participants

7

Binghamton University

▪ 22 Participants

▪ Mix of

o EMS/ODMs

o OEMs

o Suppliers

o Universities

iNEMI LTSPR Project Phases and Timeline

8

Team Formation

and SOW

Ratification

Materials Selection

and Process

Development

Mechanical Shock

Testing and

Evaluation

Temperature

Cycling and other

Reliabiliy

Evaluations

Manufacturing

Validation of

Product Board

2015 2016 2017 2018

Module

o Brittleness of Solder Joints formed using BiSn solder paste

SAC

region

Bi-mixed

region

Fracture

Through / above

IMC

Mechanical Shock or Drop

Bi causes joint

hardening and is

prone to brittle

fractures under

mechanical shock and

drop forces

Major issue with BiSn based Solders

➢ Bismuth is inherently more brittle than Tin

Bi region of Mixed BGA solder joint

Bi region of solder joint

PCB Land

crack

Cracking in the solder and along the solder/IMC interface

crack

9

BGA Solder Joint Example

Paths to Reduce BiSn Solder Joint Embrittlement

✓ Resin added in the solder paste cures during

reflow soldering process

✓ Such resin containing pastes are called Joint

Reinforcement Pastes (JRP)

At Package level

Cured

Resin

At Solder Joint Level

✓ Resin Applied around the corners of Package and

cured either during or post reflow soldering

Resin Reinforcement

Corner Glue

• Various alternative strategies chosen by solder paste suppliers to modify the solder metallurgy for reduction in brittleness of mixed SAC-BiSnsolder joints

Ductile Bi-Sn Metallurgy

Ductile

BiSn

based

Region

➢ Both Paths considered for INEMI LTSPR Project 10

Solder Pastes EvaluatedCode

Paste

Category

Board

Assembly

Site

Liquidus

Temp, C# Name

D197 Raja Kunyit SAC 1,2 219.6

D166 Balik PulauBi-Sn

Baseline

1 142.8

D165 Chee Chee 2 139.0

D160 Teka 3 139.0

D158 Kan You

Ductile Bi-Sn

3 174.0

D200 Black Thorn 2 191.4

D175 Red Prawn 1 142.2

D164 Red Flesh 2 179.0

D24 Sultan 2 151.1

D163 Horlor

JRP Resin

Bi-Sn Based

1 139.0

D159 Golden Pillow 3 141.0

D145 Beserah 1 139.0

D123 Chanee 1 140.0

Distribution with

Four Categories

▪ 5 Ductile Bi-Sn

Metallurgy pastes

▪ 4 Resin Reinforced

Bi-Sn pastes

▪ 3 Bi-Sn baseline

pastes (0%, 0.4%,

1%Ag)

▪ 1 SAC paste to

serve as current

technology baseline

11

Board Test Vehicle Design and Components

Designation Description QntyDaisy

Chain

PCB6”x7”x0.040”, 8 layers, OSP

surface finish1 N/A

FC BGA16x24mm, 0.4mm nominal

pitch, SAC405 solder spheres2 Yes

LGA CPU

Socket

2066 pins, Bi-Sn-Ag solder

spheres1 No

LGA CPU

Socket

2066 pins, SAC305 solder

spheres1 No

QFN10x10mm, center ground pad,

72 terminations, 0.5mm pitch,2 Yes

QFP100L 14x14mm, 0.5mm pitch 2 Yes

QFP208L 28x28mm, 0.5mm pitch 2 Yes

Chip Cap 0402 Pad design with

4/6/8/12 mils body to

body spacing

20 Yes

Chip Cap 0201 20 Yes

Chip Cap 01005 20 Yes

SwitchTactile switch with SMT and

THM pins2 No

DDR4 THM Connector 1 No

USB3 THM Connector 1 No

7 inches

6 in

ch

es

1.0 mm thick, 8 layers, OSP Surface finish 12

Stencil Printing Evaluation Goal: To compare printing efficiency of the four solder paste categories

Stencil Materials:

Laser Etch Stainless Steel stencils and Squeegees

No paste transfer enhancement

Equipment Parameters Set Up: As specified by paste supplier, but tweaked

during process development

Measurement: Printed Paste Volume for 10th print after set up

Analysis: Transfer Efficiency and Coefficient of Variation for each area ratio

Results of pastes in each category lumped

together

Data from stencil apertures with the three

smallest Area Ratios presented

Component

Stencil Aperture

Area Ratio for

Lands

Chip 01005 0.50

FC BGA 0.59

Chip 0201 0.75

13

Transfer Efficiency of

Four Solder Paste CategoriesTrends Observed

• %TE decreases markedly with decrease in Area Ratio

• No significant decrease in %TE for the four categories down to 0.59 Area Ratio

• At Lowest Area Ratio of 0.5, JRP Resin reinforced pastes are significantly worse than the other three

• Resin impact is felt at the lowest area Ratio stencil apertures

14

Trends Observed

• Coefficient of Variation increase significantly from 0.59 to 0.5 stencil aperture area ratios

• JRP Resin reinforced solder paste has the higher coefficient of variation at the lowest area ratio aperture evaluated

• As in the case of the Transfer Efficiency, the impact of resin contained in JRP solder pastes is felt at the lowest area Ratio stencil apertures

Coefficient of Variation of

Four Solder Paste Categories

15

Typical Reflow Soldering Profiles-- For Each Category of Solder Paste --

Reflow

Soldering

Profile

Zone

Reflow Profile

Property

Comparison Between Paste

Categories

Initial Ramp Ramp Rate SAC is significantly lower

SoakTemperature SAC significant higher

Time No significant difference

Reflow

Peak Reflow

Temperature

SAC is significant higher

JRP resin is significant lower

Time above

Liquidus

JRP Resin is significant higher

Bi-Sn baseline is significant

lower

Cool Down Cooling Rate No significant difference

➢ Significant Differences in Key

Solder Reflow Profile Categories

for the four categories of Solder

Pastes Studied

16

Partial Wetting Solder joints Defects-- All for FCBGA component when using JRP Resin Pastes --

Partial wetting Void near T3 interface

IMC present

Separation at T3 interface

➢ These defects can arise due to

premature gelling of the resin

before the solder powder in the

paste has melted and wetted the

SAC solder spheres on the

package

➢ The initial Ramp Rate of the

reflow profile is critical in the

formation of this defect

Cured resin

D145 - Beserah D123 - Chanee D159 – Golden Pillow

D123 - Chanee

Cro

ss-s

ectio

ns

Dye

& P

ry

Partial wetting of PCB Land

17

Partial Wetting Defects – Potential MechanismTem

pera

ture

, C

Time, seconds

Reflow

Temperature

Plateau

Time above Liquidus/ Resin Curing Time, secs

➢ Trapezoidal Shape to the profile• Critical parameters: Initial Ramp Rate,

Reflow Temperature Plateau and Time

Above Liquidus/ Resin Curing time

Solder Joint

Formation

Resin Curing Phase

➢ Initial Ramp Rate is very important• Solder Paste has to melt, wet the lands and

the solder ball BEFORE the resin starts to

gel and its decrease its viscosity in its cure

progression

➢ If ramp rate is slow, resin will gel and

cure before the solder joint has fully

formed and lead to partial wetting

18

Hot Tearing Defects for FCBGA Solder Joints

Hot Tearing Observations

All defective solder joints were under

the Silicon Die Shadow

For D200 Solder Paste, the defect occurred

o at the PCB Land to Solder Interface

o D200 solder alloy had ~15% Bismuth content in solder,

with a large pasty range

For the other three solder pastes (D165, D158,

D160) the defect

▪ Occurred at the Package Substrate to Solder Interface

▪ Bismuth stratification observed at this interface

▪ These three solder paste gave the highest level of

bismuth mixing in the solder joints

D200(Black

Thorn)

D165(Cheh

Chee)

D158(Kan

You)

D160(Teka)

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‘GOOD’ SOLDER JOINTS FOR VARIOUS COMPONENTS

20

Paste

Category0402 Chip FCBGA

SKT R4

(SAC Sphere)

SKT R4

(BiSnAg

Sphere)

QFN

Termination

QFN Ground

Pad

DDR4 P-i-P

THM

Bi-Sn

Baseline

Ductile

Bi-Sn

JRP

Resin

Scoring Table for Each Rework Process Attribute

➢ For each Component Reworked an assessment of the ease of rework was made by assigning a score to

that particular rework attribute based on the scoring guidelines in table above

➢ Scores of 10 are the best and highest attainable

➢ Scores between 9 and 5 are termed moderate

➢ Scores below 4 are termed low

AttributeScore

1 3 5 7 10

B Part removal

Suction + High

force, cannot be

removed

Suction + High

force, to pry and

removed

Suction +

Medium force

to pry and

remove

Suction + low

force to pry and

remove

Removes on tool

suction alone

C Amount of material left >75% 50%-75% 25-50% 10-25% 0-10%

D No. of pads damaged >9 6～9 3～6 1～2 0

E No. of traces damaged >9 6～9 3～6 1～2 0

GTime for flux or resin residue

removal>10mins ≦10mins ≦8mins ≦5mins ≦3mins

H Time for solder wicking >10mins ≦10mins ≦8mins ≦5mins ≦3mins

I Solder mask damageSignificant damage

(>15% area of site)

Damage to 10～

15% area

Damage to 5～

10% area

Damage to <5%

areaNo damage

J Ergo Behavior Not Possible High Force Medium Force Low Force Minimal Force

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Rework Assessment Scores for Each Attribute

DowntrendDowntrend

Significantly

Less Damage

for low temp

pastes

Weak trend

No damage to

traces with low

temperature

soldersNo Effect for JRP

Resin Pastes

Lower

Scores

for JRP

Resin

Lower

Scores

for JRP

Resin

G - Time for flux (or resin) residue removal

➢ When compared to the higher melting SAC solder joints, the lower melting temperature of the solder joints

formed with Bi-Sn solder pastes

• facilitates easier part removal and site redress.

• Reduces Incidences of solder mask and trace damage

➢ When using resin-reinforced low-temperature JRP solder pastes, the presence of cured resin for solder joints

formed results in a longer site redress process.

22

SIR measurements for All Pastes

➢ All measured SIR values above 1x10 8 ohms level, which is lower limit

➢ Three pastes had significantly lower values than their control boards 23

▪ IPC-650 Method 2.6.3.7 using IPC-B-24 coupons

Summary iNEMI initiated the LTSRP project in 2015 to evaluate new Bi-Sn based solder pastes

Phase 1 of this project was to evaluate the SMT processability of these new pastes

Salient Results of this Phase 1 Evaluation are shown below

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Process /

Property

Solder Paste Type

Bi-Sn Baseline Ductile Bi-Sn JRP resin

Stencil Printability ➢ Equivalent to SAC even at <0.66 area ratio stencil apertures➢ Worse at the lowest Area

ratio (0.50) evaluated

Key Reflow Profile

Parameters

➢ Ramp-Soak-Peak Topography ➢ Trapezoidal Topography

➢ Initial Ramp Rate higher than SAC pastes but achievable in currently used ovens

➢ Soak Temperature lower than SAC ➢ No Soak Zone

➢ Reflow Temperature lower than SAC ➢ Reflow Temperature lowest

➢ Time above Liquidus (TAL) lower than SAC ➢ TAL longer than SAC

Summary(continued)

25

Process / PropertySolder Paste Type

Bi-Sn Baseline Ductile Bi-Sn JRP resin

Solder Joint Defects

➢ FCBGA: Hot Tearing under die shadow for

some solder pastes due to interaction of Bi

mixing in SAC ball, component substrate

warpage and cooling rate during reflow

soldering

➢ FCBGA and P-i-P THM:

Partial Wetting due to

premature resin curing

Rework(FCBGA and QFN)

➢ Easier part removal and site redress as well as

reduction in solder mask and trace damage

➢ Less damage to solder

mask and trace but site

Redress process takes

longer due to cured resin

Surface Insulation

Resistance (SIR)

➢ All Solder Pastes met the 1 x108 value when tested using IPC-650 Method

2.6.3.7 and B-24 coupons

➢ Mechanical Shock Robustness of PoP and FCBGA component solder joints formed with

these solder pastes in ongoing ; Accelerated Temperature Cycling Evaluation is planned

The authors acknowledge the engagement, effort and contribution

of the whole participating project team members: Intel, Celestica,

Wistron, IBM, Lenovo, Nokia, Flex, iST, Indium, Senju, Alpha,

Interflux, Eunow, Shinko, Nihon Superior, Heraeus, Dell, Keysight,

Abbott, Microsoft, Binghamton Univerisity and Purdue University.

We also appreciate the in-kind contribution of materials,

components and PCBs to our project study from ASE, FIT, Lotes,

Molex, Tripod, ITEQ, Tamura, Panasonic and Yincae.

Thank You!

Acknowledgment

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27

BACK UP

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SIR Measurement Method

▪ IPC-650 Method 2.6.3.7

Temperature,

C

Humidity,

% RH

Bias,

Volt

Frequency of

Measurement,

Mins

Total Duration of

Measurements,

Hours

40 (+/- 1) 90 (+/- 3) 5 30 168

Experimental Parameters

IPC-B-24 Coupon

• 4 nets

▪ Each Solder Paste Supplier Prepared the Coupons themselves for their

solder paste

▪ At least 2 Control Coupons and 3 Coupons with Solder Pastes applied

per Solder paste Evaluated

▪ SIR Test run and Measurements done at an independent testing house

29

SIR vs Time Measurements for Three Solder Pastes

SIR

, O

hm

s (

Lo

g S

ca

le)

Measurement Time, Hours

Paste Code Paste CategorySIR Trend

beyond 50 hours

Balik Pulau Bi-Sn Baseline Up

Chanee JRP Resin Down

Teka Bi-Sn Baseline Down

▪ These three pastes had significantly lower SIR

values for the coupons applied with solder paste

when compared to the control coupons

▪ But All measured values were above 1x 108 Ohms

lower limit

Limit

30