iNEMI Roadmap

Packaging and Component Substrates TWG

TWG Leaders:

W. R. Bottoms

William Chen

Presented by M. Tsuriya

Agenda

• Situation

– Everywhere in Electronics

– Evolution & Blooming

– Drivers Changing

• iNEMI Roadmap

– 21 TWGs, Outline, Cross TWG Activities

– Rapid Change in Requirement

– Material

– Single Chip Package

– WLP Complexity

– 2.5D/3D Integration

– Embedded Packages

– Future Co-Integrated SiP

• Conclusion

• Schedule

2

Everywhere in Electronics

3 Source: Yole at iNEMI Package workshop 2014

Evolution & Blooming Flowers

4 Source: Yole at iNEMI Package workshop 2014

• Requirement

– High Band Density

– Low Latency

– Expanded Data Processing

– Expanded data Storage

• Major Gaps

– Power (particularly Package Related)

– Thermal Management

– Cost

– Heterogeneous Integration

– Physical Density of Bandwidth

– Latency

Drivers Changing…..

5

This requires change in packages

Power Reduction

6

Thermal Management

7

Chapter Outline

Executive Summary

Introduction

Situation Analysis - bench mark state of the art

Packaging and Substrate Markets

Roadmap of Quantified Key Attribute Needs

• Single Chip Packaging

• Component Substrates

• Wafer Level Packaging

• 3D integration

• MEMS Packaging

• Automotive Electronics

• SiP Packaging

Gaps and Showstoppers

Recommendations for Potential Alternative Technologies

Critical Research Needs

Contributors

9

Cross TWG Activity

Technology Working Group / PEG 1 2 3 4 5 6 7 8 9

Semiconductor Technology x x

Final Assembly x

Interconnect PCB (Organic) x x

Modeling, Simulation & Design Tools x

Optoelectronics x x

Packaging & Component Substrates x

RF Components & Subsystems x x

Test, Inspection and Measurement x x

Thermal Management x x

Board Assembly x x

Passive Components x x

Interconnect Substrates (Ceramic) x

Electronic Connectors x x

MEMS/Sensors x

Photovoltaics x

Power Conversion Electronics x x

Office / Consumer x x

Portable / Wireless x x

Automotive x x

High-End Systems x x

Medical x x

Aerospace/Defense x x

10

All Materials will Change

11

Single-Chip Package Technology

Year of Production 2015 2017 2019 2021 2023 2025

Cost per Pin Minimum for Contract Assembly

(Cents/Pin)

Low-end, Low-cost package .20 -.34 .20-.30 .2-.27 .19-.25 .19-.25 .17-.24

Mobile Device Package 0.35 0.33 0.31 0.29 0.27 0.25

Memory 0.21 0.21 0.21 0.21 0.2 0.19

Cost-performance .46–.79 .42–.71 .37–.64 .33–.58 0.31–0.52 0.29–0.48

High-performance 1.21 1.09 0.99 0.89 0.81 0.75

Harsh .20–1.47 .20–1.33 .20–1.20 .19–1.08 .19–1.01 0.18–.97

Performance: chip-to-chip

Low-end, Low-cost package(MHz) 100 100 100 100 100 100

Mobile Device Package(MHz) 1000 1000 1000 1000 1000 1000

Memory(MHz) 3200 3200 3200 3200 3200 3200

Cost-performance (Gb/s) 30 40 50 60 70 80

High-performance (Gb/s) 30 40 50 60 70 80

Harsh 150 150 150 150 150 150

Performance: Pkg-to-Board

Low-end, Low-cost package(MHz) 100 100 100 100 100 100

Mobile Device Package(MHz) 1000 1000 1000 1000 1000 1000

Memory(MHz) 3200 3200 3200 3200 3200 3200

Cost-performance (Gb/s) 30 40 50 60 70 80

High-performance (Gb/s) 30 40 50 60 70 80

Manufacturable solutions exist, and are being optimized

Manufacturable solutions are known

Interim solutions are known

Manufacturable solutions are NOT known

12

The Rapid Change in Requirement is

Driving a Revolution in Packaging

13

• New Material

• New Package Architecture

– 2.5D Packages

– Wafer Level Packages

– System Integration in a Package (SiP)

• New Manufacturing Process

– Cu Pillar

– No Underfills

– Panel Level Processing

New Materials Will Be Required

• Cu interconnect

• Ultra Low k dielectrics

• High k dielectrics

• Organic semiconductors

• Green Materials

– Pb free

– Halogen free

But improvements are needed

Many are in use today Many are in development

Nanotubes

Nano Wires

Macromolecules

Nano Particles

Composite materials

14

WLP Complexity is Rising

15

2.5D/ 3D Integration

16

Future Co-Integrated SiP

Silicon Substrate with TSV interconnects and Si Waveguides

Photonic engine CMOS logic

Memory controller

DRAMDRAM

DRAM

DRAM

Power

ControllerMemory controller

DRAMFlash memory

DRAM

Flash memory Flash memoryFlash memory

Photonic/electronic Circuit Board

Electronics,

Photonics and

Plasmonics on an

SOI Substrate

Multiple voltage

regulators

to match power delivery

to each component to the

work in process

TSV memory stack,

direct bonding

interconnect, serdes

in controller

PCB with electronic

and photonic signals

with embedded

components

Large on-package

memory cache with

serdes in controller

17

Gap

• 3D TSV Integration

– Cost

– Test Strategy

– Thermal Management

– Signal and Power Integrity

– Handing Thin Die/Wafer

– Bonding

• System in Package

– Heterogeneous Integration

– Noise/Cross Talk

– Thermal Management

• Wafer Level Packaging

– Rapidly Increasing Complexity in WLP

– Contact Pitch

– Wafer2Wafer Bonding

Change Needed

• Close the gap between Chip and Substrate Wiring

• Packaging for Higher Current Density

• Flexible System Packaging

• 3D Packaging

• Low Cost Package Manufacturing

• Processes for Complex wafer Level Packages

• Photonic to the Package

New Package Architectures – Gaps & Challenges

18

2013 Edition 2015 Edition

Conclusion

System Integration at the package level is the only path to meet the cost and

Performance Requirement over the next ten years.

The definition of research needs for new materials, new architectures and

new manufacturing equipment and process is essential to ensure that

solutions are ready before Gaps become Showstoppers.

iNEMI roadmap is focused on meeting that needs.

19

• 3Q2013: Recruit Product Sector Champions, teams and refine data

charts/Begin 2015 Roadmap Newsletter & send 2013 PEG chapters

• 3/4Q13: Product Sector Champions Develop Emulators

• September 16, 2013 – Teleconference with P.E. Group Chairs

• September 27, 2013 Web based meeting TWG/PEG Chairs (key

attributes)

• October 16, 2013 – SMTAI Presentation on 2015 Plans

• October 17, 2013 - Roadmap PEG Kick-off with PEG/TWG/TC at

SMTAI

• 2013 Roadmap chapter, format, Exec. Summary emailed to each TWG

chair (Word) 1/3/2014

• Organizing Teleconference with TWG Chairs 1/10/2014:

• Feb 19,20 2014 PEG Workshop/TWG Kick-off – Agilent Technologies,

Santa Rosa, CA

• Product Sector Tables Complete – PEG Chapter rough drafts

written

• Cross cut issues are initially addressed

• May 13, 2014 Telecon With TWG Chairs, Preliminary PEG Chapters Due

• May 27, 2014 – N.A. RM WS - Open Roadmap TWG Presentations in

Orlando, FL (ECTC)

• June 11, 2014 European Roadmap Workshop/Webinar – 9:00 AM EDT

• June 18, 2014 – Asian Roadmap Workshop/Webinar – 8:00 PM EDT

• July 14, 2014 – TWG Drafts Due for TC Review

• August 20,21, 2014 – TC Face-to-Face Review with TWG Chairs at IBM,

RTP, N.C.

• September 22, 2014 Final Chapters of Roadmap Due

• October 2, 2014 TC Briefing/SMTA at SMTAI (Rosemont, Illinois)

• October 31, 2014 – Edit, Prepare Appendix A-D, Executive Summary

• November 20, 2014 – Go To “Press”

• December TBD, 2014 – Ship to Members

• April TBD, 2015 – Offer to Industry

• April TBD, 2015 – Global industry roadmap presentations via webinars

2015 Roadmap Schedule

2020

www.inemi.orgBill Bader

bill.bader@inemi.org

Grace O’Malley

gomalley@inemi.org