incremental placement algorithm for field programmable...
TRANSCRIPT
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Incremental Placement Algorithm for
Field Programmable Gate Arrays
David Leong
Advisor: Guy Lemieux University of British Columbia
Department of Electrical and Computer Engineering Vancouver, BC, Canada
© Copyright, David Leong, 2009
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Contributions • Incremental Placement Algorithm
– RePlace – Based on Placement Locality and Floor-planning – Multi-Region Algorithm
• Incremental Benchmark Circuits – Synthetic Benchmark Set – Physical Re-Synthesis Benchmark Set
• Findings – 50-260x speed up for Single-Region Benchmarks – 50-70x speed up for Multi-Region Benchmarks
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Motivation • Runtime for placement is
increasing with increasing FPGA sizes – 6 hours for 50,000 LUT circuit – Time == Engineering Cost
• System-on-Chip circuits are made of many subcomponents
• What if one part is modified? – Component reuse and
hierarchy – Multiple regions of the circuit
need incremental placement in order to support reuse
– Floor-planning for each circuit
• Physical Re-Synthesis Flows
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Incremental Placement Challenges
a2
b2
a3 a4
b3 b4
a5 a6
b5 b6
c1 c2
d1 d2
c3 c4
d3 d4
c5 c6
d5 d6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
1 2 3 4 5 6
1
2
3
4
5
6
IO IO IO IO IO IO
IO IO IO IO IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
• Example: – C4,C5,D4,D5 is a
modified sub-circuit – Can only fit <=4 CLBs in
the previous location – Free space is far away! – How do we fit >4 CLBs
quickly?
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RePlace Formulation
• Placement Locality – Modified Sub-Circuits should be “close” to
previous location – Floorplans
• Expanded “Virtual” Placement Grid – Literally thinking outside of the box!
• Efficient Shifting Algorithm – No CPU Intensive LE/CLB swapping and cost
evaluation
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RePlace Algorithm
Four Steps to Incremental Placement
1. Previous Placement and Floor-planning 2. Expanded “SuperGrid” Placement 3. Compaction Re-legalization 4. Simulated Annealing Refinement
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Previous Placement and Floor-planning
a2
b2
a3 a4
b3 b4
a5 a6
b5 b6
c1 c2
d1 d2
c3 c4
d3 d4
c5 c6
d5 d6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
1 2 3 4 5 6
1
2
3
4
5
6
IO IO IO IO IO IO
IO IO IO IO IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
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Expansion Phase (SuperGrid)
a2
b2
a3 a4
b3 b4 b5
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2
i3
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
c6
d6
a5IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO IO IO IO IO IO
IO IO IO IO IO IO
a2
b2
a3 a4
b3 b4 b5
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
c6
d6
a5IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO IO IO IO IO IO
IO IO IO IO IO IO
a2
b2
a3 a4
b3 b4
b5 a6
i7 b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
c6
d6
a5
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO IO IO IO IO IO
IO IO IO IO IO IO
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Compaction Phase
a2 a3
b2 b3
a4 b5
b4 i7
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
c6
d6
a5
a2 a3
b2 b3
a4 b5
b4 i7
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
c6
d6
a5
a2 a3
b2 b3
a4 b5
b4 i7
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
c6
d6
a5
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Compaction Phase
a2 a3
b2 b3
a4 b5
b4 i7
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
c6
d6
a5
a2 a3
b2 b3
a4 b5
b4 i7
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
c6
d6
a5
a2 a3
b2 b3
a4 b5
b4 i7
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
c6
d6
a5
a2 a3
b2 b3
a4 b5
b4 i7
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6
e1 e2 e3 d4
f3 f4
e5 e6
f5 f6
c6
d6
a5
a2 a3
b2 b3
a4 b5
b4 i7
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6e1 e2 e3 d4
f3 f4 e5 e6f5 f6
c6
d6
a5
a2 a3
b2 b3
a4 b5
b4 i7
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
i3 i6e1 e2 e3 d4
f3 f4 e5 e6f5 f6
c6 d6
a5
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Intermediate Solution a2 a3
b2 b3
a4 b5
b4 i7 a5
a6
b6
c1 c2
d1 d2
c3 i1
d3 i4
i2 i5
c6 d6
e1 e2
f3 f4
e3 d4
f5 f6
i3 i6
e5 e6
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Simulated Annealing Refinement
• Retuned VPR Simulated Annealing Algorithm – Lower Initial Temperature (44% temp) – Smaller Range Window – Lower Temperature degradation factor
(Alpha) – Variable number of swaps per temperature
range, 1-3x number of CLBs
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Benchmarking • Two Benchmark Sets • Single Region:
– Synthetic Flow • Simulates a design change
• Multi Region: – Physical Re-Synthesis flow
• Circuit unchanged, clustering or tech-mapping changed for optimizations
• Scaled to select multiple regions
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Single Region Synthetic Benchmark Set (SR)
• Developed by Dave Grant • Select a rectangular region on the placement grid
– Replace it with a synthetic clone – Clone can be same size, smaller, or larger (double size)
• Selection region of 2.5%, 5%, 10% of array size
Selected Area
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SR: Run-Time Results
SyntheticCircuit Syn - 2.5 Syn - 5 Syn - 10 Syn - 2.5d Syn - 5d
CLMA 72.0 70.8 73.5 80.3 70.0EX1010 77.6 75.0 77.0 69.0 76.2MISEX3 - - - - -PDC 80.6 64.0 68.7 84.4 68.1SPLA 75.7 55.5 44.8 84.0 51.2
Geometric Mean: 70.1
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SR: Channel Width Results
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Multi-Region Physical Resynthesis Benchmark (MR)
• Un/DoPack developed by Marvin, Guy and myself
• Iterative Congestion Reduction Algorithm – Select congested region – Spread out LUTs by
adding whitespace to each CLB
• Multiple Regions • Select all regions needed to
reduce CW by 10%, 20%, 30%, 40%, 50%
• 1/3 to 2/3 of the entire FPGA re-synthesized
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MR: Run-Time Results
Multi-RegionCircuit
MR - 50 MR - 40 MR - 30 MR - 20 MR -10
CLONE 62.8 70.0 68.3 61.5 75.9STDEV0 67.3 66.8 55.1 56.0 66.3STDEV010 47.1 59.7 68.6 66.5 58.5
Geometric Mean 63.0
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MR: Channel Width Results
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MR: Critical Path Results
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Contributions • Incremental Placement Algorithm
– RePlace – Based on Placement Locality and Floor-planning – Multi-Region Algorithm
• Incremental Benchmark Circuits – Synthetic Benchmark Set – Physical Re-Synthesis Benchmark Set
• Findings – 50-260x speed up for Single-Region Benchmarks – 50-70x speed up for Multi-Region Benchmarks
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Future Works
• Support for Macro Blocks • Support for Carry Chains • More Intelligent Shifting
– Still keep it simple • Integration with Commercial flows
– EG: QUIP
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End of Talk, Thank you!!
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Questions?