i.mx 6sololite applications processor reference...
TRANSCRIPT
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i.MX 6SoloLite ApplicationsProcessor Reference Manual
Document Number: IMX6SLRMRev. 2, 06/2015
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i.MX 6SoloLite Applications Processor Reference Manual, Rev. 2, 06/2015
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Contents
Section number Title Page
Chapter 1Introduction
1.1 About This Document...................................................................................................................................................123
1.1.1 Audience...................................................................................................................................................... 123
1.1.2 Organization.................................................................................................................................................123
1.1.3 Suggested Reading.......................................................................................................................................124
1.1.3.1 General Information.................................................................................................................124
1.1.3.2 Related Documentation............................................................................................................124
1.1.4 Conventions................................................................................................................................................. 124
1.1.5 Register Access............................................................................................................................................ 126
1.1.5.1 Register Diagram Field Access Type Legend..........................................................................126
1.1.5.2 Register Macro Usage..............................................................................................................126
1.1.6 Signal Conventions...................................................................................................................................... 127
1.1.7 Acronyms and Abbreviations.......................................................................................................................128
1.2 Introduction...................................................................................................................................................................129
1.3 Target Applications.......................................................................................................................................................130
1.4 Features.........................................................................................................................................................................130
1.5 Architectural Overview.................................................................................................................................................133
1.5.1 Simplified Block Diagram........................................................................................................................... 133
1.5.2 Architectural Partitioning.............................................................................................................................134
1.5.3 Endianness Support......................................................................................................................................136
1.5.4 Memory Interfaces....................................................................................................................................... 136
Chapter 2Memory Maps
2.1 Memory system overview.............................................................................................................................................137
2.2 ARM Platform Memory Map....................................................................................................................................... 137
2.3 DMA memory map.......................................................................................................................................................142
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Chapter 3Interrupts and DMA Events
3.1 Overview.......................................................................................................................................................................145
3.2 A9 interrupts................................................................................................................................................................. 145
3.3 SDMA event mapping.................................................................................................................................................. 149
Chapter 4External Signals and Pin Multiplexing
4.1 Overview.......................................................................................................................................................................151
4.1.1 Pin Assignments...........................................................................................................................................151
4.1.2 Muxing Options........................................................................................................................................... 199
Chapter 5Fusemap
5.1 Boot Fusemap............................................................................................................................................................... 243
5.2 Lock Fusemap...............................................................................................................................................................250
5.3 Fusemap Descriptions Table.........................................................................................................................................251
Chapter 6External Memory Controllers
6.1 Overview.......................................................................................................................................................................257
6.2 Multi-mode DDR controller (MMDC) overview and feature summary...................................................................... 257
6.3 EIM-PSRAM/NOR Flash controller overview.............................................................................................................258
6.3.1 EIM features.................................................................................................................................................259
6.3.2 EIM boot scenarios...................................................................................................................................... 260
6.3.3 EIM boot configuration................................................................................................................................260
6.3.4 OneNAND requirements..............................................................................................................................260
Chapter 7System Debug
7.1 Overview.......................................................................................................................................................................261
7.2 Chip and ARM Platform Debug Architecture.............................................................................................................. 261
7.2.1 Debug Features............................................................................................................................................ 262
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7.2.2 Debug System components..........................................................................................................................263
7.2.2.1 AMBA trace bus (ATB)...........................................................................................................264
7.2.2.2 ATB replicator......................................................................................................................... 264
7.2.2.3 Embedded Cross Triggering.................................................................................................... 264
7.2.2.3.1 Cross-Trigger Matrix (CTM)............................................................................265
7.2.2.3.2 Cross-Trigger Interface (CTI)...........................................................................266
7.2.2.4 Debug Access Port (DAP)....................................................................................................... 266
7.2.3 i.MX6SoloLite-Specific SJC Features.........................................................................................................267
7.2.3.1 JTAG Disable Mode................................................................................................................ 267
7.2.3.2 JTAG ID...................................................................................................................................267
7.2.4 System JTAG Controller - SJC....................................................................................................................268
7.2.5 System JTAG controller main features........................................................................................................268
7.2.6 SJC TAP Port............................................................................................................................................... 268
7.2.7 SJC main blocks...........................................................................................................................................268
7.3 Smart DMA (SDMA) core............................................................................................................................................269
7.3.1 SDMA On Chip Emulation Module (OnCE) Feature Summary................................................................. 269
7.3.1.1 Other SDMA Debug Functionality.......................................................................................... 270
7.3.1.2 SDMA ROM Patching............................................................................................................. 271
7.4 Miscellaneous............................................................................................................................................................... 271
7.4.1 Clock/Reset/Power.......................................................................................................................................271
7.5 Supported tools............................................................................................................................................................. 271
Chapter 8System Boot
8.1 Overview.......................................................................................................................................................................273
8.2 Boot modes................................................................................................................................................................... 274
8.2.1 Boot mode pin settings.................................................................................................................................274
8.2.2 High level boot sequence............................................................................................................................. 275
8.2.3 Boot From Fuses Mode (BOOT_MODE[1:0] = 00b)................................................................................. 276
8.2.4 Serial Downloader........................................................................................................................................277
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8.2.5 Internal Boot Mode (BOOT_MODE[1:0] = 0b10)......................................................................................278
8.2.6 Boot security settings................................................................................................................................... 279
8.3 Device Configuration....................................................................................................................................................279
8.3.1 Boot eFUSE Descriptions............................................................................................................................ 280
8.3.2 GPIO Boot Overrides...................................................................................................................................282
8.3.3 Device Configuration Data.......................................................................................................................... 284
8.4 Device Initialization......................................................................................................................................................284
8.4.1 Internal ROM /RAM memory map..............................................................................................................284
8.4.2 Boot Block Activation ................................................................................................................................ 285
8.4.3 Clocks at Boot Time.................................................................................................................................... 286
8.4.4 Enabling MMU and Caches.........................................................................................................................287
8.4.5 Exception Handling......................................................................................................................................288
8.4.6 Interrupt Handling During Boot...................................................................................................................289
8.4.7 Persistent Bits...............................................................................................................................................289
8.5 Boot Devices (Internal Boot)........................................................................................................................................ 289
8.5.1 NOR Flash/OneNAND using EIM Interface............................................................................................... 290
8.5.1.1 NOR Flash Boot Operation......................................................................................................290
8.5.1.2 OneNAND Flash Boot Operation............................................................................................ 291
8.5.1.3 IOMUX Configuration for EIM Devices.................................................................................291
8.5.2 Expansion Device........................................................................................................................................ 293
8.5.2.1 Expansion Device eFUSE Configuration................................................................................ 293
8.5.2.2 MMC and eMMC Boot............................................................................................................296
8.5.2.3 SD, eSD and SDXC................................................................................................................. 304
8.5.2.4 IOMUX Configuration for SD/MMC...................................................................................... 304
8.5.2.5 Redundant Boot Support for Expansion Device...................................................................... 305
8.5.3 Serial ROM through SPI and I2C................................................................................................................ 306
8.5.3.1 Serial ROM eFUSE Configuration.......................................................................................... 307
8.5.3.2 I2C Boot...................................................................................................................................308
8.5.3.2.1 I2C IOMUX Pin Configuration........................................................................ 309
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8.5.3.3 ECSPI Boot.............................................................................................................................. 309
8.5.3.3.1 ECSPI IOMUX Pin Configuration................................................................... 311
8.6 Program image..............................................................................................................................................................312
8.6.1 Image Vector Table and Boot Data..............................................................................................................312
8.6.1.1 Image Vector Table Structure.................................................................................................. 313
8.6.1.2 Boot Data Structure..................................................................................................................314
8.6.2 Device Configuration Data (DCD).............................................................................................................. 314
8.6.2.1 Write Data Command.............................................................................................................. 315
8.6.2.2 Check Data Command............................................................................................................. 317
8.6.2.3 NOP Command........................................................................................................................ 318
8.6.2.4 Unlock Command.................................................................................................................... 319
8.7 Plugin Image................................................................................................................................................................. 319
8.8 Serial Downloader........................................................................................................................................................ 320
8.8.1 USB..............................................................................................................................................................321
8.8.1.1 USB Configuration Details...................................................................................................... 322
8.8.1.2 IOMUX Configuration for USB.............................................................................................. 322
8.8.2 Serial Download protocol............................................................................................................................ 323
8.8.2.1 SDP Command.........................................................................................................................323
8.8.2.1.1 READ REGISTER............................................................................................323
8.8.2.1.2 WRITE REGISTER..........................................................................................324
8.8.2.1.3 WRITE_FILE................................................................................................... 325
8.8.2.1.4 ERROR_STATUS............................................................................................ 326
8.8.2.1.5 DCD WRITE.................................................................................................... 327
8.8.2.1.6 JUMP ADDRESS............................................................................................. 328
8.9 Recovery Devices......................................................................................................................................................... 328
8.10 USB Low Power Boot.................................................................................................................................................. 329
8.11 SD/MMC Manufacture Mode.......................................................................................................................................330
8.12 High Assurance Boot (HAB)........................................................................................................................................ 331
8.12.1 HAB API Vector Table Addresses.............................................................................................................. 332
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Chapter 9Multimedia
9.1 Display and graphics subsystem................................................................................................................................... 335
9.1.1 Electrophoretic Display Controller.............................................................................................................. 336
9.1.2 PiXel Pipeline.............................................................................................................................................. 337
9.1.3 LCD Interface.............................................................................................................................................. 337
9.1.4 CMOS Sensor Interface............................................................................................................................... 337
9.1.5 2D Graphics Processing Unit (GPU2Dv2).................................................................................................. 338
9.1.5.1 2D feature summary.................................................................................................................338
9.1.5.2 2D Performance....................................................................................................................... 339
9.1.5.3 2D Software............................................................................................................................. 339
9.1.6 Vector Graphics Processing Unit (GPUVGv2)........................................................................................... 340
9.1.6.1 Vector Graphics Features.........................................................................................................340
9.1.6.2 Vector Graphics Performance..................................................................................................340
9.1.6.3 Vector Graphics Software........................................................................................................340
9.2 Display / Sensor MIPI interfaces.................................................................................................................................. 341
9.2.1 Introduction..................................................................................................................................................341
9.2.2 DSI............................................................................................................................................................... 341
9.2.3 CSI-2............................................................................................................................................................ 343
9.2.4 D - PHY....................................................................................................................................................... 344
9.3 Audio subsystem...........................................................................................................................................................345
9.3.1 Audio subsystem module overview............................................................................................................. 345
9.3.2 Synchronous Audio Interface (SAI)............................................................................................................ 347
9.3.3 Sony/Philips Digital Interface (SPDIF)....................................................................................................... 347
Chapter 10Clock and Power Management
10.1 Introduction...................................................................................................................................................................351
10.2 Device Power Management Architecture Components................................................................................................351
10.2.1 Centralized components of clock generation and management...................................................................352
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10.2.2 Centralized components of power generation, distribution and management............................................. 353
10.2.3 Reset generation and distribution system.....................................................................................................353
10.2.4 Power and clock management framework................................................................................................... 353
10.3 Clock Management....................................................................................................................................................... 354
10.3.1 Centralized components of clock management system............................................................................... 354
10.3.2 Clock generation.......................................................................................................................................... 357
10.3.2.1 Crystal Oscillator (XTALOSC) .............................................................................................. 357
10.3.2.2 LVDS I/O ports........................................................................................................................357
10.3.2.3 PLLs......................................................................................................................................... 357
10.3.2.3.1 General PLL Control and Status Functions...................................................... 359
10.3.2.4 CCM ........................................................................................................................................360
10.3.2.5 Low Power Clock Gating unit (LPCG)....................................................................................360
10.3.3 Peripheral components of clock management system................................................................................. 361
10.3.3.1 Interface and functional clock..................................................................................................362
10.3.3.2 Block level clock management................................................................................................ 362
10.3.3.2.1 Master clock protocol....................................................................................... 363
10.3.3.2.2 Slave clock protocol..........................................................................................363
10.3.3.3 Clock Domain(s)...................................................................................................................... 364
10.3.3.4 Domain level clock management.............................................................................................364
10.3.3.5 Domain dependencies.............................................................................................................. 364
10.4 Power management.......................................................................................................................................................364
10.4.1 Centralized Components of Power Management System............................................................................365
10.4.1.1 Integrated PMU........................................................................................................................365
10.4.1.1.1 Digital LDO Regulators....................................................................................366
10.4.1.1.2 Analog LDO regulators.....................................................................................367
10.4.1.1.3 USB LDO..........................................................................................................367
10.4.1.1.4 SNVS regulator.................................................................................................368
10.4.1.1.5 Reverse well biasing......................................................................................... 368
10.4.1.2 GPC - General Power Controller............................................................................................. 368
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10.4.1.3 SRC - System reset Controller................................................................................................. 369
10.4.1.4 Power domain(s)...................................................................................................................... 369
10.4.1.4.1 Power distribution ............................................................................................370
10.4.1.4.2 Domain Memory and domain logic state retention in case of Power Gating... 371
10.4.1.4.3 Power Gating Domain Management.................................................................372
10.4.1.4.3.1 Cortex-A9 Core Platform......................................................... 372
10.4.1.4.3.2 GPU2D..................................................................................... 373
10.4.1.4.3.3 SoC........................................................................................... 373
10.4.1.4.4 Power Gating domain dependencies.................................................................374
10.4.1.5 Voltage domains...................................................................................................................... 374
10.4.1.6 Voltage domain management...................................................................................................375
10.4.1.6.1 Dynamic............................................................................................................375
10.4.1.6.1.1 DVFS........................................................................................375
10.4.1.6.1.2 Voltage Scaling........................................................................ 376
10.4.1.6.2 Static ................................................................................................................ 376
10.4.1.6.2.1 Standby Leakage reduction (SLR)........................................... 376
10.4.1.6.3 Voltage domain dependencies.......................................................................... 377
10.4.1.6.4 IO voltage .........................................................................................................377
10.4.1.7 System domains layout............................................................................................................ 377
10.4.2 Power management techniques....................................................................................................................379
10.4.2.1 Power saving techniques..........................................................................................................380
10.4.2.2 Thermal-aware power management.........................................................................................380
10.4.2.3 Peripheral Power management.................................................................................................381
10.4.2.3.1 Main memory power management................................................................... 381
10.4.2.3.2 Video-Graphics system power management.................................................... 382
10.4.2.3.3 IO power reduction........................................................................................... 382
10.4.3 Examples of External Power Supply Interfacing in the i.MX 6SoloLite based systems ............................383
10.5 ONOFF (Button)...........................................................................................................................................................387
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Chapter 11System Security
11.1 Overview.......................................................................................................................................................................389
11.2 Central Security Unit (CSU).........................................................................................................................................391
11.2.1 CSU Overview............................................................................................................................................. 391
11.2.2 CSU Features............................................................................................................................................... 391
11.2.3 CSU Functional Description........................................................................................................................ 392
11.2.3.1 CSU Peripheral Access Policy.................................................................................................392
11.3 Secure Non-Volatile Storage (SNVS).......................................................................................................................... 393
11.3.1 SNVS Overview...........................................................................................................................................393
11.3.2 Tamper Detection.........................................................................................................................................394
11.4 Data Co-Processor (DCP)............................................................................................................................................. 394
11.5 High Assurance Boot (HAB)........................................................................................................................................ 394
11.6 System JTAG Controller (SJC).................................................................................................................................... 395
Chapter 12ARM Cortex A9 MPCore Platform (ARM)
12.1 Overview.......................................................................................................................................................................397
12.2 External Signals............................................................................................................................................................ 397
12.3 Platform configuration..................................................................................................................................................399
12.3.1 Platform and SCU configuration..................................................................................................................399
12.3.2 Core configuration....................................................................................................................................... 399
12.3.3 PL310 L2 Cache configuration.................................................................................................................... 400
12.3.4 Endian Modes.............................................................................................................................................. 400
12.3.5 Memory Parity error support .......................................................................................................................401
12.4 Performance and Power................................................................................................................................................ 401
12.4.1 Low-Power design....................................................................................................................................... 401
12.4.1.1 SRPG (State Retention Power Gating).................................................................................... 401
12.4.1.2 Dynamic Voltage and Frequency Scaling (DVFS)..................................................................402
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12.4.2 Clocks, frequency goals............................................................................................................................... 402
12.4.2.1 ARM Clock.............................................................................................................................. 402
12.4.2.2 Bus Clocks............................................................................................................................... 402
12.4.2.3 Debug Clocks...........................................................................................................................402
12.5 Core Platform Sub-Blocks details.................................................................................................................................403
12.5.1 ARM Cortex A9 MPCore Processor............................................................................................................403
12.5.2 Media Processing Engine (MPE - NEON).................................................................................................. 403
12.5.3 Generic Interrupt Controller (GIC).............................................................................................................. 404
12.5.3.1 Interrupt Controller Features....................................................................................................404
12.5.3.2 About the Interrupt Controller................................................................................................. 404
12.5.3.3 Interrupt Controller Clock frequency.......................................................................................404
12.5.3.4 TrustZone support.................................................................................................................... 404
12.5.4 Instruction and data caches (L1).................................................................................................................. 405
12.5.4.1 L1 features................................................................................................................................405
12.5.5 L2 Cache and controller (PL310).................................................................................................................405
12.6 Debug and Trace Sub-blocks (CoreSight components)................................................................................................405
12.6.1 Debug Access Port (DAP) .......................................................................................................................... 406
12.6.2 Program Trace Macrocell (PTM).................................................................................................................406
12.6.2.1 Program Flow Trace (PFT)...................................................................................................... 407
12.6.3 Cross Trigger Interface (CTI)...................................................................................................................... 408
12.6.4 Embedded Trace Buffer (ETB)....................................................................................................................408
12.6.4.1 AMBA Trace Bus (ATB) Replicator ...................................................................................... 408
Chapter 13AHB to IP Bridge (AIPSTZ)
13.1 Overview.......................................................................................................................................................................409
13.1.1 Features........................................................................................................................................................ 409
13.2 Clocks........................................................................................................................................................................... 409
13.3 Functional Description..................................................................................................................................................410
13.4 Access Protections........................................................................................................................................................ 411
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13.5 Access Support..............................................................................................................................................................411
13.6 Initialization Information..............................................................................................................................................412
13.6.1 Security Block..............................................................................................................................................412
13.7 AIPSTZ Memory Map/Register Definition..................................................................................................................413
13.7.1 Master Priviledge Registers (AIPSTZx_MPR)............................................................................................414
13.7.2 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR)....................................................416
13.7.3 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR1)..................................................419
13.7.4 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR2)..................................................422
13.7.5 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR3)..................................................425
13.7.6 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR4)..................................................428
Chapter 14Digital Audio Multiplexer (AUDMUX)
14.1 Overview.......................................................................................................................................................................431
14.1.1 Features........................................................................................................................................................ 433
14.1.2 Modes and Operations................................................................................................................................. 433
14.2 External Signals............................................................................................................................................................ 433
14.3 Clocks........................................................................................................................................................................... 435
14.3.1 Clock Inputs................................................................................................................................................. 435
14.3.2 Clock Diagram............................................................................................................................................. 435
14.3.3 Clocking Restrictions...................................................................................................................................436
14.4 Default Register Configuration.....................................................................................................................................436
14.4.1 Default Port Configuration...........................................................................................................................436
14.5 Functional Description..................................................................................................................................................437
14.5.1 Operating Modes..........................................................................................................................................437
14.5.1.1 Port Receive Data Modes.........................................................................................................438
14.5.1.1.1 Normal Mode....................................................................................................439
14.5.1.1.2 Internal Network Mode.....................................................................................440
14.5.1.1.3 Transmit Data Output Enable Assertion........................................................... 446
14.5.1.2 Tx/Rx Switch and External Network Mode.............................................................................447
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14.5.1.3 Timing Modes.......................................................................................................................... 448
14.5.1.3.1 Synchronous Mode (4-Wire Interface)............................................................. 448
14.5.1.3.2 Asynchronous Mode (6-Wire Interface)...........................................................450
14.5.2 Connectivity Between Ports.........................................................................................................................453
14.5.2.1 Internal Port to External Port Connectivity..............................................................................454
14.5.2.2 External Port to External Port Connectivity............................................................................ 455
14.5.2.3 Internal Port to Internal Port Connectivity...............................................................................455
14.5.2.4 Loopback Connectivity............................................................................................................ 456
14.6 AUDMUX Memory Map/Register Definition..............................................................................................................456
14.6.1 Port Timing Control Register 1 (AUDMUX_PTCR1)................................................................................ 457
14.6.2 Port Data Control Register 1 (AUDMUX_PDCR1)....................................................................................459
14.6.3 Port Timing Control Register 2 (AUDMUX_PTCR2)................................................................................ 460
14.6.4 Port Data Control Register 2 (AUDMUX_PDCR2)....................................................................................462
14.6.5 Port Timing Control Register 3 (AUDMUX_PTCR3)................................................................................ 463
14.6.6 Port Data Control Register 3 (AUDMUX_PDCR3)....................................................................................465
14.6.7 Port Timing Control Register 4 (AUDMUX_PTCR4)................................................................................ 466
14.6.8 Port Data Control Register 4 (AUDMUX_PDCR4)....................................................................................468
14.6.9 Port Timing Control Register 5 (AUDMUX_PTCR5)................................................................................ 469
14.6.10 Port Data Control Register 5 (AUDMUX_PDCR5)....................................................................................471
14.6.11 Port Timing Control Register 6 (AUDMUX_PTCR6)................................................................................ 472
14.6.12 Port Data Control Register 6 (AUDMUX_PDCR6)....................................................................................474
14.6.13 Port Timing Control Register 7 (AUDMUX_PTCR7)................................................................................ 475
14.6.14 Port Data Control Register 7 (AUDMUX_PDCR7)....................................................................................477
Chapter 15Clock Controller Module (CCM)
15.1 Overview.......................................................................................................................................................................479
15.1.1 Features........................................................................................................................................................ 479
15.1.2 CCM Block Diagram................................................................................................................................... 480
15.2 External Signals............................................................................................................................................................ 482
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15.3 CCM Clock Tree...........................................................................................................................................................482
15.4 System Clocks...............................................................................................................................................................484
15.5 Functional Description..................................................................................................................................................491
15.5.1 Clock Generation......................................................................................................................................... 491
15.5.1.1 External Low Frequency Clock - CKIL ..................................................................................491
15.5.1.1.1 CKIL synchronizing to IPG_CLK....................................................................491
15.5.1.2 External High Frequency Clock - CKIH and internal oscillator..............................................491
15.5.1.3 PLL reference clock................................................................................................................. 492
15.5.1.3.1 ARM PLL......................................................................................................... 492
15.5.1.3.2 USB PLLs......................................................................................................... 492
15.5.1.3.3 System PLL.......................................................................................................493
15.5.1.3.4 Audio / Video PLL............................................................................................493
15.5.1.3.5 Ethernet PLL.....................................................................................................493
15.5.1.4 Phase Fractional Dividers (PFD)............................................................................................. 493
15.5.1.5 CCM internal clock generation................................................................................................ 494
15.5.1.5.1 Clock Switcher..................................................................................................495
15.5.1.5.2 PLL bypass procedure.......................................................................................497
15.5.1.5.3 PLL clock change............................................................................................. 497
15.5.1.5.4 Clock Root Generator....................................................................................... 497
15.5.1.5.5 Initial values controlled by the System JTAG Controller (SJC).......................506
15.5.1.5.6 Divider change handshake................................................................................ 507
15.5.1.6 Disabling / Enabling PLLs.......................................................................................................507
15.5.1.7 Clock Switching Multiplexers................................................................................................. 507
15.5.1.8 Low Power Clock Gating module (LPCG)..............................................................................509
15.5.1.8.1 MMDC handshake............................................................................................510
15.5.2 DVFS support.............................................................................................................................................. 511
15.5.3 Power modes................................................................................................................................................ 511
15.5.3.1 RUN mode............................................................................................................................... 511
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15.5.3.2 WAIT mode............................................................................................................................. 511
15.5.3.2.1 Entering WAIT mode ...................................................................................... 511
15.5.3.2.2 Exiting WAIT mode ........................................................................................ 512
15.5.3.3 STOP mode.............................................................................................................................. 512
15.5.3.3.1 Entering STOP mode ....................................................................................... 512
15.5.3.3.2 Exiting STOP mode.......................................................................................... 513
15.6 CCM Memory Map/Register Definition.......................................................................................................................514
15.6.1 CCM Control Register (CCM_CCR)...........................................................................................................516
15.6.2 CCM Control Divider Register (CCM_CCDR)...........................................................................................518
15.6.3 CCM Status Register (CCM_CSR)..............................................................................................................519
15.6.4 CCM Clock Switcher Register (CCM_CCSR)............................................................................................520
15.6.5 CCM Arm Clock Root Register (CCM_CACRR).......................................................................................522
15.6.6 CCM Bus Clock Divider Register (CCM_CBCDR)................................................................................... 523
15.6.7 CCM Bus Clock Multiplexer Register (CCM_CBCMR)............................................................................ 525
15.6.8 CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1).................................................................... 528
15.6.9 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2).................................................................... 531
15.6.10 CCM Serial Clock Divider Register 1 (CCM_CSCDR1)............................................................................531
15.6.11 CCM SSI1 Clock Divider Register (CCM_CS1CDR)................................................................................ 534
15.6.12 CCM SSI2 Clock Divider Register (CCM_CS2CDR)................................................................................ 536
15.6.13 CCM D1 Clock Divider Register (CCM_CDCDR).................................................................................... 537
15.6.14 CCM HSC Clock Divider Register (CCM_CHSCCDR).............................................................................539
15.6.15 CCM Serial Clock Divider Register 2 (CCM_CSCDR2)............................................................................541
15.6.16 CCM Serial Clock Divider Register 3 (CCM_CSCDR3)............................................................................543
15.6.17 CCM Wakeup Detector Register (CCM_CWDR).......................................................................................544
15.6.17 CCM Divider Handshake In-Process Register (CCM_CDHIPR)............................................................... 545
15.6.18 CCM Low Power Control Register (CCM_CLPCR).................................................................................. 548
15.6.19 CCM Interrupt Status Register (CCM_CISR)............................................................................................. 550
15.6.20 CCM Interrupt Mask Register (CCM_CIMR).............................................................................................553
15.6.21 CCM Clock Output Source Register (CCM_CCOSR)................................................................................ 555
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15.6.22 CCM General Purpose Register (CCM_CGPR)..........................................................................................557
15.6.23 CCM Clock Gating Register 0 (CCM_CCGR0)..........................................................................................558
15.6.24 CCM Clock Gating Register 1 (CCM_CCGR1)..........................................................................................560
15.6.25 CCM Clock Gating Register 2 (CCM_CCGR2)..........................................................................................561
15.6.26 CCM Clock Gating Register 3 (CCM_CCGR3)..........................................................................................563
15.6.27 CCM Clock Gating Register 4 (CCM_CCGR4)..........................................................................................564
15.6.28 CCM Clock Gating Register 5 (CCM_CCGR5)..........................................................................................565
15.6.29 CCM Clock Gating Register 6 (CCM_CCGR6)..........................................................................................567
15.6.30 CCM Module Enable Overide Register (CCM_CMEOR).......................................................................... 568
15.7 CCM Analog Memory Map/Register Definition..........................................................................................................569
15.7.1 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARMn)....................................................... 573
15.7.2 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1n)......................................575
15.7.3 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2n)......................................577
15.7.4 Analog System PLL Control Register (CCM_ANALOG_PLL_SYSn)......................................................579
15.7.5 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn)...................................................581
15.7.6 Numerator of Audio PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_AUDIO_NUM)....583
15.7.7 Denominator of Audio PLL Fractional Loop Divider Register
(CCM_ANALOG_PLL_AUDIO_DENOM)...............................................................................................584
15.7.8 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEOn)................................................... 585
15.7.9 Numerator of Video PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_VIDEO_NUM).....587
15.7.10 Denominator of Video PLL Fractional Loop Divider Register
(CCM_ANALOG_PLL_VIDEO_DENOM)............................................................................................... 588
15.7.11 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENETn).................................................... 589
15.7.12 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480n)......... 591
15.7.13 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528n)......... 593
15.7.14 Miscellaneous Register 0 (CCM_ANALOG_MISC0n).............................................................................. 596
15.7.15 Miscellaneous Register 1 (CCM_ANALOG_MISC1n).............................................................................. 600
15.7.16 Miscellaneous Register 2 (CCM_ANALOG_MISC2n).............................................................................. 603
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Chapter 16CMOS Sensor Interface (CSI)
16.1 Overview.......................................................................................................................................................................609
16.2 External Signals............................................................................................................................................................ 610
16.3 Clocks........................................................................................................................................................................... 611
16.4 Principles of Operation................................................................................................................................................. 612
16.4.1 Data Transfer with the Embedded DMA Controllers.................................................................................. 613
16.4.2 Gated Clock Mode....................................................................................................................................... 615
16.4.3 Non-Gated Clock Mode............................................................................................................................... 615
16.4.4 CCIR656 Interlace Mode............................................................................................................................. 616
16.4.5 CCIR656 Progressive Mode........................................................................................................................ 618
16.4.6 Error Correction for CCIR656 Coding........................................................................................................ 619
16.5 Interrupt Generation......................................................................................................................................................619
16.5.1 Start Of Frame Interrupt (SOF_INT)........................................................................................................... 620
16.5.2 End Of Frame Interrupt (EOF_INT)............................................................................................................620
16.5.3 Change Of Field Interrupt (COF_INT)........................................................................................................620
16.5.4 CCIR Error Interrupt (ECC_INT)................................................................................................................620
16.5.5 RxFIFO Full Interrupt (RxFF_INT)............................................................................................................ 621
16.5.6 Statistic FIFO Full Interrupt (STATFF_INT)..............................................................................................621
16.5.7 RxFIFO Overrun Interrupt (RFF_OR_INT)................................................................................................ 621
16.5.8 Statistic FIFO Overrun Interrupt (SFF_OR_INT)....................................................................................... 621
16.5.9 Frame Buffer1 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB1).................................................621
16.5.10 Frame Buffer2 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB2).................................................621
16.5.11 Statistic FIFO DMA Transfer Done Interrupt (DMA_TSF_DONE_SFF)..................................................622
16.5.12 AHB Bus Response Error Interrupt (HRESP_ERR_INT)...........................................................................622
16.6 Data Packing Style........................................................................................................................................................622
16.6.1 RX FIFO Path.............................................................................................................................................. 623
16.6.1.1 Bayer Data................................................................................................................................623
16.6.1.2 RGB565 Data...........................................................................................................................623
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16.6.1.3 RGB888 Data...........................................................................................................................624
16.6.2 STAT FIFO Path..........................................................................................................................................626
16.7 CSI Memory Map/Register Definition......................................................................................................................... 626
16.7.1 CSI Control Register 1 (CSI_CSICR1)....................................................................................................... 627
16.7.2 CSI Control Register 2 (CSI_CSICR2)....................................................................................................... 631
16.7.3 CSI Control Register 3 (CSI_CSICR3)....................................................................................................... 633
16.7.4 CSI Statistic FIFO Register (CSI_CSISTATFIFO).....................................................................................635
16.7.5 CSI RX FIFO Register (CSI_CSIRFIFO)................................................................................................... 636
16.7.6 CSI RX Count Register (CSI_CSIRXCNT)................................................................................................ 636
16.7.7 CSI Status Register (CSI_CSISR)............................................................................................................... 637
16.7.8 CSI DMA Start Address Register - for STATFIFO (CSI_CSIDMASA_STATFIFO)............................... 640
16.7.9 CSI DMA Transfer Size Register - for STATFIFO (CSI_CSIDMATS_STATFIFO)................................640
16.7.10 CSI DMA Start Address Register - for Frame Buffer1 (CSI_CSIDMASA_FB1)...................................... 641
16.7.11 CSI DMA Transfer Size Register - for Frame Buffer2 (CSI_CSIDMASA_FB2)...................................... 642
16.7.12 CSI Frame Buffer Parameter Register (CSI_CSIFBUF_PARA)................................................................ 642
16.7.13 CSI Image Parameter Register (CSI_CSIIMAG_PARA)........................................................................... 643
Chapter 17Debug Monitor (DBGMON)
17.1 Overview.......................................................................................................................................................................645
17.1.1 Features Summary........................................................................................................................................646
17.1.2 Functional Description.................................................................................................................................646
17.1.3 Application...................................................................................................................................................646
17.2 DBGMON Memory Map/Register Definition..............................................................................................................647
17.2.1 HW_DBGMON_CTRL (DBGMON_HW_DBGMON_CTRL).................................................................648
17.2.2 HW_DBGMON_MASTER_EN (DBGMON_HW_DBGMON_MASTER_EN)...................................... 650
17.2.3 HW_DBGMON_IRQ (DBGMON_HW_DBGMON_IRQ)........................................................................651
17.2.4 HW_DBGMON_TRAP_ADDR_LOW (DBGMON_HW_DBGMON_TRAP_ADDR_LOW)................ 652
17.2.5 HW_DBGMON_TRAP_ADDR_HIGH (DBGMON_HW_DBGMON_TRAP_ADDR_HIGH).............. 652
17.2.6 HW_DBGMON_TRAP_ID (DBGMON_HW_DBGMON_TRAP_ID).................................................... 653
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17.2.7 HW_DBGMON_SNVS_ADDR (DBGMON_HW_DBGMON_SNVS_ADDR)...................................... 653
17.2.8 HW_DBGMON_SNVS_DATA (DBGMON_HW_DBGMON_SNVS_DATA).......................................654
17.2.9 HW_DBGMON_SNVS_INFO (DBGMON_HW_DBGMON_SNVS_INFO).......................................... 655
17.2.10 HW_DBGMON_VERSION (DBGMON_HW_DBGMON_VERSION)...................................................656
Chapter 18Data Co-Processor (DCP)
18.1 Overview.......................................................................................................................................................................657
18.1.1 DCP Limitations for Software..................................................................................................................... 659
18.2 Clocks........................................................................................................................................................................... 660
18.3 Operation.......................................................................................................................................................................660
18.3.1 Memory Copy, Blit, and Fill Functionality..................................................................................................661
18.3.2 Advanced Encryption Standard (AES)........................................................................................................ 661
18.3.2.1 Key Storage..............................................................................................................................661
18.3.2.2 AES OTP Key..........................................................................................................................662
18.3.2.3 Encryption Modes.................................................................................................................... 662
18.3.3 Hashing........................................................................................................................................................ 664
18.3.4 One Time Programmable (OTP) Key.......................................................................................................... 665
18.3.5 Managing DCP Channel Arbitration and Performance............................................................................... 665
18.3.5.1 DCP Arbitration....................................................................................................................... 666
18.3.5.2 Channel Recovery Timers........................................................................................................666
18.3.6 Programming Channel Operations...............................................................................................................667
18.3.6.1 Virtual Channels...................................................................................................................... 667
18.3.6.2 Context Switching....................................................................................................................668
18.3.6.3 Working with Semaphores.......................................................................................................669
18.3.6.4 Work Packet Structure............................................................................................................. 670
18.3.6.4.1 Next Command Address Field..........................................................................670
18.3.6.4.2 Control0 Field................................................................................................... 671
18.3.6.4.3 Control1 Field................................................................................................... 673
18.3.6.4.4 Source Buffer.................................................................................................... 673
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18.3.6.4.5 Destination Buffer.............................................................................................674
18.3.6.4.6 Buffer Size Field...............................................................................................674
18.3.6.4.7 Payload Pointer................................................................................................. 675
18.3.6.4.8 Status.................................................................................................................675
18.3.6.4.9 Payload..............................................................................................................676
18.3.7 Programming DCP Functions...................................................................................................................... 677
18.3.7.1 Basic Memory Copy Programming Example.......................................................................... 677
18.3.7.2 Basic Hash Operation Programming Example........................................................................ 678
18.3.7.3 Basic Cipher Operation Programming Example......................................................................679
18.3.7.4 Multi-Buffer Scatter/Gather Cipher and Hash Operation Programming Example..................681
18.4 DCP Memory Map/Register Definition........................................................................................................................684
18.4.1 DCP Control Register 0 (DCP_CTRL)........................................................................................................685
18.4.2 DCP Status Register (DCP_STAT)............................................................................................................. 688
18.4.3 DCP Channel Control Register (DCP_CHANNELCTRL)......................................................................... 690
18.4.4 DCP Capability 0 Register (DCP_CAPABILITY0)....................................................................................692
18.4.5 DCP Capability 1 Register (DCP_CAPABILITY1)....................................................................................693
18.4.6 DCP Context Buffer Pointer (DCP_CONTEXT)........................................................................................ 693
18.4.7 DCP Key Index (DCP_KEY)...................................................................................................................... 694
18.4.8 DCP Key Data (DCP_KEYDATA).............................................................................................................695
18.4.9 DCP Work Packet 0 Status Register (DCP_PACKET0)............................................................................. 696
18.4.10 DCP Work Packet 1 Status Register (DCP_PACKET1)............................................................................. 696
18.4.11 DCP Work Packet 2 Status Register (DCP_PACKET2)............................................................................. 700
18.4.12 DCP Work Packet 3 Status Register (DCP_PACKET3)............................................................................. 701
18.4.13 DCP Work Packet 4 Status Register (DCP_PACKET4)............................................................................. 701
18.4.14 DCP Work Packet 5 Status Register (DCP_PACKET5)............................................................................. 702
18.4.15 DCP Work Packet 6 Status Register (DCP_PACKET6)............................................................................. 702
18.4.16 DCP Channel 0 Command Pointer Address Register (DCP_CH0CMDPTR)............................................ 703
18.4.17 DCP Channel 0 Semaphore Register (DCP_CH0SEMA)........................................................................... 704
18.4.18 DCP Channel 0 Status Register (DCP_CH0STAT).................................................................................... 705
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18.4.19 DCP Channel 0 Options Register (DCP_CH0OPTS)..................................................................................707
18.4.20 DCP Channel 1 Command Pointer Address Register (DCP_CH1CMDPTR)............................................ 708
18.4.21 DCP Channel 1 Semaphore Register (DCP_CH1SEMA)........................................................................... 709
18.4.22 DCP Channel 1 Status Register (DCP_CH1STAT).................................................................................... 710
18.4.23 DCP Channel 1 Options Register (DCP_CH1OPTS)..................................................................................712
18.4.24 DCP Channel 2 Command Pointer Address Register (DCP_CH2CMDPTR)............................................ 713
18.4.25 DCP Channel 2 Semaphore Register (DCP_CH2SEMA)........................................................................... 714
18.4.26 DCP Channel 2 Status Register (DCP_CH2STAT).................................................................................... 715
18.4.27 DCP Channel 2 Options Register (DCP_CH2OPTS)..................................................................................717
18.4.28 DCP Channel 3 Command Pointer Address Register (DCP_CH3CMDPTR)............................................ 718
18.4.29 DCP Channel 3 Semaphore Register (DCP_CH3SEMA)........................................................................... 719
18.4.30 DCP Channel 3 Status Register (DCP_CH3STAT).................................................................................... 720
18.4.31 DCP Channel 3 Options Register (DCP_CH3OPTS)..................................................................................722
18.4.32 DCP Debug Select Register (DCP_DBGSELECT).....................................................................................722
18.4.33 DCP Debug Data Register (DCP_DBGDATA).......................................................................................... 723
18.4.34 DCP Page Table Register (DCP_PAGETABLE)........................................................................................723
18.4.35 DCP Version Register (DCP_VERSION)................................................................................................... 724
Chapter 19Enhanced Configurable SPI (ECSPI)
19.1 Overview.......................................................................................................................................................................725
19.1.1 Features........................................................................................................................................................ 726
19.1.2 Modes and Operations................................................................................................................................. 726
19.2 External Signals............................................................................................................................................................ 727
19.3 Clocks........................................................................................................................................................................... 730
19.4 Functional Description..................................................................................................................................................730
19.4.1 Master Mode................................................................................................................................................ 731
19.4.2 Slave Mode.................................................................................................................................................. 731
19.4.3 Low Power Modes....................................................................................................................................... 732
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19.4.4 Operations.................................................................................................................................................... 732
19.4.4.1 Typical Master Mode............................................................................................................... 732
19.4.4.1.1 Master Mode with SPI_RDY............................................................................733
19.4.4.1.2 Master Mode with Wait States..........................................................................735
19.4.4.1.3 Master Mode with SS_CTL[3:0] Control.........................................................735
19.4.4.1.4 Master Mode with Phase Control..................................................................... 736
19.4.4.2 Typical Slave Mode................................................................................................................. 737
19.4.5 Reset.............................................................................................................................................................738
19.4.6 Interrupts...................................................................................................................................................... 738
19.4.7 DMA ........................................................................................................................................................... 739
19.4.8 Byte Order....................................................................................................................................................740
19.5 Initialization.................................................................................................................................................................. 741
19.6 Applications.................................................................................................................................................................. 741
19.7 ECSPI Memory Map/Register Definition.....................................................................................................................742
19.7.1 Receive Data Register (ECSPIx_RXDATA)...............................................................................................744
19.7.2 Transmit Data Register (ECSPIx_TXDATA)..............................................................................................745
19.7.3 Control Register (ECSPIx_CONREG)........................................................................................................ 745
19.7.4 Config Register (ECSPIx_CONFIGREG)................................................................................................... 748
19.7.5 Interrupt Control Register (ECSPIx_INTREG)........................................................................................... 750
19.7.6 DMA Control Register (ECSPIx_DMAREG)............................................................................................. 751
19.7.7 Status Register (ECSPIx_STATREG)......................................................................................................... 753
19.7.8 Sample Period Control Register (ECSPIx_PERIODREG)..........................................................................754
19.7.9 Test Control Register (ECSPIx_TESTREG)............................................................................................... 756
19.7.10 Message Data Register (ECSPIx_MSGDATA)...........................................................................................757
Chapter 20External Interface Module (EIM)
20.1 Overview.......................................................................................................................................................................759
20.1.1 Features........................................................................................................................................................ 761
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20.1.2 Modes of Operation..................................................................................................................................... 761
20.1.2.1 Asynchronous Mode..................................................................................