Important Components, Blocks and Methodologies

To remember1. EXORS2. Counters and Generalized Counters3. State Machines (Moore, Mealy, Rabin-Scott)4. Controllers (FSM for control + Data Path)5. Iterative Circuits6. Generalized Register7. Pipelined8. Cellular Automata9. Oracle10.Data Flow Graph11.Butterfly12.Ping-Pong Architecture13.Trees14.Sequence Generators (permutations, selections, tree-search

strategies)15. Sequence Detectors16.Sequence Transformers

Useful tool for your creativity!

Cellular Automaton

Systolic Controller Ping-Pong Pipelined Combinational Hierarchical Iterative Circuit

Sorter X X X X X

Fast Fourier Butterfly

X X X X X

Max of N numbers

X X X X

Matrix – Vector Multiplication

X X X X X

Comparator of order

X X X X X X

Morphological Image Processing

X X X X X X

Other??

architecture

Design problem

XORs and XORs and XNORsXNORs

XOR

XOR gates

A 0 = AA 1 = A’A A’ = 1A + B = A B ABAB’ + A’B = AB’ A’BA B’ = A’ B = (A B)’

Cascading XOR gates

Parity Parity GenerationGeneration

74x280 9-bit odd/even parity 74x280 9-bit odd/even parity generatorgenerator

Tree and Tree and Iterative Iterative circuitscircuits

Fig.6.74. XORs in comparators

Always two choices:• Tree• Linear array (iterative)

Big OR functions

Sequence Sequence DetectorsDetectors

14

Sequence DetectorOne-input/one-output sequence detector: produces output value 1 every

time sequence 0101 is detected, else 0• Example: 010101 -> 000101

State diagram and state table:

Transition and output tables:

A B C D0/0

0/0

1/1

1/0

0/00/0

1/0

1/0

15

Sequence Detector (Contd.)Excitation and output maps:

Logic diagram:

1

1

1 11

y1y2

1

1

(b) Y1 map.

0 1

00

01

11

10

x

1

(a) z map.

0 1

00

01

11

10

x

1

(c) Y2 map.

0 1

00

01

11

10

xy1y2y1y2

z

y1Y1D

x

y2Y2D

z = xy1y2’y1 = x’y1y2 + xy1’y2 + xy1y2’y2 = y1y2’ + x’y1’ + y1’y2

Clock in D type synchronized FF is not shown

Sequence Detector (Contd.)Another state assignment:

z = xy1y2

Y1 = x’y1y2’ + xy2

Y2 = x’

State assignment is really important for iterative circuits

Big Big CountersCounters

18

Binary CounterOne-input/one-output modulo-8 binary counter: produces output value 1 for

every eighth input 1 value

State diagram and state table:

0/0 0/01/1 1/0

0/0

0/0

1/0 1/0

S0

S3S5

S7

S6 S2

S4

S1

1/0

1/01/0

1/0

0/0

0/0

0/00/0

• This is different type of graph of counter that we discussed before.

• Earlier the graph had no input and changes to new states corresponded to clock

• This graph assumes asynchronous FFs.

Mealy tableStays in the same state

Binary Counter (Contd.)Transition and output tables:

Excitation table for T flip-flops and logic diagram:

T1 = xT2 = xy1

T3 = xy1y2

z = xy1y2y3

z

T1

1

0

x

y1

T3

1

0

y3

T2

1

0

y2

Realization with asynchronous FFs, no clock

Implementing the Counter with asynchronous SR Flip-flops

Transition and output tables:

Excitation table for SR flip-flops and logic diagram:

• Trivially extensible to modulo-16 counter

S1 = xy1’R1 = xy1

S2 = xy1y2’R2 = xy1y2

S3 = xy1y2y3’R3 = z = xy1y2y3

S3

R3

y30

1y3

y3

S1

R1

x

y10

1y1

y1

S2

R2

y20

1y2

y2

Cell 1 Cell 3Cell 2

z

Asynchronous FFs, no clock

Counter Problems to think about:

• Design a counter modulo 2k

• Design a counter modulo 12348

• Design a counter in Gray Code.

• Design a counter in arbitrary code.

• Design a switchable counter in two codes with two capacities

• Design a reversible counter that can count up or down

Sequential Sequential Parity Parity

GeneratorsGenerators

23

Parity-bit GeneratorSerial parity-bit generator: receives coded messages and adds a parity bit

to every m-bit message• Assume m = 3 and even parity

State diagram and state table:

A

B C

D

0/0

0/00,1/0

1/0

0/0

0/0

1/0

1/0

E

F G

0/0

1/0

1/0

0,1/1

J1 = y2

K1 = y2’J2 = y1’K2 = y1

J3 = xy1’ + xy2

K3 = x + y2’ z = y2’y3

Controllers Controllers = =

(FSM+DataPath)(FSM+DataPath)

Sequential Circuit as a Control Element

Control element: streamlines computation by providing appropriate control signals

Example: digital system that computes the value of (4a + b) modulo 16• a, b: four-bit binary number• X: register containing four flip-flops• x: number stored in X• Register can be loaded with: either b or a + x• Addition performed by: a four-bit parallel adder• K: modulo-4 binary counter, whose output L equals 1 whenever the count

is 3 modulo 4

k2

L

ADD

Sequential circuit M

x

b

uInitiate

(4a + b)16

z

X

Kk1

a

4

4

444

26

Example (Contd.)

Sequential circuit M: • Input u: initiates computation• Input L: gives the count of K• Outputs: , , , z• When = 1: contents of b transferred to X• When = 1: values of x and a added and transferred back to X• When = 1: count of K increased by 1• z = 1: whenever final result available in X

k2

L

ADD

Sequential circuit M

x

b

uInitiate

(4a + b)16

z

X

Kk1

a

4

4

444

Example (Contd.)Sequential circuit M:

• K, u, z: initially at 0• When u = 1: computation starts by setting = 1

– Causes b to be loaded into X• To add a to x: set = 1 and = 1 to keep track of the number of times a

has been added to x• After four such additions: z = 1 and the computation is complete• At this point: K = 0 to be ready for the next computation

State diagram:

k2

L

ADD

Sequential circuit M

x

b

uInitiate

(4a + b)16

z

X

Kk1

a

4

4

444A

B

u = 0

D

= 1

00

11

10

L = 0/ = 1

01

C

-/z = 1

u = 1

= 1

L = 1/ = 1

-/ = 1

28

Example (Contd.)State assignment, transition table, maps and logic diagram:

A

B

u = 0

D

= 1

00

11

10

L = 0/ = 1

01

C

-/z = 1

u = 1

= 1

L = 1/ = 1

-/ = 1

z

u

y2Y2D2

Clock

L

D1

Clock

y2

y1

y1

Clock

Y1

,

0

1 11

(b) Maps for Y1 and Y2.

0 1y1

y2

0 0 u

1 L1

0 1y1

y2

0 0

Y1 Y2

PS NSy1y2 Y1Y2

00

00

1L

11

0u

10

11

01

(a) Transition table.

(c) Logic diagram.

= y1’y2

= = y1y2

z = y1y2’Y1 = y2

Y2 = y1’y2 + uy1’ + L’y2

Sequential circuit

Every student has to know (from ECE 271)

1. Realization of a state table from a state graph

2. Encoding of a state table

3. Realization of a state table with DD FFs.

4. Realization of a state table with JKJK FFs.

5. Realization of a state table with TT FFs.

• Realization of a state table with Iterative CircuitIterative Circuit

• Synchronous versus asynchronous FFs.

30

Arithmetic Arithmetic CircuitsCircuits

31

Topics

• Adder circuits

• How to subtract– Why complemented representation works out

so well

• Overflow

32

Iterative Circuit

• Functional blocks per bit

33

Adders

• Great example of this type of design• Design 1-bit circuit, then expand• Let’s look at

– Half adder – 2-bit adder, no carry in• Inputs are bits to be added• Outputs: result and possible carry

– Full adder – includes carry in, really a 3-bit adder

34

Half Adder

• S = X Y

• C = XY

35

Full Adder

• Three inputs. Third is Cin

• Two outputs: sum and carry

36

Two Half Adders (and an OR)

From Truth Table at the left we get this

37

Ripple-Carry Adder

• Straightforward – connect full adders

• Carry-out to carry-in chain– C0 in case this is part of larger chain, or just ‘0’

Iterative Iterative CircuitsCircuits

39

Iterative Combinational CircuitsIterative network: cascade of identical cells

• Sequential: counter, shift register• Combinational

Every finite output sequence that can be produced sequentially by an FSM can also be produced spatially (or simultaneously) by a

combinational iterative network

Analogy between iterative networks and sequential machines:• Cell inputs/outputs• Input/output carries

Cell 1

x11 x1lx12

z11 z1mz12

Cell 2

x21 x2lx22

z21 z2mz22

Cell i

xi1 xilxi2

zi1 zimzi2

Y21

Y2k

Y22

yi1

yi2

yik

Yi1

Yik

Yi2

Iterative combinational Circuits

Another notation and names

Iterative Iterative ComparatorsComparators

Iterative comparator of Iterative comparator of equalityequality

74x682 8-bit comparator74x682 8-bit comparator

Faster circuit

44

Cell TableCell table: analogous to state table

Example: 0101 pattern detector• Assuming the same assignment for states (A: 00, B: 01, C: 11, D: 10):

each cell same as the combinational logic of the sequential circuit derived for the 0101 sequence detector earlier

0

0

1

0

1

1

0

0

1

0

1

1

1

1

0

0

0

1

1

1

0

0

0

1

45

SynthesisExample: synthesize an n-cell iterative network

• Each cell has one cell input xi and one cell output zi

• zi = 1: if and only if either one or two of the cell inputs x1, x2, …, xi have value 1

• States A, B, C, D: 0, 1, 2, (3 or more) of the cell inputs to preceding cells have value 1

Cell table Cell Output-carries and cell-output tablexi

yi1

Yi2

yi2

Yi1

zi

Iterative comparator of orders Iterative comparator of orders and and equalityequality

1. Calculated last week2. Starts from graph3. Next table from graph4. Realize circuit combining identical

blocks5. Last block different6. Transition from combinational to

sequential circuit7. Main tradeoff of digital design –

parallel versus serial

General General Iterative Iterative CircuitsCircuits

Structures of generalized

iterative circuits

Structures

Structures

• It seems to be a loop here, but there is no loop

• You cannot create a loop that would cause creation of a memory.

• Circuit can have a loop but no memory.

• Students that do not understand iterative circuits will be severely penalized!

Slides from

• Wakerly

• Montek Singh