image thresholding pdf
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3.2.1 The Network Convergence .................................................. 17
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3.3.1 The Laser Spot Application ................................................. 24
3.3.1.1 Poor Contrast Images............................................ 24
3.3.1.2 Noisy Images ........................................................ 26
3.3.1.3 Various Illuminations............................................ 28
3.3.2 Other Applications ............................................................... 30
3.3.2.1 Document Binarization......................................... 30
3.3.2.2 Face Recognition .................................................. 31
3.3.2.3 Low Resolution Images ........................................ 32
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4.3.1 Downloading the Design to XSA board .............................. 39
4.3.2 Downloading/Uploading the Image..................................... 40
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5.2.1 Read/Write Operation Timing ............................................. 47
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5.3.1 Data Type............................................................................. 54
5.3.2 Data Width........................................................................... 54
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5.6.1 Visual Performance.............................................................. 58
5.6.2 Speed.................................................................................... 61
5.6.3 Area...................................................................................... 64
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-- Combinatorial processProcess (cl_data, w1_pres, w2_pres)
-- Variables definitionbegin
-- Variables assignmentIf dif1
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package body general isfunction boolean2stdlogic(b: in boolean) return std_logic is
variable s: std_logic;begin
if b thens := '1';
elses := '0';
end if;return s;
end function boolean2stdlogic;
function log2(v: in natural) return natural isvariable n: natural;variable logn: natural;
beginn := 1;for i in 0 to 128 loop
logn := i;exit when (n>=v);n := n * 2;
end loop;return logn;
end function log2;
end package body general;
"/ library IEEE, UNISIM;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;use WORK.general.all;package memCnt iscomponent memCnt
generic(FREQ :natural:= 70_000; -- operating frequency in KHz
DATA_WIDTH :natural:= 16; -- logic & MEM data widthNROWS :natural:= 4096; -- number of rows in MEM arrayNCOLS :natural:= 256; -- number of columns in MEM arrayCL_ADDR_WIDTH :natural:= 22; -- logic-side address widthMC_ADDR_WIDTH :natural:= 12; -- MEM-side address widthMAX_NOP:natural:= 10000;-- number of NOPs before entering self-refreshIN_PHASE:boolean:= TRUE-- MEM and controller work on same or oppositeclock edge
);port(-- logic sideclk :in std_logic; -- master clocklock :in std_logic; -- true if clock is stablerst :in std_logic; -- resetcl_rd :in std_logic; -- initiate read operationcl_wr :in std_logic; -- initiate write operation
prog :out std_logic; -- read/write/self-refresh op has begundone :out std_logic; -- read or write operation is donerdDone :out std_logic; -- read operation is done and data is availablecl_addr :in unsigned(CL_ADDR_WIDTH-1 downto 0); -- address from logic to MEMcl_Din :in unsigned(DATA_WIDTH-1 downto 0); -- data from logic to MEM
cl_Dout :out unsigned(DATA_WIDTH-1 downto 0); -- data from MEM to logic-- MEM sidemc_cke :out std_logic; -- clock-enable to MEMce_n :out std_logic; -- chip-select to MEMmc_ras :out std_logic; -- MEM row address strobemc_cas :out std_logic; -- MEM column address strobemc_we :out std_logic; -- MEM write enable
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mc_ba :out unsigned(1 downto 0); -- MEM bank addressmc_addr :out unsigned(MC_ADDR_WIDTH-1 downto 0); -- MEM row/column addresssDIn :in unsigned(DATA_WIDTH-1 downto 0); -- data from MEMsDOut :out unsigned(DATA_WIDTH-1 downto 0); -- data to MEMsDOutEn:out std_logic; -- true if data is output to MEM on sDOutudqm :out std_logic; -- enable upper-byte of MEM databus if trueldqm :out std_logic -- enable lower-byte of MEM databus if true);
end component;end package memCnt;
library IEEE, UNISIM;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;use WORK.general.all;
entity memCnt isgeneric(
FREQ :natural:= 70_000; -- operating frequency in KHzIN_PHASE: boolean:= TRUE;MAX_NOP: natural := 10000;DATA_WIDTH: natural := 16; -- logic & MEM data widthNROWS: natural := 4096; -- number of rows in MEM arrayNCOLS: natural := 256; -- number of columns in MEM arrayCL_ADDR_WIDTH:natural := 22; -- logic-side address width
MC_ADDR_WIDTH:natural := 12 -- MEM-side address width);port(-- logic sideclk :in std_logic; -- master clocklock :in std_logic; -- true if clock is stablerst :in std_logic; -- resetcl_rd :in std_logic; -- initiate read operationcl_wr :in std_logic; -- initiate write operationprog:out std_logic; -- read/write/self-refresh op has begundone :out std_logic; -- read or write operation is donerdDone :out std_logic; -- read operation is done and data is availablecl_addr :in unsigned(CL_ADDR_WIDTH-1 downto 0); -- address from logic to MEM
cl_Din :in unsigned(DATA_WIDTH-1 downto 0); -- data from logic to MEMcl_Dout :out unsigned(DATA_WIDTH-1 downto 0); -- data from MEM to logic-- MEM sidemc_cke :out std_logic; -- clock-enable to MEM
ce_n :out std_logic; -- chip-select to MEMmc_ras :out std_logic; -- MEM row address strobemc_cas :out std_logic; -- MEM column address strobemc_we :out std_logic; -- MEM write enablemc_ba :out unsigned(1 downto 0); -- MEM bank addressmc_addr :out unsigned(MC_ADDR_WIDTH-1 downto 0); -- MEM row/column addresssDIn :in unsigned(DATA_WIDTH-1 downto 0); -- data from MEMsDOut :out unsigned(DATA_WIDTH-1 downto 0); -- data to MEMsDOutEn:out std_logic; -- true if data is output to MEM on sDOutudqm :out std_logic; -- enable upper-byte of MEM databus if trueldqm :out std_logic -- enable lower-byte of MEM databus if true);
end memCnt;
architecture arch of memCnt isconstant OUTPUT:std_logic := '1'; -- direction of dataflow w.r.t. this controllerconstant INPUT :std_logic := '0';
constant NOP :std_logic := '0'; -- no operationconstant READ :std_logic := '1'; -- read operationconstant WRITE :std_logic := '1'; -- write operation
-- MEM timing parametersconstant Tinit :natural := 200; -- min initialization interval (us)constant Tref :natural := 64_000_000;-- maximum refresh interval (ns)constant Trfc :natural := 66; -- duration of refresh operation (ns)constant Trp :natural:= 20; -- min precharge command duration (ns)constant Twr :natural := 15; -- write recovery time (ns)constant Txsr :natural := 75; -- exit self-refresh time (ns)constant Tras :natural := 45;--min interval between active-precharge commands(ns)
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constant Trcd :natural := 20;-- min interval between active and R/W commands (ns)
-- MEM timing parameters converted into clock cycles (based on FREQ)-----------------------------------------------------------------------constant NORM :natural := 1_000_000;
-- normalize ns * KHzconstant INIT_CYCLES_N :natural := 1+((Tinit*FREQ)/1000);
-- MEM power-on initialization intervalconstant RAS_CYCLES_N: natural := 1+((Tras*FREQ)/NORM);
-- active-to-precharge intervalconstant RCD_CYCLES_N: natural := 1+((Trcd*FREQ)/NORM);
-- active-to-R/W intervalconstant REF_CYCLES_N: natural := 1+(((Tref/NROWS)*FREQ)/NORM);
-- interval between row refreshesconstant RFC_CYCLES_N: natural := 1+((Trfc*FREQ)/NORM);
-- refresh operation intervalconstant RP_CYCLES_N: natural := 1+((Trp*FREQ)/NORM);
-- precharge operation intervalconstant WR_CYCLES_N: natural := 1+((Twr*FREQ)/NORM);
-- write recovery timeconstant XSR_CYCLES_N: natural := 1+((Txsr*FREQ)/NORM);
-- exit self-refresh timeconstant MODE_CYCLES_N:natural := 2;
-- mode register setup timeconstant CAS_CYCLES_N: natural := 3;
-- CAS latencyconstant RFSH_OPS_N: natural := 8;-- number of refresh operations needed to init MEM
-- timer registers that count down times for various MEM operations-----------------------------------------------------------------------signal timer_r, timer_x: unsigned(log2(INIT_CYCLES_N+1)-1 downto 0);
-- current MEM op timesignal rasTimer_r, rasTimer_x:unsigned(log2(RAS_CYCLES_N+1)-1 downto 0);
-- active-to-precharge timesignal wrTimer_r, wrTimer_x: unsigned(log2(WR_CYCLES_N+1)-1 downto 0);
-- write-to-precharge timesignal refTimer_r, refTimer_x:unsigned(log2(REF_CYCLES_N+1)-1 downto 0);
-- time between row refreshessignal rfshCntr_r, rfshCntr_x:unsigned(log2(NROWS+1)-1 downto 0);
-- counts refreshes that are needesignal nopCntr_r, nopCntr_x: unsigned(log2(MAX_NOP+1)-1 downto 0);
-- counts consecutive NOP operationssignal doSelfRfsh: std_logic;
-- active when the NOP counter hits zero and self-refresh can start
-- MEM timing parameters converted into unsigned clock cycles for clarity----------------------------------------------------------------------------constant INIT_CYCLES :unsigned := TO_UNSIGNED(INIT_CYCLES_N, timer_r'length);constant RAS_CYCLES :unsigned := TO_UNSIGNED(RAS_CYCLES_N, rasTimer_r'length);constant RCD_CYCLES :unsigned := TO_UNSIGNED(RCD_CYCLES_N, timer_r'length);constant REF_CYCLES :unsigned := TO_UNSIGNED(REF_CYCLES_N, refTimer_r'length);constant RFC_CYCLES :unsigned := TO_UNSIGNED(RFC_CYCLES_N, timer_r'length);constant RP_CYCLES :unsigned := TO_UNSIGNED(RP_CYCLES_N, timer_r'length);constant WR_CYCLES :unsigned := TO_UNSIGNED(WR_CYCLES_N, wrTimer_r'length);constant XSR_CYCLES :unsigned := TO_UNSIGNED(XSR_CYCLES_N, timer_r'length);constant MODE_CYCLES :unsigned := TO_UNSIGNED(MODE_CYCLES_N, timer_r'length);constant CAS_CYCLES :unsigned := TO_UNSIGNED(CAS_CYCLES_N, timer_r'length);constant RFSH_OPS :unsigned := TO_UNSIGNED(RFSH_OPS_N, rfshCntr_r'length);
constant MAX_NOP_CNT :unsigned := TO_UNSIGNED(MAX_NOP, nopCntr_r'length);
-- states of the MEM controller state machine------------------------------------------------type cntlState is (
INITWAIT, -- initializationINITPCHG, -- initialization - initial precharge of MEM banksINITSETMODE, -- initialization - set MEM modeINITRFSH, -- initialization - do initial refreshesRW -- read/write/refresh the MEMACTIVATE, -- open a row of the MEM for reading/writingREFRESHROW, -- refresh a row of the MEM
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SELFREFRESH -- keep MEM in self-refresh mode with CKE low);
signal state_r, state_x: cntlState; -- state register and next state
-- commands that are sent to the MEM to make it perform certain operations-- commands use these MEM input pins (ce_n,mc_ras,mc_cas,mc_we,udqm,ldqm)-----------------------------------------------------------------------------subtype sdramCmd is unsigned(5 downto 0);constant NOP_CMD :sdramCmd := "011100";constant ACTIVE_CMD :sdramCmd := "001100";constant READ_CMD :sdramCmd := "010100";constant WRITE_CMD :sdramCmd := "010000";constant PCHG_CMD :sdramCmd := "001011";constant MODE_CMD :sdramCmd := "000011";constant RFSH_CMD :sdramCmd := "000111";
-- MEM mode registersubtype sdramMode is unsigned(11 downto 0);constant MODE: sdramMode := "00" & "0" & "00" & "011" & "0" & "000";
-- the logic address is decomposed into these sets of MEM address componentsconstant ROW_LEN :natural := log2(NROWS);-- number of row address bitsconstant COL_LEN :natural := log2(NCOLS);-- number of column address bits
signal bank :unsigned(mc_ba'range); -- bank address bitssignal row :unsigned(ROW_LEN - 1 downto 0); -- row address within banksignal col :unsigned(mc_addr'range); -- column address within row
-- registers that store the currently active bank and row of the MEMsignal activeBank_r, activeBank_x :unsigned(bank'range);signal activeRow_r, activeRow_x :unsigned(row'range);signal activeFlag_r, activeFlag_x:std_logic;-- indicates that some row is activesignal doActivate:std_logic;-- indicates when a new row needs to be activated
-- there is a command bit embedded within the MEM column addressconstant CMDBIT_POS :natural := 10; -- position of command bitconstant AUTO_PCHG_ON:std_logic := '1';-- CMDBIT value to auto-precharge the bankconstant AUTO_PCHG_OFF :std_logic := '0';-- CMDBIT value to disable auto-prechargeconstant ALL_BANKS :std_logic := '1';-- CMDBIT value to select all banksconstant ACTIVE_BANK:std_logic := '0';-- CMDBIT value to select only active bank
-- status signals that indicate when certain operations are in progresssignal wrInProgress :std_logic; -- write operation in progresssignal rdInProgress :std_logic; -- read operation in progresssignal activateInProgress:std_logic; -- row activation is in progress
-- these registers track the progress of read and write operations
-- registered outputs to logicsignal prog_r,prog_x :std_logic;
-- true when MEM read or write operation is startedsignal cl_Dout_r,cl_Dout_x:unsigned(cl_Dout'range);
-- holds data read from MEM and sent to the logicsignal cl_DoutOppPhase_r, cl_DoutOppPhase_x :unsigned(cl_Dout'range);
-- holds data read from MEM on opposite clock edge
-- registered outputs to MEMsignal mc_cke_r,mc_cke_x:std_logic; -- clock enable
signal cmd_r,cmd_x :sdramCmd; -- MEM command bitssignal mc_ba_r,mc_ba_x :unsigned(mc_ba'range); -- MEM bank address bitssignal mc_addr_r,mc_addr_x:unsigned(mc_addr'range); -- MEM row/column addresssignal mc_data_r,mc_data_x:unsigned(sDOut'range); -- MEM out databussignal mc_dataDir_r,mc_dataDir_x:std_logic;-- MEM databus direction control bit
begin------------------------------------------------------------- attach some internal signals to the I/O ports------------------------------------------------------------- attach registered MEM control signals to MEM input pins(ce_n,mc_ras,mc_cas,mc_we,udqm,ldqm)
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mc_cke
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-- any read or write resets NOP counter and exits self-refresh statenopCntr_x '0');doSelfRfsh
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when INITWAIT =>if lock = YES then
timer_x
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---------------------------------------------------------elsif cl_wr = YES then
if doActivate = YES thenif (activateInProgress=NO) andwrInProgress=NO)and (rdInProgress=NO) then
cmd_x
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timer_x
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7=9
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