iki10230 pengantar organisasi komputer bab 5.1: memori

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1 IKI10230 Pengantar Organisasi Komputer Bab 5.1: Memori 9 April 2003 Bobby Nazief ([email protected]) Qonita Shahab ([email protected]) bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/ Sumber : 1. Hamacher. Computer Organization, ed-5. 2. Materi kuliah CS152/1997, UCB.

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IKI10230 Pengantar Organisasi Komputer Bab 5.1: Memori. Sumber : 1. Hamacher. Computer Organization , ed-5. 2. Materi kuliah CS152/1997, UCB. 9 April 2003 Bobby Nazief ([email protected]) Qonita Shahab ([email protected]) bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/. - PowerPoint PPT Presentation

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AT90S8515*
running)
That is, any computer, no matter how primitive or advance, can be divided into five parts:
1. The input devices bring the data from the outside world into the computer.
2. These data are kept in the computer’s memory until ...
3. The datapath request and process them.
4. The operation of the datapath is controlled by the computer’s controller.
All the work done by the computer will NOT do us any good unless we can get the data back to the outside world.
5. Getting the data back to the outside world is the job of the output devices.
*
Istilah/Jenis Semikonduktor Memori
RAM --Random Access Memory time taken to access any arbitrary location
in memory is constant
SRAM --Static RAM A RAM chip design technology (see later)
DRAM --Dynamic RAM A RAM chip design technology (see later)
ROM --Read Only Memory ROMs are RAMs with data built-in when the
chip is created. Usually stores BIOS info.
Older uses included storage of bootstrap info
PROM --Programmable ROM A ROM which can be programmed
EPROM --Erasable PROM A PROM which can be programmed, erased
by exposure to UV radiation
EEROM – Electrical EPROM A PROM programmed & erased electrically
*
A packaging technology (single 32-bit data path)
DIMM Dual In-Line Memory Module
A packaging technology (dual 32-bit data paths)
FPM RAM Fast Page-Mode RAM
An older technology capable of about 60ns cycle time
EDO RAM Extended-data-out RAM
More modern FPM RAM, exploiting address coherency (see cache`later) capable of about 20ns access speed
SDRAM Synchronous DRAM
low as about 10ns
*
Jika transfer data per-word: 32 bit (data bus) => 4 bytes
Bytes mana yang diakses dari kemungkinan word tsb?
Perlu 2 bits untuk menentukan bytes yang mana dari word
Sisa bit: 30 bits digunakan untuk address word
*
Sel berisi 1 bit informasi
Baris dari sel membentuk untaian satu word
Contoh: 16 x 8 memori
memori SRAM mengandung 16 words
setiap words terdiri dari 8 bit data
Kapasitas memori: 16 x 8 = 128 bits
Decoder digunakan untuk memilih baris word mana yang akan diakses
*
Write:
1. Drive bit lines sesuai dengan bit (mis. b = 1, b’ = 0)
2. Select row store nilai b dan b’ menjadi state latch
Read:
Select row
3. Sense amp mendeteksi bit lines mana yang low state bit
6-Transistor SRAM Cell
Contoh: state 1
word line pull high (select)
The classical SRAM cell looks like this. It consists of two back-to-back inverters that serves as a flip-flop. Here is an expanded view of this cell, you can see it consists of 6 transistors.
In order to write a value into this cell, you need to drive from both sides. For example, if you want to write a 1, you will drive “bit” to 1 while at the same time, drive “bit bar” to zero.
Once the bit lines are driven to their desired values, you will turn on these two transistors by setting the word line to high so the values on the bit lines will be written into the cell.
Remember now these are very very tiny transistors so we cannot rely on them to drive these long bit lines effectively during read.
Also, the pull down devices are usually much stronger than the pull up devices. So the first thing we need to do on read is to charge these two bit lines to a high values.
Once these bit lines are charged to high, we will turn on these two transistors so one of these inverters (the lower one in our example) will start pulling one of the bit line low while the other bit line will remain at HI.
It will take this small inverter a long time to drive this long bit line to low but we don’t have to wait that long since all we need to detect the difference between these two bit lines.
And if you ask any circuit designer, they will tell you it is much easier to detect a “differential signal” (point to bit and bit bar) than to detect an absolute signal.
+2 = 30 min. (Y:10)
Address
decoder
A0
A1
A6
sense/write
amps
b7’
b7
d7
sense/write
amps
b1’
b1
d1
sense/write
amps
b0’
b0
d0
5-bit
decoder
W0
W1
W31
Static RAM (SRAM)
SRAM dapat menyimpan “state” (isi RAM) selama terdapat “tegangan” power supply
Sangat cepat, 10 nano-detik
Densitas rendah (bits per chip) memerlukan 6 transistor per-sel mahal
*
Write:
Read:
sesuai dengan value (threshold)
Refresh
row select
Perlu refresh!
The state of the art DRAM cell only has one transistor. The bit is stored in a tiny transistor.
The write operation is very simple. Just drive the bit line and select the row by turning on this pass transistor.
For read, we will need to precharge this bit line to high and then turn on the pass transistor.
This will cause a small voltage change on the bit line and a very sensitive amplifier will be used to measure this small voltage change with respect to a reference bit line.
Once again, the value we stored will be destroyed by the read operation so an automatic write back has to be performed at the end of every read.
+ 2 = 48 min. (Y:28)
r
o
w
d
e
c
o
d
e
r
row
address
Similar to SRAM, DRAM is organized into rows and columns.
But unlike SRAM, which allows you to read an entire row out at a time at a word, classical DRAM only allows you read out one-bit at time time.
The reason for this is to save power as well as area. Remember now the DRAM cell is very small we have a lot of them across horizontally.
So it will be very difficult to build a Sense Amplifier for each column due to the area constraint not to mention having a sense amplifier per column will consume a lot of power.
You select the bit you want to read or write by supplying a Row and then a Column address.
Similar to SRAM, each row control line is referred to as the word line and each vertical data line is referred to as the bit line.
+2 = 57 min. (Y:37)
Nonpersistant
Densitas tinggi: 1 transistor/bit
Lebih murah dari SRAM
electrical noise, light, radiation
*
Seluruh row dibaca & disimpan di column latches
Isi dari row memori cells akan di-refresh
Column Address (~10ns)
Access selected bit
WRITE: Set selected column latch to Din
Rewrite/Refreshed (~30ns)
RAS’
Let me show you an example. Here we are performing two write operation to the DRAM.
Setup/hold times in colar bars
Remember, this is very important. All DRAM access start with the assertion of the RAS line.
When the RAS_L line go low, the address lines are latched in as row address. This is followed by the CAS_L line going low to latch in the column address.
Of course, there will be certain setup and hold time requirements for the address as well as data as highlighted here.
Since the Write Enable line is already asserted before CAS is asserted, write will occur shortly after the column address is latched in. This is referred to as the Early Write Cycle.
This is different from the 2nd example I showed here where the Write Enable signal comes AFTER the assertion of CAS. This is referred to as a Later Write cycle.
Notice that in the early write cycle, the width of the CAS line, which you as a logic designer can and should control, must be as long as the memory’s write access time.
On the other hand, in the later write cycle, the width of the Write Enable pulse must be as wide as the WR Access Time.
Also notice that the RAS line has to remain asserted (low) during the entire access cycle.
The DRAM write cycle time is defined as the time between the two RAS pulse and is much longer than the DRAM write access time.
+3 = 63 min. (Y:43)
Time
RAS’
Similar to DRAM write, DRAM read can also be a Early read or a Late read.
In the Early Read Cycle, Output Enable is asserted before CAS is asserted so the data lines will contain valid data one Read access time after the CAS line has gone low.
In the Late Read cycle, Output Enable is asserted after CAS is asserted so the data will not be available on the data lines until one read access time after OE is asserted.
Once again, notice that the RAS line has to remain asserted during the entire time. The DRAM read cycle time is defined as the time between the two RAS pulse.
Notice that the DRAM read cycle time is much longer than the read access time.
Q: RAS & CAS at same time? Yes, both must be low
+2 = 65 min. (Y:45)
Need to rewrite row
prosesor menunggu sampai cycle time selesai lalu melakukan request lagi.
Must Refresh Periodically
Approx. every 1ms
*
Teknologi memori: segi kecepatan akses berkembang sangat lambat
Gap yang semakin membesar dengan kecepatan prosesor (cycle sangat kecil => 1 nsec, akses memori orde puluhan nsec).
Perkembangan teknologi DRAM
Inovasi dilakukan dari segi: cara melakukan akses
memotong waktu akses (mis. CAS tidak diperlukan)
burst mode: sekaligus mengambil data sebanyak mungkin (seluruh word)
perlu tambahan rangkaian: register, latch dll
*
At video rate
Entire row buffered here
row access time col access time cycle time page mode cycle time
50ns 10ns 90ns 25ns
N x M “SRAM” to save a row
After a row is read into the register
Only CAS is needed to access other M-bit blocks on that row
RAS’ remains asserted while CAS’ is toggled
A
Col Address
Col Address
2nd M-bit
3rd M-bit
4th M-bit
N cols
So with this register in place, all we need to do is assert the RAS to latch in the row address, then entire row is read out and save into this register.
After that, you only need to provide the column address and assert the CAS needs to access other M-bit within this same row.
I like to point out that even I use the word “SRAM” here but this is no ordinary sram. It has to be very small but the good thing is that it is internal to the DRAM and does not have to drive any external load.
Anyway, this type of operation where RAS remains asserted while CAS is toggled to bring in a new column address is called Page Mode operation.
Strore orw so don’t have to repeat: SRAM
It will become clearer why this is called Page Mode operation when we look into the operation of the SPARCstation 20 memory system.
+ 2 = 71 min. (Y:51)
Burst Mode:
Standards: PC100, PC133
Cell array is organized in 2 banks
allows interleaving of word’s access
Standards: PC2100, PC2300
RDRAM: Rambus DRAM
Data is transferred on both edges of the clock
Memory cells are organized in multiple banks
Standards: proprietary owned by Rambus Inc.
*
Memory Bandwidth:
Data
CAS’
D0
D1
D2
D3
Col
RAS’
Addr
Row
So with this register in place, all we need to do is assert the RAS to latch in the row address, then entire row is read out and save into this register.
After that, you only need to provide the column address and assert the CAS needs to access other M-bit within this same row.
I like to point out that even I use the word “SRAM” here but this is no ordinary sram. It has to be very small but the good thing is that it is internal to the DRAM and does not have to drive any external load.
Anyway, this type of operation where RAS remains asserted while CAS is toggled to bring in a new column address is called Page Mode operation.
Strore orw so don’t have to repeat: SRAM
It will become clearer why this is called Page Mode operation when we look into the operation of the SPARCstation 20 memory system.
+ 2 = 71 min. (Y:51)
17 address lines
8 data lines
L H Read data at location on address lines
L L Write write data on data lines to address
on address lines
Contoh: Struktur 1 MB (2/4)
1 MB dapat dikonstruksi dengan
organisasi 8 chips memori 128 KB (8 x 128 x 8 = 1 MB)
The address space is
block 1 has addresses 128K -- 256K-1
block 2 has addresses 256K -- 384K -1
:
:
:
:
This will be chip 0
This will be chip 1
This will be chip 7
Berapa banyak bits yang diperlukan untuk alamat pada chips?
memilih chips yang mana?
1MB membutuhkan alamat sebesar 20 bit,
Ide: membagi field address menjadi 2 yakni:
bits untuk memilih chips dan address pada field tsb.
Bits 16 -- 0 (17 address bits)
Bits 19 -- 17 (3 address bits)
17 bits select the address in each
128KB block (== each chip)
128KB blocks (chips)
Data Lines
3 Address Lines
EEPROM
Implementation:
*
Pilihan untuk memberikan kapasitas BESAR pada sistem memori.
SRAM cepat tapi mahal dan kapasitas kecil
Pilihan untuk menyediakan sistem memori yang waktu aksesnya CEPAT.
Struktur memori besar dapat dibangun dari kumpulan chips memori kecil:
Field alamat dibagi: field address dan field untuk memilih chips/memori yang mana.
Next topic: Trend teknologi memori
(go to: http//www.tomshardware.com, search SDRAM guide)
*
berada pada sumber/tujuan data yakni memori.
µProc
Latency
Cliché: