iki10230 pengantar organisasi komputer bab 4.1: input/output & interrupt

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1 IKI10230 Pengantar Organisasi Komputer Bab 4.1: Input/Output & Interrupt 19 Maret 2003 Bobby Nazief ([email protected]) Qonita Shahab ([email protected]) bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/ Sumber : 1. Hamacher. Computer Organization, ed-5. 2. Materi kuliah CS152/1997, UCB.

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IKI10230 Pengantar Organisasi Komputer Bab 4.1: Input/Output & Interrupt. Sumber : 1. Hamacher. Computer Organization , ed-5. 2. Materi kuliah CS152/1997, UCB. 19 Maret 2003 Bobby Nazief ([email protected]) Qonita Shahab ([email protected]) - PowerPoint PPT Presentation

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Pengantar Organisasi Komputer*
Processor
(active)
Computer
Control
(“brain”)
Datapath
(“brawn”)
Memory
(passive)
(where
programs,
data
live when
not running)
That is, any computer, no matter how primitive or advance, can be divided into five parts:
1. The input devices bring the data from the outside world into the computer.
2. These data are kept in the computer’s memory until ...
3. The datapath request and process them.
4. The operation of the datapath is controlled by the computer’s controller.
All the work done by the computer will NOT do us any good unless we can get the data back to the outside world.
5. Getting the data back to the outside world is the job of the output devices.
*
I/O lets computers do amazing things:
Read pressure of synthetic hand and control synthetic arm and hand of fireman
Control propellers, fins, communicate
Read bar codes of items in refrigerator
*
I/O Speed: bytes transferred per second
(from mouse to display: million-to-1)
Device Behavior Partner Data Rate (Kbytes/sec)
Keyboard Input Human 0.01
Mouse Input Human 0.02
Network-LAN I or O Machine 10,000.00
Graphics Display Output Human 30,000.00
Here are some examples of the various I/O devices you are probably familiar with.
Notice that most I/O devices that has human as their partner usually has relatively low peak data rates because human in general are slow relatively to the computer system.
The exceptions are the laser printer and the graphic displays.
Laser printer requires a high data rate because it takes a lot of bits to describe high resolution image you like to print by the laser writer.
The graphic display requires a high data rate because as I will show you later in today’s lecture, all the color objects we see in the real world and taken for granted is very hard to replicate on a graphic display.
Let’s take a closer look at one of the most popular storage device, magnetic disks.
+2 = 28 min. (Y:08)
What do we need to make I/O work?
A way to connect many types of devices to the Proc-Mem
A way to control these devices, respond to them, and transfer data
A way to present them to user programs so they are useful
Windows
Files
Proc
Mem
Control
Datapath
Memory
Processor
Input
Output
1 register menyatakan kesiapan untuk menerima/mengirim data
(I/O ready), sering disebut Status/Control Register SIN, SOUT
1 register berisi data, sering disebut Data Register DATAIN, DATAOUT
Prosesor membaca isi Status Register terus-menerus, menunggu I/O device men-set Bit Ready di Status Register (0 1)
Prosesor kemudian menulis atau membaca data ke/dari Data Register
tulis/baca ini akan me-reset Bit Ready (1 0) di Status Register
Prosesor
SOUT
DATAOUT
Display
SIN
DATAIN
Keyboard
Bus
Move DATAIN,(R0) ; Read character
Output: Write to display
Move (R0),DATAOUT; Write character
; Meanwhile, stores it
Call Process ; Do something
Called “Memory Mapped Input/Output”
A portion of the address space dedicated to communication paths to Input or Output devices (no memory there)
The registers are accessed by Load/Store instructions, just like memory
Some machines have special input and output instructions that read-from and write-to Device Address Space:
Called “I/O Mapped Input/Output”
IN Rx,Device-Address ; Processor Device
Branch=0 READ ; Wait for key-in
In DATAIN,R1 ; Read character
Output: Write to display
Branch=0 ECHO ; Wait for it
Move (R0),R1 ; Get the character
Out R1,DATAOUT ; Write it
; Meanwhile, stores it
Call Process ; Do something
Processor-I/O Speed Mismatch
500 MHz microprocessor can execute 500 million load or store instructions per second, or 2,000,000 KB/s data rate
I/O devices from 0.01 KB/s to 30,000 KB/s
Input: device may not be ready to send data as fast as the processor loads it
Also, might be waiting for human to act
Output: device may not be ready to accept data as fast as processor stores it
What to do?
WAITK: TestBit STATUS,#0 ; Keyboard (IN) ready?
Branch=0 WAITK ; Wait for key-in
Move R0,DATAIN ; Read character
Output: Write to display
Branch=0 WAITD ; Wait for it
Move DATAOUT,R0 ; Write character
Move (R1)+,R0 ; Store & advance
Branch≠0 WAITK ; No, get more
Call Process ; Do something
STATUS
DATAIN
DATAOUT
OUT
IN
Cost of Polling?
Assume for a processor with a 500-MHz clock it takes 400 clock cycles for a polling operation (call polling routine, accessing the device, and returning). Determine % of processor time for polling
Mouse: polled 30 times/sec so as not to miss user movement
Floppy disk: transfers data in 2-byte units and has a data rate of 50 KB/second.
No data transfer can be missed.
*
Times Mouse Polling/sec
Times Polling Floppy/sec
Floppy Polling Clocks/sec
*
Times Polling Disk/sec
Disk Polling Clocks/sec
What is the alternative to polling?
Wasteful to have processor spend most of its time “spin-waiting” for I/O to be ready
Wish we could have an unplanned procedure call that would be invoked only when I/O device is ready
*
An I/O interrupt is “asynchronous”
More information needs to be conveyed
An I/O interrupt is asynchronous with respect to instruction execution:
I/O interrupt is not associated with any instruction, but it can happen in the middle of any given instruction
I/O interrupt does not prevent any instruction from completion
How does an I/O interrupt different from the exception you already learned?
Well, an I/O interrupt is asynchronous with respect to the instruction execution while exception such as overflow or page fault are always associated with a certain instruction.
Also for exception, the only information needs to be conveyed is the fact that an exceptional condition has occurred but for interrupt, there is more information to be conveyed.
Let me elaborate on each of these two points.
Unlike exception, which is always associated with an instruction, interrupt is not associated with any instruction. The user program is just doing its things when an I/O interrupt occurs.
So I/O interrupt does not prevent any instruction from completing so you can pick your own convenient point to take the interrupt.
As far as conveying more information is concerned, the interrupt detection hardware must somehow let the OS know who is causing the interrupt.
Furthermore, interrupt requests needs to be prioritized. The hardware that can do all these looks like this.
+2 = 64 min. (Y:44)
jr
interrupt
service
routine
(4)
(5)
That is, whenever an I/O device needs attention from the processor, it interrupts the processor from what it is currently doing.
This is how an I/O interrupt looks in the overall scheme of things. The processor is minding its business when one of the I/O device wants its attention and causes an I/O interrupt.
The processor then save the current PC, branch to the address where the interrupt service routine resides, and start executing the interrupt service routine.
When it finishes executing the interrupt service routine, it branches back to the point of the original program where we stop and continue.
The advantage of this approach is efficiency. The user program’s progress is halted only during actual transfer.
The disadvantage is that it require special hardware in the I/O device to generate the interrupt. And on the processor side, we need special hardware to detect the interrupt and then to save the proper states so we can resume after the interrupt.
+2 = 62 min. (Y:42)
Main Program
BitSet #9,PS ; Set interrupt-enable bit in the PS.

Move PNTR,R0 ; Load buffer pointer.
MoveByte DATAIN,R1 ; Get input character and
MoveByte R1,(R0)+ ; store it in the buffer.
Move R0,PNTR ; Update buffer pointer.
CompareByte #$0D,R1 ; Check if Carriage Return
Branch≠0 RTRN
RTRN:
Return-from-interrupt
Benefit of Interrupt-Driven I/O
400 clock cycle overhead for each transfer, including interrupt. Find the % of processor consumed if the hard disk is only active 5% of the time.
Interrupt rate = polling rate
= 500K interrupts/sec
= 200,000,000 clocks/sec
Disk active 5% 5% * 40% 2% busy
*
Save the PC for return
To enable the “proper return” when the interrupt has been served
AVR uses the stacks
To allow “proper branch” to the service routine
AVR defines:
Determine cause of interrupt?
To guarantee “proper service routine” serving “proper interrupt”
*
Interrupt Request
I/O Devices interrupt processor through a single line known as Interrupt Request signal (INTR)
To serve n devices, the line uses wired-or connection that allows any interrupting device to activate the signal
any INTRi is switched on, INTR will become TRUE
INTR1
INTRn
INTR2
Vdd
Processor
INTR
The device activates interrupt request signal.
The processor interrupts the program currently being executed.
Interrupts are disabled by changing the control bits in the PS.
The device is informed that its request has been recognized, and in response, it deactivates the interrupt request signal.
The action requested by the interrupt is performed by the interrupt service routine.
*
Need to have priority scheme
Which I/O device caused exception?
Need to convey the identity of the device generating the interrupt
Can processor avoid interrupts during the interrupt routine?
In general, interrupts are disabled whenever one is being serviced; interrupts will be enabled after the service is completed
However, occasionally a more important interrupt may occur while this interrupt being served
Who keeps track of status of all the devices, handle errors, know where to put/supply the I/O data?
*
The Interrupting Device may provide its identity through:
Interrupt-Request (IRQ) bit in its Status Register, which will be evaluated one-by-one by the processor (polling)
Sending special code the the processor over the bus (vectored interrupt)
CPU
Advantage: simple
CPU
INTA
Release
INTR
wired-OR
The daisy chain arbitration scheme got its name from the structure for the grant line which chains through each device from the highest priority to the lowest priority.
The higher priority device will pass the grant line to the lower priority device ONLY if it does not want it so priority is built into the scheme.
The advantage of this scheme is simple. The disadvantages are:
(a) It cannot assure fairness. A low priority device may be locked out indefinitely.
(b) Also, the daisy chain grant line will limit the bus speed.
+1 = 39 min. (Y:19)
Prioritized Interrupt: Priority Groups
Interrupt Nesting: an Interrupt Service Routine may be interrupted by other, higher-priority interrupt
CPU
Interrupt is only a subset of Exception
Exception: signal marking that something “out of the ordinary” has happened and needs to be handled
Interrupt: asynchronous exception
Trap: synchronous exception
To recover from errors: Illegal Instruction, Divide By Zero, …
To debug a program
*
I/O & Operating System
The I/O system is shared by multiple programs using the processor
OS guarantees that user’s program accesses only the portions of I/O device to which user has rights (e.g., file access)
Low-level control of I/O device is complex because requires managing a set of concurrent events and because requirements for correct device control are often very detailed
OS provides abstractions for accessing devices by supplying routines that handle low-level device operations
I/O systems often use interrupts to communicate information about I/O operations
OS handles the exceptions generated by I/O devices (and arithmetic exceptions generated by a program)
Would like I/O services for all user programs under safe control
*
I/O Device
User’s
Call appropriate routine
Push new values for PS and PC on stack
Return from interrupt
Initialize memory buffer address pointer
Call device driver to initialize device & enable
interrupts in the device interface (VDTINIT)
Return from subroutine
Call appropriate device driver (VDTDATA)
If END = 1, then set process status to Runnable
Return from interrupt
If character = CR, then set END = 1;
else set END = 0
.org OVF0addr
main:
rjmp idle
rjmp wait
Do some work
out TIFR,u_tmp ; to clear T/C0 overflow flag
out TIMSK,u_tmp ; and enable T/C0 overflow interrupt
Do more work
reti
tim0_ovf:
Do something
clr u_tmp
cbr u_status,(1<<BUSY)|(1<<TD) ;Clear busy-flag and transmit-flag
reti