978-1-61284-736-8/11/$26.00 ©2011 IEEE 239 27th IEEE SEMI-THERM Symposium

Thermal Mapping of Delphi Thermal Test Dies

Pavel L. Komarov1, Peter E. Raad1, 3, Mihai G. Burzo1, Taehun Lee2, and Moon J. Kim2 1Department of Mechanical Engineering, SMU, Dallas, TX 75275

2Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX 75083 3Corresponding author: praad@smu.edu

Abstract The primary purpose of this work was to investigate the

relative heat removal effectiveness of various thermal interface and buried oxide materials as they would be used in actual conditions. The thermoreflectance thermography approach was used to measure, non-invasively and with submicron spatial resolution, the surface temperature fields of two types of thermal test devices: (i) Delphi thermal test dies that have been attached to the heat sink with different thermal interface materials and (ii) microresistor test devices built on various buried oxide structures. The temperature maps were used to identify the most thermally efficient material in each of the two types investigated.

Keywords Thermal Mapping, thermography, thermoreflectance,

TIM, BOX, thermal interface materials, buried oxide materials.

1. Introduction Microelectronic devices continue to push material and

manufacturing limitations of what can be achieved within the existing knowhow and capabilities. To keep up with the 1965 vision of Gordon Moore, designers will need to come up with radical new ideas such as 3D chips and memristors. To achieve landmarks of the scale of constructing 2 billion transistors in a chip (Intel’s Tukwila CPU), electronics manufacturers must confront severe scaling and financial challenges that are making it necessary to spend over $4 billion for a new fab. The idea originally formulated in Moore's 1965 paper did not address solely the density of transistors that can be achieved, but rather the density of transistors at which the cost per transistor is the lowest [1]. Even if Moore’s law will not survive in its current form (doubling the number of transistors in a chip every couple of years), the exponential trend of increasing the device density in a chip will survive at least for the foreseeable future, but accompanied with solving serious technological challenges along the way. One such challenge is that the increase in device density produces a tremendous amount of heat that must be removed before temperatures rise to levels that can damage even the device’s physical integrity.

Moore concluded that as more transistors are included in a chip, the cost of making each transistor decreases, but the chance that the chip will not work due to a defect also increases. Moore examined the density of transistors at which cost is minimized, and observed that, as transistors were made smaller through advances in photolithography, this number would increase at “a rate of roughly a factor of two per year.” No one in the mid-sixties could have envisioned that thermal issues will someday become just as critical as solving the

photolithography challenges, but that is precisely where we are now.

The challenge of thermally characterizing modern chips is made tenfold harder by the exceedingly small scales combined with the fact that for experimental approaches to work they require either physical access or a visual path to the region of interest. Contact methods [2], for example, present the difficulties of having to access features of interest with an external probe, or in the case of embedded features, fabricate a measuring probe into the device, and then having to isolate and exclude the influence of the probe itself. On the other hand, non-contact methods [2] can provide temperature profiles only on device surfaces, but since most devices use a transparent passivation and field oxide layers, it turns out that such methods can also provide direct temperature measurement of the channel area of a device with deep submicron spatial resolution. One such non-contact method is the thermoreflectance thermography employed here.

This work will make use of the thermoreflectance thermography (TRTG) method [3, 4] to investigate the thermal effectiveness of thermal interface materials (TIM) and of buried oxide (BOX) materials, which represent thermal interfacing approaches used at two significantly different spatial scales. TIMs are used to thermally attach dies while BOX materials are used in the fabrication of devices that ultimately make up the much larger dies. Determining the thermal efficiency requires knowing temperatures, which cannot be measured directly but rather through a third body. Thermal test dies, such as the Delphi dies, have been devised for such a purpose. By combining a heater surface and an electric diode, the die makes it possible to heat a test stack with a prescribed power and extract the average surface temperature from an electrical measurement of the calibrated diode. The construction of the Delphi test die, however, appears to yield a systematic error resulting from the placement of the diode, which gives it an independent heat path to the sink. The newer submicron measurement approach used here made it possible to identify this type of error. Dealing with the thermal characterization of thin buried films such as BOX materials requires the use of commensurately micro-scale measurement techniques. An analog of the test die used for macro-scale TIMs becomes to construct a microresistor directly on the wafer and use it to determine the local average surface temperature from an electrical measurement of the calibrated resistor. The application of the submicron TRTG approach at the different scales provides direct confirmation of the thermal effectiveness of TIM and BOX materials through the observation of temperature maps. While diodes and resistors make it possible to extract an average local temperature, the TRTG approach adds information on the distribution of that temperature over the area of interest.

Komarov et al., Thermal Mapping of Delphi Thermal Test Dies 27th IEEE SEMI-THERM Symposium

2. Methodology (TRTG) The experimental temperature mapping system is based on

the thermoreflectance (TR) method [3-6], where the change in the surface temperature is measured by detecting the change in the reflectivity of the sample. A functional schematic of the TTRG system is shown in Fig. 1.

The measurement methodology involves a calibration phase and a device activation phase. In the calibration phase, the thermoreflectance coefficient, CTR, is determined for each of the surface materials in the region of interest. This consists of determining the relationship between the changes in reflectance and surface temperature. To do so, the device is held at prescribed low and then high temperatures, and the reflectance field is measured at each of the two different temperatures levels. Dividing the measured change in reflectance by the prescribed temperature delta yields CTR = �R/R·�T-1 for a given material at a given wavelength of light. The thermoreflectance coefficient is highly sensitive to the wavelength of the probing light and varies strongly from one material to another. In order to maximize the signal to noise ratio, the light wavelength is chosen to maximize CTR for each material (e.g., the optimal wavelength of light for gold has been found to be at around 485 nm).

In the activation phase, the changes in surface reflectivity in the on and off states of the device are collected in the region of interest with submicron spatial resolution. The frames containing the change in surface reflectivity induced by the temperature variations of the device under test (DUT) are acquired, averaged, and scaled according to the calibration data obtained in the first step above, which yields the temperature map over the area of interest on the first non-transparent surface of the device (as viewed from the camera).

3. Thermal characterization of TIM layers using Delphi thermal test dies The Delphi thermal test devices, which have been

discontinued by the manufacturer but are still widely available in various laboratories, are still in use as a proven tool for various tasks, one of which is in determining the interface thermal resistance of a TIM and identifying the most effective TIM from a list of available candidates.

3.1 Device specification The device tested in this phase of the investigation is a

well-known silicon thermal test die: Delphi PST2-03. It has dimensions of 3.81×3.81×0.254 mm, and can handle a maximum of 60-65 W of power dissipation. The heater area covers 80% of the entire die area. In the central region of the die is a chain of five, serially connected diodes meant to monitor the die’s average temperature (See Fig. 2).

3.2 Results and discussion The temperature of the heater was measured with the

T°Imager™ TRTG system in two locations corresponding to the two different material stack construction (heater and diode areas). Figure 3a shows the image of the area of the device that was measured, while Fig. 3b shows the map of the acquired relative reflectivity change for an activation power level of 5.3 W. Calibration for this device at a light wavelength of 490 nm yielded CTR values of 1.89×10-4 K-1 for the diode area (identified with 1 in Fig. 3b) and 4.37×10-4 K-1 for the heater area (identified with 2 in Fig. 3b). Applying these calibration values to the acquired relative reflectivity map in the delineated areas 1 and 2 in Fig. 3 yields the average temperature rise resulting from device activation. The

(a)

(b)

Figure 2: Pictures of Delphi thermal test die: (a) full view, and (b) diode chain region with area of TRTG measurement denoted.

Figure 1: Functional schematic of the CCD-based thermo-reflectance thermography system [7].

Komarov et al., Thermal Mapping of Delphi Thermal Test Dies 27th IEEE SEMI-THERM Symposium

differences in reflectivity change are due to the differences in CTR, which is higher in the heater area than in the diode area. The passivation layers in the two areas are different which creates light interference as the light travels through the different stacks. As a result, the CTR value changes from one region to another where the fabrication process is different. However, even after accounting for the change in CTR, the temperature rise in the diode area is still approximately 10% smaller than in the heater area. To clarify the discrepancy, these measurements were repeated at five different levels of activation power. The results are plotted in Fig. 4. For comparison purposes, the temperature rise values obtained from the built-in diode chain are also shown on the same figure.

It is observable that the 10% discrepancy in temperature rise occurs for all five power levels, and that the behavior is linear. In addition, the temperature rise values obtained with the built-in diode coincide well with those measured with TRTG in the diode region. Therefore it is clear that the discrepancy is systematic and is somehow related to differences in the thermal resistance between the heater and the sink. To shed light on this issue, an SEM image was

obtained, which showed that indeed there is an additional oxide layer under the heater region (Fig. 5).

(a)

(b) Figure 5: SEM images of material stack structure of diode and heater areas: (a) top view, and (b) cross-sectional view.

This extra oxide layer under the heater (450 nm of Oxide 2 in Fig. 5) provides an additional resistance in the heat path to the sink, which elevates the temperature in that region. In designing a test die, temperature uniformity is desirable, but is difficult to achieve because of the nature of deposition and etching processes during fabrication as well as the need to

(a)

(b)

Figure 3: TRTG measurement results: (a) image ofmeasured area as identified in Fig. 2, and (b) relativereflectivity change due to device activation. Regions 1 and 2correspond to the different material stacks in the diode andheater regions, respectively.

Figure 4: Temperature versus power measured with the built-in diode chain and with the thermography system (error bars show the uncertainty associated with the TRTG data).

Si

Oxide 2Oxide 1

Heater

Komarov et al., Thermal Mapping of Delphi Thermal Test Dies 27th IEEE SEMI-THERM Symposium

accommodate important electrical design features. In any event, the diode in these types of test dies is not intended to measure the temperature of the heater, but rather the temperature of the substrate in contact with the material under test, which in this case is the TIM. The fact that in this work the submicron measurements detected a discrepancy is not an indication that the dies are poorly constructed and exhibit a systematic uncertainty. Rather, it is a demonstration that submicron measurements can detect unexpected temperature non-uniformities, which are inherently undetectable with macro-scale and built-in electrical sensors.

In order to characterize the thermal effectiveness of the five different TIMs under investigation, a Delphi device was affixed with each TIM to a metallic sink plate. The five fixtures were identical in all other ways except for the TIM used to attach the Delphi die to the sink plate. TRTG measurements and calibrations were conducted for all five Delphi dies to eliminate any possible manufacturing variations from die to die. The measured average surface temperature rise values of the devices (�Tavg) are summarized in Table 1.

The thermal resistance, R�, of each TIM was then calculated as the ratio between the applied heating power per unit area, P/A, and the averaged temperature rise �T = Tavg - Tamb. The heater area for the Delphi device in use is 2.5 mm × 3 mm. The results, shown in Table 1, indicate that TIM B has the lowest effective thermal resistance.

4. In-situ thermal characterization of BOX substrates using built-in microresistors As recent integrated circuit designs have been quickly

approaching their physical limits, the short channel effects have become secondary issues due to channel length reduction. Since the conventional SOI technology employs SiO2 buried oxide (BOX), the SOI device degradation caused by the self-heating effect has been a challenging issue. The self heating effect [8] has hampered a wider SOI application particularly in high-performance, high-speed analog and mixed-signal ICs due to degraded carrier mobility, reduced drain current, and increased power consumption [9]. Thus, the replacement of the buried silicon oxide layer with alternative materials that help remove heat more efficiently during the device operation as well as offer higher electrical resistivity, thermal stability, and electrical breakdown is crucial to improve the performance and reliability of SOI devices [10, 11]. In this work, some candidate dielectric materials were selected and tested using a submicron TRTG system to

provide an insight for future SOI substrates especially targeted to high performance mixed-signal applications.

4.1 Description of the device under test Several BOX candidate materials were prepared on 100

mm diameter Si (100) (1-3�) wafers by LPCVD, PECVD, and RF sputtering systems, as specified in the second row of Table 2. The dielectric properties were also measured and it was found that all BOX materials evaluated here have good dielectric properties, as the values in the last two rows of Table 2 would indicate. Once the BOX layer was laid down, sets of identical microresistors were built on top of each structure as shown in Fig. 6. The thickness of the resistors was 0.3 μm and the length and width of each resistor strip was 1000 μm and 20 μm, respectively. Two pads were constructed at each end of the resistor strip to enable the use of a 4-wire activation scheme, which makes it possible to accurately determine the heating power generated by each resistor.

4.2 Results and Discussion Thermal imaging was performed to determine the degree

of heat dissipation through the various BOX structures considered here. An identical power of 4 W was applied to all

Figure 6: Schematic showing top and cross-sectional views of the microresistors (20 μm by 1000 μm resistors).

TIM Material

No.

Applied Power P (W)

Average Delta Temperature

�Tavg (°C)

Thermal Resistance

R�=�T.A.P-1 (m2-K/W) A 5.50 36.7 5.0×10-5

B 5.30 17.2 2.4×10-5 C 5.43 17.8 2.5×10-5 D 5.31 20.6 2.9×10-5 E 5.32 26.0 3.7×10-5

Table 1: Applied power, average surface temperature rise, and thermal resistance for the TIMs under test.

BOX material SiO2 DLC Al2O3 Si3N4

Deposition method

Thermally grown

LPCVD/ PECVD RF sputter LPCVD

Dielectric strength (MV/cm)

8-10 5 5.5-6.5 8.6

Dielectric constant 3.9 5.4 7.5-12 8.9

Table 2: Deposition method and dielectric properties for all BOX materials considered.

Komarov et al., Thermal Mapping of Delphi Thermal Test Dies 27th IEEE SEMI-THERM Symposium

the microresistors made from a gold alloy. The heat generated by the microresistors, due to self-heating joule effect, produces a surface temperature rise that is inversely proportional to the thermal resistance of the BOX structure. Thus by comparing the thermal map of the microresistors one can find which DUT runs cooler and hence find the BOX material that produces the lowest effective thermal resistance. The thermal map was obtained for each BOX sample considered and the results are shown in Fig. 7. The TRTG measurements were made with a light wavelength of 485 nm, which maximizes the value CTR for gold (CTR = -2.2×10-4). The temperature was averaged in a 900 �m2 area in the same location of the microresistors and the data are presented in the second column of Table 3. These results demonstrate the different degree of heat dissipation into the Si substrate through various BOX films. As expected, the highest temperature rise of 115 °C was measured on SiO2 films, and the lowest temperature rise of 79°C was obtained for the silicon nitride BOX sample.

5. Conclusions The work presented here suggests a new approach to

studying the effectiveness of the heat transport on TIM and BOX materials of interest. Thermal resistance measurements of the TIM samples with Delphi test dies revealed the most conductive TIM material as well as proved the applicability of the TRTG method to this class of measurements. Also, the method shows potential for measuring non-uniformity in the temperature field on a test die, which should be helpful to designers in improving these types of test devices.

Thermal resistance measurements of the BOX samples by the use of microresistors point to silicon nitride as the most promising BOX layer, among those tested, in prospective

micro-devices. The measurements reported on in this work also demonstrate the ease with which investigations of this type can be conducted when using the TRTG method. Of course, the use of the TRTG method is not limited to thermal resistance measurements. For existing devices, the highly resolved and accurate map of the 2D temperature field obtained with a TRTG method would provide the ability to detect hot spots, diagnose performance, and assess reliability. In design and manufacturing of new devices, the new tool has the potential to provide a rapid approach for analyzing the thermal behavior of complex stacked structures, identify regions of excessive heat densities, and ultimately contribute to improved thermal designs, better device reliability, and shorter design cycle time.

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Integrated Circuits”, Electronics Magazine, p. 4. 1965. ftp://download.intel.com/museum/Moores_Law/Articles-Press_Releases/Gordon_Moore_1965_Article.pdf

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�a)�400nm�SiO2��

�b)�360nm�DLC��

�

�c)�480nm�Al2O3��

�d)�400nm�Si3N4��

Figure 7: Thermal surface maps of the identical microresistor devices built on top of various BOX materials. Temperature scale is from 0°C (blue) to 100°C (red). The averaged temperature of the resistors is shown in Table 3.

Box Material

Applied Power P, W

Average Delta Temperature

�T, °C

Thermal Resistance

R�=�T.A.P-1 (m2-K/W)

SiO2 4.0 115 5.8×10-7 DLC 4.0 98 4.9×10-7 Al2O3 4.0 86 4.3×10-7 Si3N4 4.0 79 4.0×10-7

Table 3: Applied power, average surface temperature rise, and thermal resistance for the investigated BOX structures.

Komarov et al., Thermal Mapping of Delphi Thermal Test Dies 27th IEEE SEMI-THERM Symposium

Transient Thermal Imaging,” Proc. To the 26th IEEE Semiconductor Thermal Measurement and Management Symposium, pp. 228-234, 2010.

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