An Input Amplitude Modulated Harmonic Outphasing PA

Zeid Abou-Chahine, Tilman Felgentreff Nokia Siemens Networks GmbH − RF Technology

Lise-Meitner-Str. 7, 89081 Ulm, Germany zeid.abou-chahine@ieee.org

Georg Fischer and Robert Weigel Friedrich-Alexander-Universität Erlangen-Nürnberg

Lehrstuhl für Technische Elektronik Cauerstr. 9, 91058 Erlangen, Germany

Abstract—In this paper, an outphasing power amplifier (PA) made using 2x30W GaN HEMTs and operated in deep class-C bias is presented. The design methodology along with some practical design aspects is also considered. The paper reports a working novel operational concept of outphasing with unmatched combiner, showing a potential to deliver more than 40% drain efficiency at 10 dB Power Back Off (PBO).

Keywords—Base stations; load modulation; outphasing architecture; power combining; radiofrequency (RF) amplifiers.

I. INTRODUCTION Driven by an increasing global demand for more mobile

connectivity, telecommunication systems and standards are continuously being subjected to rapid changes and developments. The spectrum’s scarcity of mobile broadband communications has led to the emergence of complex modulation techniques, generally characterized by their high peak-to-average power ratio (PAPR) signals. Consequently, whether it is dedicated for use in handsets or in basetransceiverstations (BTSs), the employed traditional hardware would consume more power when operated with these new schemes. Namely, devices such as power amplifiers (PAs) have shown a corresponding deteriorated average efficiency, initiating therefore a vigorous search for new PA architectures. In this context, a proof of concept outphasing PA design addressed for BTS applications and based on the original Chireix proposal (Fig. 1) [1] is presented. It is shown however how a completely different operational concept of the classical Chireix PA would drastically boost efficiency, revealing a decent potential in the power back off region where BTSs are operated most of the time. The reported design is aimed for the 2.14 GHz band while is tests pertain to a pulsed RF signal.

Fig. 1. Outphasing architecture.

II. DESIGN METHODOLOGY & SIMULATIONS As a starting point, bias settings, input matching and

second harmonic termination were adopted from a previously realized class-E PA using the intended devices (input prematched 030MK Sumitomo transistors). Besides that, the employed design methodology is mainly simulation based. It can be described as follows:

1) Determining Cds and package parasitic admittance and subsequently calculate the compensation element Ycomp.

2) Calculation of the suitable θc in relation to the desired signal amplitude statistics [2] and therefore determining the reactive Chireix elements (+jX and –jX) as in (1).

3) Realization of the circuit shown in Fig. 1 in ADS schematic environment including harmonic terminations, using equation blocks and ideal transmission lines (TLIN)s, and verification of outphasing operation through simulation.

4) Tuning θc, impedance values and/or other variables to reach desired performance.

5) Translation of circuit into Microstrip Transmission Line (MLIN) topology and verification.

6) Translation of the resulting harmonic combiner/balun structure properties into a microstrip element structure, in ADS Momentum environment this time.

7) Tuning and optimization.

During simulations, it was noted that while the 3rd harmonic termination had negligible effects on performance, terminating the transistors with proper 2nd harmonic terminations is essential for high efficiency performance. Fig. 2 shows the impedance tracks that each of the transistors “sees” superimposed on the load pull data on the Smith chart as the outphasing angle is swept. One can conclude that designing a good outphasing PA is equivalent to designing a combiner that allows the associated transistors’ impedances to move on high efficiency tracks throughout outphasing action. Fig. 3 depicts the corresponding instantaneous efficiency as the outphasing angle θ is varied from 0° up to a near 90° value while the input power is held constant. Since the two transistors are all time connected, this makes the design more challenging than other load modulation methods, such as Doherty for instance, where at some time, only one transistor would be operating.

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Subsequently, a layout is generated for this outphasing PA to be driven with external drivers. Two versions of it were made available for testing: one having the drain bias circuitry implemented using lumped elements while the other using distributed ones.

Fig. 2. Simulated individual impedance tracks Gamma1 and Gamma2 during outphasing action superimposed on load pull data of a single transistor.

Fig. 3. Simulated outphasing PA power added efficiency (PAE).

III. MEASUREMENTS As the objective for this design was concept assessment

and development, the signal component separator (SCS) block (Fig. 1) was exchanged for an RF signal generator feeding a driver PA whose output is followed by a 3 dB symmetric power splitter, and a manually adjustable phase shifter connected to one of the available branches (PA2 in this case) after the splitter. Fig. 4 depicts the corresponding setup. The phase shifter emulates outphasing operation by introducing a phase delay that ultimately would have been encoded digitally if an SCS was employed. This allows to fully characterize the instantaneous efficiency of the PA. The SCS however should be included in a final PA demonstrator. The output of the PA under test is connected to an attenuator before reading the output power with a power meter on one channel. The other channel was used for reading the input power just before splitting. In order to avoid burning the transistors when measuring the performance at high power levels, the setup was configured for pulsed measurements. The measurement routine mainly consisted of recording the output power and corresponding DC current for each manually adjusted phase delay. Some measurement results are presented next.

Fig. 4. Measurement setup.

A. Efficiency Fig. 5 shows the measured drain efficiency of the

realized outphasing PA at 2.14 GHz. In this measurement, the input power was set to 33 dBm and the outphasing angle was varied with the mean of the phase shifter. One problem associated with outphasing was the output power’s dynamic range [3]. In this design a 16 dB dynamic range was obtained. This is sufficient for the intended telecommunication application.

Although not optimal as suggested by simulations, the design serves to proof the concept for use in BTSs and validates the design procedure. In such circumstances, the availability of reliable transistor models plays a critical role in developing a superior outphasing PA. A deviation in modeling, for instance of the output impedance of the transistor, would result in a severe discrepancy in reality leading to far from optimum performances. This aspect is vital when dealing with load modulated architecture designs, especially when heavy load modulation is taking place between the transistors as the case with outphasing.

To be considered as well is the selection of gate bias voltage. Proper gate biasing is crucial for good efficiency performance while maintaining a minimum desired output power capability. Although the bias setting was used from an earlier design, running a refinement for finding the new optimum bias point is necessary. Fig. 5 shows that deep class-C voltage levels are beneficial. In the datasheet, the pinch off of the transistor was specified to have a typical -1.5 V value. A gate voltage of -2.25 V was found to be suitable, owing outphasing its LINC (linear amplification with nonlinear components) acronym.

Fig. 5. Measured outphasing PA drain efficiency with different gate bias voltages.

B. Lumped vs Distributed The effect of the additional uncertainty introduced by

employing capacitors in the PAs output matching circuitry is presented. Fig. 6 compares the results obtained after designing the bias circuit using distributed elements to the results of a designed circuit with lumped capacitors in the bias. Even with the availability of powerful simulation tools like ADS, ending up with having to tune the RF board after production is necessary in almost all cases [4]. Employing distributed elements delivers better results with diminished tuning. This however comes mainly at the cost of circuit size.

Fig. 6. Measured outphasing PA efficiency with lumped vs distributed bias circuitries.

IV. INPUT AMPLITUDE MODULATION OUTPHASING Considering its limited choice in up-to-date PA

applications, it could be said that regardless whether isolated (e.g. Wilkinson) or unmatched (Chireix) combining is implemented, the conventional outphasing realization still needs to be modified somehow to be able to serve high PAPR signals with high efficiency. As a result, several variations of it are being proposed, the multilevel asymmetric outphasing [5], [6] being one of the most prominent. For this category, one motivation was to reduce the outphasing angle(s) as it appears in the expression of the Wilkinson combiner efficiency [6], which in turn affects the overall efficiency. That was possible due to the exploitation of multileveling and/or asymmetry in the two signal paths of an isolated combining outphasing PA. Irrespective of the implementation technique, the load presented to the transistors stays constant [6]. Making it in this way helps reduce the power lost in the combiner, but does not allow benefiting from the load modulation concept. This enhances the efficiency beyond original outphasing however limits it below the state of the art Doherty performances, which is currently the typical load modulation architecture for BTSs' PA applications. In the following, a variable amplitude drive scheme is suggested with the Chireix implementation instead.

Basically this consists of having the same topology as the original outphasing [1] however the signal component separator algorithm is exploited in a totally different manner: the split outphased signals are allowed to take on several (continuous/discrete) amplitude levels in accordance with achieving the highest efficiency at each desired output

power level. This means that the input voltage to the PA blocks is not anymore restricted to a constant level. This might look counterintuitive to the understanding of the outphasing concept which is motivated by driving the PAs into saturation all the time with fixed input voltage; however a careful examination of this modification reveals that it results in an essentially improved load modulation behavior enabling higher average efficiencies. While Fig. 2 shows the impedance tracks for the conventional outphasing concept, the corresponding status for IAMO would be the appearance of several impedance tracks each corresponding to an input power level (Fig. 7) and equivalently to a separate load pull data set as well. The resulting measured efficiency performance is shown in Fig. 8.

The test runs in the same way as explained in section three, repeated for different input amplitude power levels. In a digital implementation, for each desired output power level, the SCS assigns the amplitude and phases of the input signals that will result in maximum instantaneous efficiency. Therefore the overall instantaneous drain efficiency curve would be the envelope of the efficiency curves in Fig. 8, i.e. approximated by the dashed green curve. This proof of concept experiment using the same outphasing PA presented in this paper shows more than 50% drain efficiency at 8 dB PBO, a significant improvement from conventional outphasing (around 25% at 8 dB PBO in this case).

Fig. 7. Simulated individual impedance tracks Gamma1 and Gamma2 during outphasing action for different input drive levels.

Fig. 8. Input amplitude modulated outphasing (IAMO) proof of concept experiment measurement results.

The improvement can be interpreted by noting that in practice the transistors are more or less voltage controlled current sources. This is an essential differentiation from the idealistic voltage sources requirement that the Chireix analysis is based on [1], which is violated in practice, for instance by the presence of non-linear-elements such as Cds. Therefore to maintain as ideal-voltage-sources-behavior as possible at the output, the drain current needs to be controlled stabilizing in turn the voltage amplitude; that could be realized by using input amplitude control. IAMO allows restoring the drift in the voltage, thus more approaching the idealistic Chireix efficiency performance (Fig. 9). The IAMO simulations using GaN large signal transistor models for a 15° θc compensation are presented in Fig. 10. The envelope of the efficiency curves finely matches this understanding. Furthermore, the PBO peak given by (2) of the ideal Chireix analysis is largely validated. This approximates to 11.74 dB PBO for a selected 15° θc.

Fig. 9. Chireix drain efficiency with ideal Class-B transistors [2].

Fig. 10. IAMO simulations with GaN HEMTs’ large signal models for θc=15°.

V. CONCLUSION In this paper, a 60W outphasing PA dedicated to the

evaluation of this specific architecture for use in next generation BTSs was presented. A design methodology was validated and some practical design aspects were considered. It was found that the realization of a competitive outphasing PA critically depends on the reliability of the

transistor models. A novel PA concept based on original outphasing was revealed as well. IAMO further exploits the load modulation technique in order to improve RF PAs efficiency. Benefiting from today’s advanced DSP hardware for a fast SCS, the concept would enable therefore a practical approach to the implementation of the ideal Chireix architecture. The novel concept was proofed with measurements: it exhibited more than 50% efficiency at 8 dB PBO, exposing a promising potential in the race for high efficiency PA architectures. An improved digitally driven design is planned for the future.

REFERENCES [1] H. Chireix, "High power outphasing

modulation," Proceedings of the Institute of Radio Engineers , vol. 23, no. 11, pp. 1370- 1392, November 1935.

[2] F. Raab, "Efficiency of outphasing RF power-amplifier systems," IEEE Transactions on Communications , vol. 33, no. 10, pp. 1094- 1099, October 1985.

[3] R. Beltran, F.H. Raab, and A. Velazquez, "HF outphasing transmitter using class-E power amplifiers," 2009 IEEE MTT-S Int. Microwave Symp. Dig., pp.757-760, June 2009.

[4] S.K. Patro, Y. Buch, and R.B. Kishore, "Effective use of ceramic capacitor tuning sticks for impedance matching," High Frequency Electronic, vol. 6, no. 9, pp. 20-26, September 2007..

[5] K.-Y. Jheng, Y.-J. Chen, and A.-Y. Wu, "Multilevel LINC system designs for power efficiency enhancement of transmitters," IEEE Journal of Selected Topics in Signal Processing, vol. 3, no. 3, pp. 523- 532, June 2009.

[6] Z. Abou-Chahine, T. Felgentreff, G. Fischer, and R. Weigel, "Efficiency analysis of the asymmetric 2-level outphasing PA with Rayleigh enveloped signals," 2012 IEEE Topical Conference on Power Amplifiers for Radio and Wireless Applications (PAWR), vol. 41, pp. 85- 88, January 2012.