A Simulator for Flexible Sensor Nodes in Wireless Networks

Jingyao Zhang, Srikrishna Iyer, Patrick Schaumont, and Yaling Yang

Department of Electrical and Computer EngineeringVirginia Polytechnic Institute and State University

Blacksburg, Virginia 24060Email: {jingyao, skr, schaum, yyang8}@vt.edu

Abstract—Most current sensor nodes are composed of amicrocontroller and a radio. Their real-time and peak per-formance would be a bottleneck when executing compute-intensive tasks. Several works demonstrate that addinga hardware co-processor could accelerate the executionspeed of the sensor nodes. So far, no simulators cansimulate these new sensor nodes in wireless networks.An extension to SUNSHINE [1], a hardware-softwareemulator is developed to fill the void.

Keywords-Simulator; FPGA; sensor nodes; wireless sen-sor network

I. INTRODUCTION

Real-time performance is one of the most crucial

metrics for wireless sensor networks when executing

time-sensitive tasks. Compared with fixed circuits of

CPU on current sensor nodes, FPGA can configure

and combine logic blocks to execute tasks according

to the specific characteristics of applications in parallel.

Hence, the addition of a hardware coprocessor, such

as an FPGA, to a fixed sensor platform can increase

the execution speed of many applications as shown

in [3] [4]. In addition, the peak performance of sensor

nodes would be higher by incorporating the hardware

coprocessor. However, a sensor node with an add-on

FPGA is not always beneficial for all applications due

to the overhead of communication between the hardware

coprocessor and CPU. Whether the sensor platform

with FPGA will outperform fixed sensor platform is

application specific. Therefore, it is very important

for a designer to evaluate the pros and cons of both

flexible and fixed sensor platforms before their actual

development of sensor networks.

Due to the cost of setting up and debugging pro-

totype of sensor networks, evaluating applications of

sensor networks in simulation is a more economical

choice before building real networks. Unfortunately,

current sensor network simulators such as TOSSIM [5],

Atemu [6], and Avrora [7] only simulate fixed sensor

platforms. Even though ModelSim [8] and GEZEL [9]

can predict the behaviors of FPGAs, they do not support

simulation of wireless channels so that these simulators

cannot simulate the behaviors of nodes in wireless

network environment. The incapability of emulating

flexible sensor nodes in wireless networks limits the

development of sensor nodes with new hardware archi-

tectures.

In our previous work, we developed SUNSHINE

framework [1], which is an emulator for sensor net-

works that accurately simulates the hardware-software

interactions of sensor nodes in network environment.

SUNSHINE integrates P-sim (integrated simulation tool

as a component of SUNSHINE) and TOSSIM. SUN-

SHINE scales to large networks via the combined

simulation of cycle-accurate nodes simulated by P-sim

(called co-sim nodes) and event-based nodes simulated

by TOSSIM (called TOSSIM nodes) [1]. In SUNSHINE

simulation, fine-grained cycle-level nodes behaviors can

be captured in co-sim nodes while only coarse-grained

nodes behaviors are captured in TOSSIM nodes. How-

ever, one key feature of SUNSHINE, supporting emula-

tion of flexible sensor nodes in wireless networks, was

not developed at that time. In this paper, we discuss how

we extended SUNSHINE to realize this key feature.

Several challenges were encountered when we ex-

tended SUNSHINE to simulate flexible sensor nodes in

wireless network context. One of the challenges is how

to build a simulator to support simulation of hardware-

software components together. For example, how the

simulator can coordinate activities of microcontroller,

hardware coprocessor and radio; how the simulator can

configure hardware architectures of sensor nodes in

simulation; and so on. The other challenge is to make

the simulator be able to simulate cycle-accurate co-sim

nodes (including both flexible and fixed sensor nodes)

and TOSSIM nodes in one simulation. The need for

mixed simulation is because of the following reasons.

On one hand, to accurately capture the cycle-accurate

behaviors of co-sim nodes, the simulator has to spend

much time to simulate the detailed behaviors of sensor

nodes at cycle level, which would take much more

time than only simulating TOSSIM nodes at event

level. The low simulation speed prevents the simulator

to scale to large network if all of the nodes in the

network are totally composed of cycle accurate sensor

nodes. To speed up the simulator’s execution speed,

it is reasonable to incorporate event level nodes in

2011 Seventh International Conference on Mobile Ad-hoc and Sensor Networks

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2011 Seventh International Conference on Mobile Ad-hoc and Sensor Networks

978-0-7695-4610-0/11 $26.00 © 2011 IEEEDOI 10.1109/MSN.2011.93

373

2011 Seventh International Conference on Mobile Ad-hoc and Sensor Networks

978-0-7695-4610-0/11 $26.00 © 2011 IEEEDOI 10.1109/MSN.2011.93

373

simulation. On the other hand, for many actual network

applications, not all of the nodes need to be simulated

at cycle level. Nodes that are responsible for executing

compute-intensive tasks should be simulated at cycle

level in SUNSHINE. For nodes that are only responsible

for relaying messages, it is suitable to simulate them at

event level.

Therefore, incorporating TOSSIM nodes is a fea-

sible choice in SUNSHINE simulation. SUNSHINE

supports simulation of co-existence of TOSSIM nodes

and cycle-accurate co-sim nodes including flexible and

fixed nodes. Based on this functionality, to accelerate

the simulator’s runtime, it is feasible for SUNSHINE

to simulate crucial nodes at cycle level, while other

nodes at event level. As a result, the co-existence of

different types of nodes makes SUNSHINE scale to

large networks.

In this paper, we present the extension of SUN-

SHINE1 to realize the above functionalities.

Figure 1. SUNSHINE Architecture for Flexible Sensor Nodes

II. SYSTEM ARCHITECTURE

Figure 1 presents the architecture of SUNSHINE,

which is an extension of [2]. The flexible sensor node

is composed of a microcontroller, a radio and a FPGA.

The microcontroller interacts with the other two com-

ponents using SPI, where the microcontroller works as

a master, while the other two are slaves. Two appli-

cations are needed, one is TinyOS application, which

is used to specify the behaviors of the microcontroller,

the other is GEZEL code, which is used to configure

the architecture of sensor node and the application

running on FPGA. In simulation, the microcontroller

is simulated by SimulAVR, while the FPGA and the

1SUNSHINE is an open source project. For more information,please check http://rijndael.ece.vt.edu/sunshine/index.html.

radio are emulated by GEZEL simulation kernel, and

the wireless channel is simulated by TOSSIM. To be

specific, SimulAVR interprets binaries compiled from

TinyOS applications, and interacts with FPGA and radio

emulated by GEZEL. The sensor node transmits or

receives data to or from other nodes via wireless channel

that is simulated by TOSSIM. For actual hardware

prototype, both TinyOS application and GEZEL code

can be compiled to binaries that can be loaded on

actual hardware. GEZEL, a cycle-accurate hardware

description language is used to configure the hardware

architecture of sensor nodes. The snippets of GEZEL

code are listed as follows:

1 i p b l o c k a v r { / / s p e c i f y m i c r o c o n t r o l l e r2 i p t y p e ” a tm128core ” ;3 ipparm ” exec =app ” ;4 ipparm ” fcpuMhz=8” ;5 ipparm ” asnyc t ime rkHz =32.768 ” ;}6 i p b l o c k m cc2420 ( / / s p e c i f y r a d i o7 out f i f o , f i f o p , cca , s f d : ns ( 1 ) ;8 in s s r , sck , mosi : ns ( 1 ) ;9 out miso : ns ( 1 ) ) {

10 i p t y p e ” i p b l o c k c c 2 4 2 0 ” ;11 ipparm ” node id = 1 ” ; }12 dp hw top ( / / c o n f i g u r e FPGA13 in s s : ns ( 1 ) ;14 in sck : ns ( 1 ) ;15 in mosi : ns ( 1 ) ;16 out miso : ns ( 1 ) ) {17 . . . . . . } / / codes r u n n i n g on FPGA

As shown in the snippets, three blocks are included.

The first block “ipblock avr{}” specifies a 8 Mhz

Atmega128 microcontroller with a 32.768Khz asyn-

chronous timer that executes a binary “app”. The second

block “ipblock m cc2420{}” specifies a CC2420 radio

that uses SPI to communicate with the microcontroller.

The last block “dp hw top()” configures the applications

running on FPGA and the communication protocol

(SPI) used to interconnect the FPGA with the micro-

controller. With the support of GEZEL, SUNSHINE can

design and simulate flexible sensor nodes.

III. CHARACTERISTICS OF SUNSHINE

SUNSHINE has the followings characteristics:

Flexibility: SUNSHINE designs flexible hardware

architecture of sensor nodes at configuration step before

simulation. In addition, SUNSHINE supports to add

a hardware accelerator when nodes have to execute

compute-intensive tasks.

Compatibility: Nodes running TinyOS applications

can be simulated in SUNSHINE. This is essential be-

cause TinyOS is the dominating operating system for

wireless sensor networks.

Accuracy: SUNSHINE accurately captures the be-

haviors of sensor nodes at cycle level. This ensures that

the behaviors of sensor nodes estimated by SUNSHINE

are close to the measurement results of actual boards.

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Bridging: SUNSHINE bridges the gap between de-

sign and implementation of flexible sensor nodes’ appli-

cations. The applications evaluated by SUNSHINE can

be loaded and run on actual hardware.

IV. EXPERIMENTS

A. Real-time Comparison

Three applications: AES-128, CubeHash-512 and

Cordic algorithms are used to make the comparison

among different working schemes. We simulated each of

these algorithms running on different processors: micro-

controller (SW), FPGA (HW), and microcontroller with

FPGA (HW-SW). The HW-SW let the microcontroller

send data to FPGA and let FPGA execute the relevant

algorithms based on the input data and then, send the

data back.

Table IPERFORMANCE COMPARISON RESULTS

SW HW HW-SW HW HW-SW

cycles cycles cycles speedup speedup

Aes 14321 12 3858 1193.42 3.71

CubeHash 9813059 1354 46640 7247.46 210.4

Cordic 4537 22 794 206.23 5.71

As shown in Table I, all the three algorithms need

much more execution time on software than on hard-

ware. The reason why HW-SW speedup is not as

significant as HW is that the communication between

microcontroller and FPGA takes time. The execution

speed can be further accelerated by using efficient com-

munication protocols. In addition, it is wise to incorpo-

rate a hardware accelerator for compute-intensive tasks

with short input data. Therefore, when met compute-

intensive algorithms, adding a hardware co-processor

would help sensor nodes meet real-time requirement.

B. Scalability

In the experiment, nodes are randomly distributed

from 2 to 128 and are paired to communicate with

each other. The simulation ends when every reception

node receives a packet from its neighbor. For AES

application, only 25% nodes are emulated as flexible

nodes, others nodes are simulated by TOSSIM. In

Figure 2, wall clock time represents the simulator’s run

time. As the Figure shows, SUNSHINE slows down

when simulating 128 nodes. This is reasonable because

SUNSHINE needs to simulate the behaviors of sensor

nodes on both software (microcontroller and radio) and

hardware (FPGA). SUNSHINE has to spend much time

on capturing detailed and accurate information of the

flexible sensor nodes.

ACKNOWLEDGMENT

This work is supported by National Science Founda-

tion award CCF-0916763.

0 20 40 60 80 100 1200

50

100

150

200

250

number of nodes

wal

l clo

ck ti

me

(s)

100% cycle−accurate nodes50% cycle−accurate nodes25% cycle−accurate nodes25% cycle−accurate nodes with FPGAs

Figure 2. Scalability

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