ic 封裝新技術發展趨勢

Download Ic 封裝新技術發展趨勢

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  • IC

    2016/05/30

    Kent Yang +886-988267432

  • Content

    1.

    2. , IOT &

    3.

    3.1 POP (Package on Package,AP) 3.2 BOT (Bump On Trace, Flip Chip ) 3.3 SIP (System In Package, ) 3.4 2.5D/3D+ TSV (3D SIP/Memory ) 3.5 FOWLP (Fan Out WLP,16nm) 3.6 Substrate Level Die Embedded () 3.7 FOWLP SIP (SIP) 4.

  • 1.1 - IC

    : ,

    cost

    : high pin count

    : Fine flip chip

    bump pitch/ Low

    Cost/

    :

    : High pin count/

    high performance

    : /

    150um bump

    pitch

    : Fine pitch /

    : ,

    : /

    :

    ACF/ACP

    Bond

    LCD Driver/

    Eutectic

    Bond

    LCD Driver/ high

    power LED

    BOT

    BOL

    Bump on

    Trace

    Bump on Line

    AP(MTK),

    C4

    bump flip chip

    Flip ChipFlip Chip

    AP, CPU,

    GPU high pin

    count/ high

    performance

    Bonding Type

    Wire

    Bond

    Wire

    Bond

  • 1.2 -

    DIP

    (Dual in-line Package)

    QFP

    (Quad Flat Package)

    PGA

    (Pin Grid Array)

    LGA

    (Land Grid Array)

    BGA

    (Ball Grid Array)

  • 2. , IOT & -1

    : PCB, SMT, ,

    : PCB, SMT, ,

    Bare Chip

  • 2. , IOT & -2

    iPad

    iPhone6

    iWatch (SIP)

    FOWLP

    Bare Chip

  • 2. , IOT & -3

    iWatch (SIP)

  • 3.

    POP

    BOT

    FOWLP

    SBT Level Die

    Embedded

    SIP

    TSV

  • RAM

    3.1.1 POP (Package on Package,AP)

    APRAM,

  • 3.1.2 POP

    Flip Chip Bonding

    Top Side Ball Mount

    Molding

    BGA Ball Mount

    Package on Package

    Mounting

    Laser Drill

  • 3.1.3 POP Challenge

    PoP ball pitch

    0.4mm0.3mm

    -> touch

    Interproser

    Cu Pillar

    Au stop

    Bond

    Die, Chip

  • 3.2.1 BOT (Bump On Trace, Flip Chip )

    Solder Bump

    BOL(BOT) Bump

    UBM

    Ball Pad

    Pillar

    Trace

    Bump Pitch:

    130~180um

    Trace Pitch:

    40~50um

    Smaller bump pitch is capable

  • 3.2.2 BOT

    Flux Coating

    Flux Coating

    Cu Pillar

  • 3.2.3 BOTChallenge

    -Smaller bump (trace) pitch

    -Trace embedded (Adhesion)

    -Solder bleeding issue

    Trace embedded

    bump

  • 3.3.1 SIP (System In Package, )-1

    Package

    1.Chip on board, ,

    2.(package),

    3.()

    4.SIP, , so ,,

    5.SIP, IOT

    Bare Chip

    Component

  • 3.3.1 SIP (System In Package, )-2

    /IC,,life time

    SoC SIP, SIP

    ,

  • 3.3.2 SIP -1

    Component & package

    mounting

    Bare chip assembly

    Testing

    1.

    2. High Performance()

    3. Reduce time to market

    4. Turkey Service()

    5. Lower overall Cost

    Molding

    EMI

  • 3.3.3 SIP Challenge

    1. (, )

    , SIP

    2. (())

    3.

    4. Flux//Jet

    5. ,

    6. (Sputter EMI shielding)

    7.

  • 3.4.1 2.5D/3D+ TSV (3D SIP/Memory ) -1

    1. Memory Die, 16Die

    2.TSV,,

  • 2.5D(CoWoS, Chip on Wafer on Substrate) 3D

    Interproser

    1. 2.5D/3D SIP /Interproser

    2. 2.5D Interproser Interproser

    3.4.1 2.5D/3D+ TSV (3D SIP/Memory ) -2

  • 3.4.2 3D TSV

    Via Last

  • 3.4.2 2.5D/3D+ TSV Challenge

    1. TSV IC/Full 3D

    2. TSVCMOS Sensor, MEMs, Memory

    3. SIP (2.5D&3D)

  • 3.5.1 FOWLP (Fan Out WLP,16nm)

    , low pin count

    Fan in WLP Fan out WLP()

    Fan out, , high pin count ,

    16nm ,, FC

    Chip

  • 3.5.2 FOWLP

    Fan in WLP Process Flow

    Fan out WLP Process Flow

  • 3.5.3 FOWLP Challenge

    1.

    2. ()

    3. Warpage (8 or12 Organic RDL)

    4. Chip alignment & Shift (Temp. film , moldingShift)

  • 3.5.4 FOWLP -1

    I/O pitch

    performance 16nm finer bump pitch

    Flip Chip Fan out

    Chip: Pillar/solder Bump

    IC Substrate/ Solder Bump

    w/o Pillar/solder Bump (only UBM)

    Chip

    No need

    Substrate

  • 3.5.4 FOWLP -2

    FOWLP Chip

    Flip Chip*3 Fan out *3

    Chip

    No need

    Substrate

    + + +

    Chip Chip

    Chip-1 Chip-2 Chip-3

  • 3.6.1 Substrate Level Die Embedded ()-1

    Substrate Level SIPRF Power IC

    ICFan out, 3D

  • 3.6.1 Substrate Level Die Embedded ()-2

  • 3.6.1 Substrate Level Die Embedded ()-3

    TDK ASE ,

    3949USD,51%

  • 3.6.2 Substrate Level Die Embedded

  • 3.6.3 Substrate Level Die Embedded Challenge

    1. Die(or component) embedded

    2. Wafer DB handling Die embedded

    3. Wafer

    4. Resource Substrate level SIP

  • 3.7.1 FOWLP SIP (SIP)

  • 4.

    1. SMT SIP

    2. SIP HDIMSAP component embedded HDI

    3. IC

    A.SIPFOWLP SIP

    (MSAP/SAP2/2/23/2/3)

    B. Substrate Level die embedded for SIP

    Wafer

    4. SIPFOWLP/ FO SIPSubstrate level die embedded

    5. FOWLP/FO SIP Turkey