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High Speed ClockDistribution DesignTechniques for CDC509/516/2509/2510/2516

APPLICATION REPORT: SLMA003A

Boyd Barrie Bus Solutions

Mixed Signals DSP Solutions September 1998

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ContentsAbstract ....................................................................................................................... .. 7Product Support ........................................................................................................... 8

World Wide Web ....................................................................................................... 8Email......................................................................................................................... 8

Introduction................................................................................................................... 9Clock Terminology...................................................................................................... 10Basic Operation .......................................................................................................... 11Operating Modes......................................................................................................... 13

Zero Delay Buffer.................................................................................................... 14Power Supply Considerations ................................................................................... 15Output Termination..................................................................................................... 16Board Layout Considerations for Signal Integrity and EMI ..................................... 17Typical Characteristics Curves CDC509/ CDC516..................................................... 19

FiguresFigure 1. CDC509/2509 Functional Block Diagram ......................................................... 11Figure 2. CDC516 Functional Block Diagram .................................................................. 12Figure 3. CDC509/2509 Device Configurations ............................................................... 13Figure 4. PC DRAM Configuration................................................................................... 14Figure 5. Typical Application Circuit ................................................................................ 16Figure 6. Phase Error vs. Clock Frequency ..................................................................... 19Figure 7. Duty Cycle vs. Clock Frequency....................................................................... 19Figure 8. Analog ICC vs. Clock Frequency...................................................................... 20Figure 9. Phase Error vs. Clock Frequency ..................................................................... 20Figure 10. Duty Cycle vs. Clock Frequency..................................................................... 21Figure 11. Analog ICC vs. Clock Frequency.................................................................... 21Figure 12. Dynamic ICC vs. Clock Frequency ................................................................. 22

TablesTable 1. Mode Summary ................................................................................................. 14

High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 7

High Speed Clock DistributionDesign Techniques for CDC

509/516/2509/2510/2516

Abstract

The memory bandwidth of high performance microprocessors isincreasing at a rapid rate and the future memory bandwidthrequirements are expected to keep increasing. The bandwidthrequirements of RAM will be satisfied in the near term by usingSynchronous DRAM. The need to drive multiple DRAM chips athigh speeds with low skew necessitates the use of clockdistribution devices with Phase Locked Loop (PLL) technology.

To meet the designer’s need for high-performance clock systemcomponents, Texas Instruments has developed PLL Clock Driversthat push the clock speeds up to 125 MHz. The focus of thisapplication note will be on Clock Distribution chips specificallydesigned for use with Synchronous DRAMs. The clock driverseries designed for buffered SDRAM applications includesCDC509, CDC516, CDC2509, CDC2510 and CDC2516. Some ofthe advanced features offered by these chips include:

� Phase-Lock Loop Clock Distribution for Synchronous DRAMapplications

� Distributes one clock to multiple outputs in a banked mode� External Feedback (FBIN) pin is used to Synchronize the

Outputs to the Clock Input� No External RC Network Required� Operates at 3.3-V Vcc� Packaged in Plastic Thin Shrink Small-Outline Package� Series or parallel termination options

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8 High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516

Product Support

World Wide Web

Our World Wide Web site at www.ti.com/sc/cdc contains the mostup to date product information, revisions, and additions. Usersregistering with TI&ME can build custom information pages andreceive new product updates automatically via email.

Email

For technical issues or clarification on switching products, pleasesend a detailed email to [email protected]. Questions receive promptattention and are usually answered within one business day.

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Introduction

The memory bandwidth of high performance microprocessors isincreasing at a rapid rate and the future memory bandwidthrequirements are expected to keep increasing. The bandwidthrequirements of RAM will be satisfied in the near term by usingSynchronous DRAM. The need to drive multiple DRAM chips athigh speeds with low skew necessitates the use of clockdistribution devices with Phase Locked Loop (PLL) technology.

To meet the designer’s need for high-performance clock systemcomponents, Texas Instruments has developed PLL Clock Driversthat push the clock speeds up to 125 MHz. The focus of thisapplication note will be on Clock Distribution chips specificallydesigned for use with Synchronous DRAMs. The clock driverseries designed for buffered SDRAM applications includesCDC509, CDC516, CDC2509, CDC2510 and CDC2516. Some ofthe advanced features offered by these chips include:

� Phase-Lock Loop Clock Distribution for Synchronous DRAMapplications

� Distributes one clock to multiple outputs in a banked mode

� External Feedback (FBIN) pin is used to Synchronize theOutputs to the Clock Input

� No External RC Network Required

� Operates at 3.3-V Vcc

� Packaged in Plastic Thin Shrink Small-Outline Package

� Series or parallel termination options

The designer has the option of using either CDC2xxx or CDC5xxseries of clock drivers. The CDC2509 provide the same functionsas the CDC509, but also include series-damping resistors toimprove signal integrity without increasing component count, seeFigure 1. The CDC516 is a scaled version of the CDC509, withthe CDC516 having sixteen outputs instead of nine, see Figure 2.Though these chips were designed for SDRAM applications, thedesigner should not limit the scope to which these chips can beused.

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Clock Terminology

Peak-to-Peak-Jitter (Period Jitter) , is defined as the upper andlower bounds of a distribution of a large number of samples ofcycle-to-cycle period measurements from ideal. In reference to aPLL, the period jitter is the worst case period deviation from idealthat would ever occur on the output of the PLL.

Output Skew - t sk(o) , is the difference between two concurrentpropagation delay times that originate from a single input, ormultiple inputs switching simultaneously and terminating atdifferent outputs.

Board Skew - t sk(pcb) , is introduced into the clock system byunequal trace lengths and loads. It is independent of the skewgenerated by the clock driver. It is important to keep line lengthsequal to minimize board skew.

Electrical Length , is the distance a signal or clock travels in aspecified length of time in a specified media.

Early Clock , is a clock generated by a phase locked loop whosephase is leading that of the input to the PLL. The output clock isgenerated before the input clock arrives.

Late Clock , is a clock generated by a phase locked loop whosephase is lagging that of the input to the PLL. The output clock isgenerated after the input clock arrives.

Static Phase Error - t ph(in-fb) , is the static phase offset of thereference input clock and the feedback input to the PLL.

Period Jitter (Cycle-to-Cycle) , is the difference in the period ofsuccessive cycles of a continuous clock pulse.

Accumulated Phase Error , is the static phase error plus (orminus) the cycle to cycle jitter across n cycles.

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Basic Operation

A clock distribution chip consists of a Phase Locked Loop (PLL)system that is buffered to one or more outputs. The output clocksare controlled in banks with “1G” and “2G” enabling each bank asshown in Figure 1 below.

The PLL is a closed loop system designed so that there isnominally zero phase error between CLK and FBIN. Phasecompensation is achieved by adjusting the propagation delay inthe feedback line. The feedback line is a microstrip or striplinetrace that connects the FBOUT to the FBIN. The propagationdelay is a function of the velocity of propagation and the microstripor stripline trace length.

Figure 1. CDC509/2509 Functional Block Diagram

ENB

ENB

ENB

ENB

ENB

ENB

ENB

ENB

3

4

5

8

21

20

16

17

1Y0

1Y1

2Y1

2Y0

1Y3

1Y2

2Y2

2Y3

FBOUT

1G

2G

CLK

FBIN

AV CC

PLL

2312

13

24

14

11

ENB 9 1Y4

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Figure 2. CDC516 Functional Block Diagram

ENB

ENB

ENB

ENB

ENB

ENB

ENB

ENB

31

30

27

26

47

46

42

43

3Y0

3Y1

4Y1

4Y0

3Y3

3Y2

4Y2

4Y3

FBOUT

3G

4G

CLK

FBIN

AV CC

PLL

ENB

ENB

ENB

ENB

18

19

22

23

2Y0

2Y1

2Y3

2Y2

2G

ENB

ENB

ENB

ENB

2

3

6

7

1Y0

1Y1

1Y3

1Y2

1G

1135

37

12

40

33

16

9

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Operating Modes

The CDC2509 has many modes of operation which aid thedesigner in trouble shooting, reducing power consumption andminimizing EMI. On the CDC2509 banked operation is achievedby using 1G and 2G to enable or disable banks 1Y and 2Yrespectively. If a bank is disabled (1G or 2G is logic low) then theoutput clock is pulled to a low state as shown in Figure 3. Asummary of all normal modes of operation is given in Table 1. Theenable/disable feature provides a method of disabling all or part ofthe clock output without the need for PLL restoration. Thus, thedesigner can maintain signal integrity and still can use on/offoperation as a measure for reducing power consumption andradiated emissions.

Additionally, the designer can disable the PLL by taking AVCC toground. This places the chip in a bypass test mode. In this mode,the input clock is buffered directly to the output. Therefore, theoutput clock will be only be delayed by the output buffer. Bydisabling and enabling the PLL, the designer can compare thecharacteristics of the PLL. This will aid the designer in evaluatingjitter characteristics and phase differences created by the PLL.

Figure 3. CDC509/2509 Device Configurations

FBIN FBOUT

Y1(0:4)

Y2(0:3)

CLK

CDC25091G

2G

25-125 MHz

Vcc

FBIN FBOUT

Y1(0:4)

Y2(0:3)

CLK

CDC25091G

2G

25-125 MHz

Vcc

FBIN FBOUT

Y1(0:4)

Y2(0:3)

CLK

CDC25091G

2G

25-125 MHz

FBIN FBOUT

Y1(0:4)

Y2(0:3)

CLK

CDC25091G

2G

25-125 MHz

Vcc

FBIN FBOUT

Y1(0:4)

Y2(0:3)

CLK

CDC25091G

2G

X

X

FBIN FBOUT

Y1(0:4)

Y2(0:3)

CLK

CDC25091G

2G

25-125 MHz

VccAVCC

BYPASS MODE

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Table 1. Mode Summary

INPUTS OUTPUTS

1G 2G CLK1Y

(0:4)2Y

(0:3)FBOUT

X X L

L L H

L H H

H L H

H H H

L L L

L L H

L H H

H L H

H H H

Zero Delay Buffer

A typical SDRAM application configured as a zero delay buffer isshown in Figure 4. The PLL of the CDC2509 generates an earlyclock that results in the clock edge arriving at the loads at thesame time that the clock arrives at the clock buffer input. This isachieved by matching the propagation delay of the output to load(tPD(LOAD)) with the propagation delay of the feedback line (tPD(FB)).This effectively compensates for the propagation delay throughthe output PC board traces.

To ensure that each load is clocked at the same time, thedesigner should route output clock traces with matched lengths.Additionally, clock signal quality can be ensured by matching andcontrolling trace impedance and loading. Typically, each output iscapable of driving five loads or a total capacitance of 30pF.

Figure 4. PC DRAM Configuration

FBIN

25-125 MHz

1Y(0:4), 2y(0:3)

U9

U8

U7

U6

U5

U4

U3

U2

U1

CDC 2509

FBOUT

tP D ( f b )

tP D ( l o a d )

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Power Supply Considerations

The CDC509, CDC516, CDC2509, CDC2510 and CDC2516family of clock drivers uses a precision integrated analog PLL thatis sensitive to noise on the analog power and ground pins. Noiseon the analog supply line can significantly increase the output jitterand the total system skew margin. For best performance results, afilter network as shown in Figure 5 should be utilized.

The filter may be designed using an inductor, ferrite bead or aresistor as a noise mismatch component. The designer shouldchoose the approach that meets the application jitter toleranceand cost compromise. For best results, all components should beplaced as close as possible to the pins of the device. To maximizeRF decoupling, the use of surface mount components isrecommended. Choose capacitors with low parasitic inductanceand keep lead lengths as short as possible.

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Output Termination

To avoid poor clock transmission quality, it is be necessary to useeffective line termination techniques. The correct method ofterminating an output clock is dependent on the specificapplication. If multiple loads are to be driven off the same clockoutput then an RC termination may be necessary to balanceoutput loading. If the output clock is not used, then the output canbe left either unterminated or RC terminated as shown in Figure 5.The unterminated approach does not affect performance and isrecommended because of lower power consumption and a lowercomponent count.

Figure 5. Typical Application Circuit

NOTES:

1) The recommended method of terminat ing unconnected c lock outputs is open c i rcu i t . Warn ing: Unused or unconnected c lock outputs should never be t ied to ground. 2) RC terminat ion is acceptable and may be necessary to balance d is t r ibut ion loading.

AGND1

Vcc2

31Y0

41Y1

CLK

AVcc

Vcc

2Y0

24

23

2221

1Y25

GND6

7GND

81Y3

2Y1

GND

GND2Y2

20

19

1817

1Y49

Vcc1011 1G12 FBOUT

2Y3

Vcc

2G

FBIN

16

15

14

13

CDC 2509

SDRAM

SDRAM

SDRAMNC

SDRAM

NC

3) NC - No connect ion

NC

NC

NC

NC

NC

4.7 uF 4.7 uF 220 nF 2.2 nF

R = 10 - 15 Ohms

CLK IN

DigitalD V C C

DVCC

DVCC

DVCC

DVCC

4.7 uF

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Board Layout Considerations for Signal Integrity and EMI

The following are general guidelines for proper clock buffer layoutand usage. These suggestions may help the designer reduceradiated and conducted emissions and improve signal quality.This list is not entirely inclusive and it is up to the designer toresearch those techniques that will be most beneficial to thedesign.

� Match consistent impedance of signal lines by using either apower or a ground plane to form a (micro)strip line.

� Do not route traces closer to the edge of the PCB board than 3times the height above the image plane (or 3 x layerthickness).

� Face the power plane with its return ground plane and have nosignal trace layers in between.

� Maintain impedance control for all clock traces. Calculateimpedance for both microstrip and stripline. Minimizeimpedance mismatches by reducing the number vias andconnectors. If an impedance mismatch is necessary, keep themismatch as close to the clock source as possible.

� Be aware of differences in propagation delays of signal tracesrouted through microstrips versus those routed throughstriplines. Microstrip allows for fastest transition of signaledges while permitting greater amounts of RF energy to beradiated. Stripline provides more shielding but transition timesare slower.

� Calculate capacitive loading of all components and properlycompensate with a series resistor and/or end termination.

� Decouple clock components (VCC) with capacitors having aself-resonant frequency (that frequency above which thecapacitor looks resistive) higher than the clock harmonicsrequiring suppression. Place capacitors near the clock chipand avoid long trace lengths.

� Minimize or eliminate use of vias to route clock traces. Viasadd inductance to the trace. Vias could change the traceimpedance causing reflections of EMI emissions.

� Do not locate clock signals near I/O areas.

� Keep trace impedance as balanced as possible and keeptraces as short as possible to minimize reflections, ringing, andcreation of RF common mode currents.

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� Route clock traces on one routing plane only. This layer mustbe adjacent to a solid (image) plane at all times. If possible,route all clock traces using stripline.

� If possible, create localized ground and VCC planes on the toplayer of the PCB. The localized ground plane can residebeneath the chip while the VCC plane can surround the chip.Tie the ground and VCC planes to their respective main plane.These localized planes will provide a path for RF currents toreturn to the ground plane via the localized planes to itsrespective reference plane at many points.

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Typical Characteristics Curves CDC509/CDC516

Figure 6. Phase Error vs. Clock Frequency

Phase Error CDC509 (typical)(Vcc= 3.3V, Ta=25 deg. C)

-400.0E-12-200.0E-12

000.0E+0200.0E-12

400.0E-12600.0E-12

800.0E-121.0E-9

1.2E-9

35 55 75 95 115 135

Clock Frequency [MHz]

Pha

se E

rror

[s]

Figure 7. Duty Cycle vs. Clock Frequency

Output Duty Cycle CDC509 (typical)(Vcc= 3.3V, Cl= 30pF)

43

45

47

49

51

53

55

57

30E+6 40E+6 50E+6 60E+6 70E+6 80E+6 90E+6 100E+6 110E+6 120E+6 130E+6

Clock Frequency [Hz]

Dut

y C

ycle

[%]

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Figure 8. Analog ICC vs. Clock Frequency

Analog ICC at AVCC CDC509 (typical )(Vcc= 3.3V, T= 25 deg C)

0.00

2.00

4.00

6.00

8.00

10.00

25 35 45 55 65 75 85 95 105 115 125


AIC

C [m

A]

Figure 9. Phase Error vs. Clock Frequency

Phase Error CDC516 (typical )(Vcc= 3.3V, Ta=25 deg. C)

-600E-12

-500E-12

-400E-12

-300E-12

-200E-12

-100E-12

000E+0

100E-12

200E-12

300E-12

400E-12

500E-12

35 55 75 95 115 135


Pha

se E

rror

[s]

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Figure 10. Duty Cycle vs. Clock Frequency

Output Duty Cycle CDC516 (typical)(Vcc= 3.3V, Cl= 30pF)

43

45

47

49

51

53

55

57

30E+6 50E+6 70E+6 90E+6 110E+6 130E+6


Dut

y C

ycle

[%]

Figure 11. Analog ICC vs. Clock Frequency

Analog ICC at AVCC CDC 516 (typical)(Vcc= 3.3V, T= 25 deg C)

0.001.002.003.004.005.006.007.008.009.00

10.00

25 35 45 55 65 75 85 95 105 115 125


AIC

C [m

A]

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Figure 12. Dynamic ICC vs. Clock Frequency

Dynamic ICC at VCC CDC(2)516 (typical )VCC= 3.60Volt, Bias= 0/3 Volt , Load= 30pF to GND

Average at 25 deg C

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.0E+00

2.0E+07

4.0E+07

6.0E+07

8.0E+07

1.0E+08

1.2E+08

1.4E+08

1.6E+08


ICC

[A]

CDC516

CDC2516

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