guidelines for choosing the right buck regulator control ... · guidelines for choosing the right...

Guidelines for Choosing the Right Buck Regulator Control Strategy

(Part B)

Brian Cheng Eric Lee

Brian Lynch Robert Taylor

2-2 Texas Instruments – 2014/15 Power Supply Design Seminar

How Do You Choose?

•  Part A –  Buck regulator basics –  Fixed frequency control

•  Part B –  Variable frequency control

•  Constant on-time •  Adaptive on-time

–  TI D-CAP™ families •  D-CAP2TM

•  D-CAP3TM

•  D-CAP+TM

–  Conclusions


Variable Frequency Control

Buck Converter

Constant On-‐Time Co

ntrol

VFB

VREF

VSW

TON

+

+

Comparator

VFB

RFBT

RFBBVREF

On-Time

GeneratorPower Stage

Reference

Voltage

Comparator

Output

Voltage

Divider

VOUT

Minimum

Off-Timer

One-Shot

On-Timer

+-

Texas Instruments – 2014/15 Power Supply Design Seminar 2-4

Constant On-Time Control – Basic Operation

•  Initiate fixed on-time when VFB<VREF

•  On-time can be fixed or changed by input voltage

VOUTVOUT

VIN

VDD

CT_ON

TON

VC

VC

VFBVREF

VSW

TON

Input Voltage (V)

Switc

hing

Fre

quen

cy (k

Hz)

1800

1600

1400

1200

1000

800

600

400

200

03 5 7 9 11 13 15 17 19

Constant On-Time

Adaptive On-Time


Adaptive On-Time Control – Frequency

•  Constant on-time has a fixed TON

•  Adaptive on-time adjusts the TON based on the input voltage

α


COT Control – Transient Performance

•  D-CAP™ mode: direct output capacitor voltage feedback

•  D-CAP™ mode does not have an error amplifier or compensation

4 A Load Step 100 µs/div

53 mV !!

VOUT

190 mV

VOUT

IOUT IOUT 4 A Load Step

100 µs/div

D-CAP™ Mode – Output Cap = 22 µFx3 Voltage Mode – Output Cap = 100 µFx4


COT Control – Seamless DCM/CCM

No Load à Varying Load à No Load •  The DCM/CCM transition is happening naturally without a mode change

VOUT

Switch Node

ILOAD


COT Control – High Efficiency @ Light Loads

TPS53219 + CSD86350 •  Efficiency FSW = 500 kHz, 12 V

to 1.1 V

–  > 80% from 0.2 A to 25 A

–  > 55% efficiency in Skip mode at 10 mA

Skip Mode

FCCM Mode

Load Current - A

- Ef

ficie

ncy

- %

0.01 0.1 1 10

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

+

-

+

-

+

-

+-

+-

VOUT

VOUT

VIN

Ref

Ref

Loop

Comparator

On-Time

Generator

Control

Logic &

Driver

Control

Logic &

Driver

PWM

Comparator

Error Amp


COT Control – External Components

D-CAP™ Mode

Voltage Mode

5 extra external components needed for compensation!

++–

S

QR

–Q

VOUT

RFBH

RFBL

VOUT

VREF

VOUT

RLOAD

RCO

LX

CO

VIN VIN

RampGenerator

One-ShotOn-Timer

ControlLogic&

Driver


TI D-CAP™ Control Architecture

•  Adaptive constant on-time

•  Ramp is generated to improve the jitter performance

TON =VOUTVIN

× K


COT Control – Ramp Compensation

•  Ramp compensation improves jitter performance by reducing the noise band •  Ramp compensation is built-in to most TI D-CAP controllers

No Ramp Compensation With Ramp Compensation

Noise Margin

T1 : Jitter Due to Noise

VFB

VREF

VSW

Noise Margin

T2 : Jitter Due to Noise

VFB

VREF+VRAMP

VSW


TI D-CAP™ – Ripple Requirements

Without Series Resistor RC With Sufficient RC

ΔVOUT = ΔIL × RCo +ΔIL

8 × fSW × CO = VESR +VC

Feedback signal going down when it should be going up!!


TI D-CAP™ – Stability Measurement

•  Conven<onal open-‐loop Bode plot measurement is not applied to COT control architecture since output is directly fed back to PWM modulator

•  Closed-‐loop frequency measurement used to indicate stability issue

•  Due to inherent load feed-‐forward capability, bandwidth measured from small-‐signal analyses will not indicate large-‐signal load transient performance


TI D-CAP2™ Control Architecture

•  Adaptive constant on-time

•  Ripple injection is added to D-CAP2™

•  This allows stability with low output ripple and ceramic output capacitors

TON =VOUTVIN

× K

++–

+–

S

QR

–Q

VOUT VSW

RFBH

RFBL

VOUT

VREF

VOUT

RLOAD

RCORC2

RC1LX

CO

CC1

CC2

VIN VIN

VSW

One-ShotOn-Timer

ControlLogic&

Driver

G

CSP

CSN

VFB

CCM

DCM

CSP

CSP

CSN

CSN

CSP

CSN

VFB

VREF

+

+

-

-


TI D-CAP2™ – Output Accuracy in DCM/CCM

•  Under CCM:

•  Under deep DCM:

•  Offset is not constant in CCM and DCM

VFB

−VREF

≅VRAMP

2

VFB

≅ VREF

VRAMP

2


TI D-CAP2™ – Duty Cycle Dependency

12 V to 0.6 V 12 V to 5 V

•  Fixed RC1CC1 time constant = 30 µs for both outputs

•  Transient performance is very different with different duty cycles

VOUT

Switch Node

IOUT

VOUT

Switch Node

IOUT


TI D-CAP3™ Control Architecture

•  All of the benefits of D-CAP2™

•  Adaptive ripple algorithm changes RC1CC1 time constant with VIN, VOUT and IOUT

•  Sample and hold circuit improves DC accuracy

++–

+–

S

QR

–Q

VOUT VSW

RFBH

VOUT

VREF

VOUT

RLOAD

RCORC2

RC1 LX

CO

CC1

CC2

VIN VIN

One-ShotOn-Timer

ControlLogic

&Driver

G

Adaptive RippleTuning Algorithm

Adaptive RippleGenerator

DC AccuracyImprovement

with S&H

S&H


TI D-CAP3™ – VOUT Accuracy

•  DC accuracy is improved in CCM operation

D-CAP2™

DCM: VFB ≈ Vref CCM: VFB > Vref

Half Effective Ramp Amplitude VFB Vref

DCM: VFB ≈ Vref CCM: VFB ~ VREF

VFB Vref

D-CAP3™ (With Sample-and-Hold Circuits)


TI D-CAP3™ – Adaptive Ripple Injection

•  Time constant for D-CAP2™ = 30 µs

•  Time constant for D-CAP3™ = 120 µs

•  Adaptive ripple algorithm changes RC time constant with VIN, VOUT and IOUT

D-CAP2™ 12 V to 5 V

VOUT

Switch Node

IOUT

VOUT

Switch Node

IOUT

D-CAP3™ 12 V to 5V (With Adaptive Ripple)

CH1 – Brown, 200 mV/Div CH2 – Blue, 10 V/Div CH4 – Green, 5 A/Div

VOUT

ILOAD COUT

VIN L

L

L

CIN

PHASE 1

PHASE 2

PHASE 3

Phase 1 – Switch Node




Multiphase DC-DC Converter – Introduction

•  Set of parallel converters

•  Each power-stage is known as a phase

•  The phases operate equally spaced through the period


Multiphase DC-DC Converter – Output Ripple

IL1

IL2

ISUM

PH1

PH2

Example – Two-Phase System

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Duty Ratio

Normalized Output Current Ripple 1

0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1

0

Reduced output ripple current Lower output capacitance to maintain same voltage ripple

→


Multiphase DC-DC Converter – Input Ripple

Reduced switch current Distributed power loss and better thermal performance

→

IL1

IL2

IHSSW1

IHSSW2

IAVGPH1

IAVGPH2

Lower input RMS current Smaller capacitance, lower ESR power loss, reduced self heating

→

Normal Operating Mode Normal Operating Mode

60 amp

24 amp

15 amp

6 amp


Multiphase DC-DC Converter – Load Transients

•  During load insertion, all the phases (N) are turned on –  If L is the inductor of each phase, effective inductance is L/N –  Ability to deliver current to the output capacitor is N times higher than single-phase

Improved transient with pulse overlap Lower output capacitance →


Multiphase DC-DC Converter – High Efficiency

High Efficiency Over Wide Load Range

•  Dynamic phase management is integral to achieve high-efficiency over wide loading conditions

–  Higher load current, more phases

–  As load current is reduced, there is a trade-off between switching and conduction losses — dropping phases can optimize the efficiency

–  At extreme light load, the power supply transitions to single-phase discontinuous conduction mode (DCM)

1-ph DCM 1-ph CCM 2-ph 3-ph

Load [A]

R Q

S Q

+

+Gn

+

+G1

... گ+

+...

SW CLK

PWM1

PWM2

PWM3

ISUM

EA

CSP1

CSN1

CSPn

CSNn

CSP1 CSN1

CSPn CSNn

ISNS1

ISUM

ISNSn

EA

One-Shot

ON-Timer

Phase

Management

Control

Logic

&

Driver

Control

Logic

&

Driver

VOUT

VREF

RCOMP RLOAD

RCSn

RCS1

CO

VFB

VIN

VOUT

VIN

VIN

LX1

LXn


TI D-CAP+™ Control Architecture

LOAD

Vcore

LOAD

Vcore

Isum

DROOP

Isum

DROOP

SW_CLK

Phase 1

Phase 2

Phase 3

SW_CLK

Phase 1

Phase 2

Phase 3


TI D-CAP+™ – Illustrated Transient Waveforms

•  Pseudo constant switching frequency at steady state without internal clocks

•  Variable switching frequency during load transients

•  Dynamic current sharing during load transients

Load Step-Up Load Step-Down


TI D-CAP+™ – Dynamic Phase Shedding

Phase Adding Phase Shedding

Iload (10 A/div)

•  Phase adding/shedding is determined based on the instantaneous ISUM

•  Consists of both current and time hysteresis for phase shedding

SW1 (10 V/div)

SW2 (10 V/div)

SW3 (10 V/div)


TI D-CAP+™ – Loop Gains with Different Phases

Loop Gain is Insensi4ve to the Number of Phases

-‐40

-‐20

0

20

40

60

80

1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06

1Ph, LL @ 10A

2Ph, LL @ 10A

4Ph, LL @ 10A

Frequency (Hz)

Gain (dB)

12Vin to 1.7Vout @ 600kHz, 10A, 150mV Ramp, Comp: 12kΩ/1.2nF/33pFLoop Gain Bode Plots

0

20

40

60

80

100

120

140

160

180

1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06

1Ph, LL @ 10A

2Ph, LL @ 10A

4Ph, LL @ 10A

Frequency (Hz)

Phase (degree)

12Vin to 1.7Vout @ 600kHz, 10A, 150mV Ramp, Comp: 12kΩ/1.2nF/33pFLoop Gain Bode Plots

TPS53640 with 12 VIN to 1.7 VOUT @ 600 kHz, 10 A load and 1 mΩ loadline


TI D-CAP+™ – High Efficiency

TPS53661 + CSD95372B with 12 VIN to 1.8 VOUT @ 600 kHz, 150 nH

82.0%

83.0%

84.0%

85.0%

86.0%

87.0%

88.0%

89.0%

90.0%

91.0%

92.0%

93.0%

94.0%

95.0%

96.0%

0 50 100 150 200

Eff

icie

nc

y (

%)

Output Current (A)

5-phase

4-phase2-phase

1-phase CCM

1-phase DCM


TI D-CAP+™ – Fast Phase Adding

120 nH @ 500 kHz with 2x470 µF/4.5 mΩ + 8x22 µF/DIMM

LF RR @ 1 kHz, 50% duty cycle (@ sensing point) 14.2 A-59.5 A @ 11.3 A/µs

20 mV/div

5 V/div

5 V/div 4 µs/div 200 µs/div

20 mV/div

5 V/div

5 V/div


TI D-CAP+™ – Dynamic Current Sharing

•  Currents are amplified, filtered and compared with average current

•  At each on-time, the on-time reference (DAC) is “tweaked” by a voltage equivalent to K x (IIN - IAVG)

•  Since filtering is light (5 µs), system response is < 25 µs

•  Current sharing loop analysis paper is available on request

+

+

+

+

+

VBAT

VDAC

IAVG

RT_on

CT_on

K x (I1-IAVG) PWM1

VBAT

VDAC

IAVG

IAVG

RT_on

CT_on

K x (I2-IAVG) PWM2CCSP2

CCSN2 Amp

VBAT

VDAC

IAVG

RT_on

CT_on

K x (I3-IAVG) PWM3CCSP3

CCSN3 Amp

AveragingCircuit

+CCSP1

CCSN1 5 µsFilter

5 µsFilter

5 µsFilter

Amp


TI D-CAP+™ – Dynamic Current Sharing

(1 A to 100 A @ 600 A/us) (100 A to 1 A @ 600 A/us)

(1 A to 100 A @ 600 A/µs and Load Frequency = Switching Frequency)

2 µs/div

2 µs/div 2 µs/div

2 µs/div

iL1 iL2 iL3 iL4

10 A/div

iL1 iL2 iL3 iL4 10 A/div

iL1 iL2 iL4 10 A/div

iLoad 50 A/div

iL1 iL2 iL4 10 A/div

iLoad 50 A/div


Comparisons of TI D-CAP™ Families

Control Architecture Features

D-CAPTM •  Adaptive on-time control •  Fast load transient response •  Ramp compensation built-in •  High efficiency @ light loads

D-CAP2TM •  Internal ripple compensation for MLCCs

D-CAP3TM •  Sample-and-hold for DC accuracy improvement for CCM/DCM

•  Adaptive ripple compensation D-CAP+TM •  With actual current feedbacks

•  Extension to multi-phase applications •  Dynamic current sharing •  Dynamic phase shedding


COT Control – Advantages and Challenges

Advantages Disadvantages

Simple design, no compensation required

Variable switching frequency (Solution: D-CAP/D-CAP2/D-CAP3/D-CAP+)

Excellent load transient response

Sensitive to PCB design for jitter (Solution: D-CAP/D-CAP2/D-CAP3/D-CAP+)

Excellent line transient response Minimum ripple requirement or output capacitor type limitations (Solution: D-CAP2/D-CAP3/D-CAP+)

Seamless DCM/CCM transitions for good light-load efficiency

Poor load/line regulation (Solution: D-CAP3/D-CAP+) Not easy for multi-phase configurations (Solution: D-CAP+)


Design Example #3 COT Control – Design Specifications

Design Specifications

Input voltage range 5 V to 18 V

Target output voltage 1.2 V

Output current range 0 A to 6.6 A

Switching frequency 500 kHz

Controller TPS53515 PG

OO

D

PGOOD

Thermal Pad

RF

VO

TRIPPGND

PGND

PGND

PGND

PGND

DNC

GND1

GND2

O

FB

GN

D

MO

DE

VR

EG

VREG

VD

D

NC

VIN

VIN

VIN

VIN

VOUT

EN

EN

VB

ST

N/C

SW

SW

SW

SW

TPS53515

1 2 3 4 5 6 7 8 9

23 22 21 20 19 18 17 16 15

10

11

12

13

14

28

27

26

25

24

1.3

1.25

1.2

1.15

1.10 2 4 6 8 10 12

Output Current (A)

0 2 4 6 8 10 12Output Current (A)

V OU

T (V)

100

90

80

70

60

Effic

ienc

y (%

)

VIN = 5 VVIN = 12 VVIN = 18 V

fSW = 500 kHzVDD = 5 VVOUT = 1.2 VTA = 25° CLOUT = 1 µHMode = Auto-skip


Design Example #3 COT Control – Performance Graph

Efficiency

SW (5 V/div)

VOUT (10 mV/div)

SW (6 V/div)

VOUT (50 mV/div)

ILoad (6 A/div)

Transient Response

Switching Operation

Load Regulation

1 µs/div

100 µs/div


Design Example #4 D-CAP+ Design Specifications

Design Specifications Input voltage range 12 V

Target output voltage 1.6 V-1.9 V

Output current range 0 A to 189 A

Switching frequency 600 kHz

Controller TPS53641

Load

VCORE_OUTPWM1

CSP1

VSP

VSN

PWM2

CSP2

PWM3

CSP3

PWM4

CSP4SDIO

SCLKALERT#To/From

CPU

I2C orPMBus

(Optional)

SLEW-MODE

ENABLE

VR_RDYVR_HOT#

VR_FAULT#

ENABLE

GND

VR_FAULT#

SKIP#-RAMP

V3R3

V1212V

V5

3.3V

PMB_DIO

PMB_CLKPMB_ALERT#

COMP

VREF

B-TMAX

O-USR

ADDR

TSEN

IMONIMON

F-IMAX

ISUM

OCP-I

12V

PS

VIN BOOT BOOT_R

VDD

ENABLE AGND

PGND

VSWPWM

FCCM

5V

IMON REFIN

TAO

12V

PS

VIN BOOT BOOT_R

VDD

ENABLE AGND

PGND

VSWPWM

FCCM

5V

IMON REFIN

TAO

12V

PS

VIN BOOT BOOT_R

VDD

ENABLE AGND

PGND

VSWPWM

FCCM

5V

IMON REFIN

TAO

12V

PS

VIN BOOT BOOT_R

VDD

ENABLE AGND

PGND

VSWPWM

FCCM

5V

IMON REFIN

TAO

5V

TPS5

3641


Design Example #4 D-CAP+ Performance Graph

Loadline Regulation @ 25C and 105C

12 V to 1.8 V with 4-phase operations @ 600 kHz, 150 nH, and 1 mΩ loadline

PWM1 (2 V/div)

PWM2 (2 V/div)

PWM3 (2 V/div)

PWM4 (2 V/div)

Phase Interleaving and Jitter @ 90 A

1.55

1.6

1.65

1.7

1.75

1.8

1.85

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200

VO

UT (

V)

IOUT (A)

Load Line @ 25C

Load Line @ 105C

Upper Limit

Lower Limit

1 µs/div


Design Example #4 D-CAP+ Performance Graph (2)

High-Frequency Transient Response (31 A to 189 A load @ 600 kHz)

PWM1 (2 V/div)

VOUT (50 mV/div)

PWM2 (2 V/div)

PWM3 (2 V/div)

PWM2 (2 V/div)

VOUT (50 mV/div)

CSO (2 V/div)

ALERT# (2 V/div)

12 V to 1.8 V with 4-phase operations @ 600 kHz, 150 nH, and 1 mΩ loadline

Dynamic Voltage Change (1.6 V to 1.82 V @ 5 A)

1 µs/div 20 µs/div


Voltage Mode C

ontrol

Buck Converter

Current Mode Control

Cons

tant

On-

Tim

e Co

ntro

l

Now I know!!

2-41

References

Texas Instruments – 2014/15 Power Supply Design Seminar

•  SEM 1500 - Under the Hood of Low Voltage DC/DC Converters

•  SLVA301 - Loop Stability Analysis of Voltage Mode Buck Regulator with Different Output Capacitor Types – Continuous and Discontinuous Modes

•  Easy Calculation Yields Load Transient Response

–  http://powerelectronics.com/site-files/powerelectronics.com/files/archive/powerelectronics.com/ar/502pet23.pdf

•  Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs

–  http://www.ti.com/lit/an/snva166a/snva166a.pdf

•  Buck Regulator Topologies for Wide Input/Output Voltage Differentials

–  http://www.ti.com/lit/an/snva594/snva594.pdf

•  Switching Power Supply Topology Voltage Mode vs. Current Mode

–  http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=slua119

•  Modeling, Analysis and Compensation of the Current-Mode Converter

–  http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=SLUA101&fileType=pdf

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