group meeting july 21, 2009
DESCRIPTION
Group Meeting July 21, 2009. Justin Burkhart. Presentation Outline. More Exact Analysis of Class E Resonant Boost Converter Gate Drive Options Transistor Layout Optimization. Boost Converter Operation. Switch is opened and closed periodically - PowerPoint PPT PresentationTRANSCRIPT
Massachusetts Institute of TechnologyLaboratory for Electromagnetic and Electronic Systems
Group Meeting July 21, 2009
Justin Burkhart
Presentation Outline
More Exact Analysis of Class E Resonant Boost Converter
Gate Drive Options
Transistor Layout Optimization
Boost Converter Operation
Switch is opened and closed periodically The rectifier LC tank is assumed to have high Q such
that the current in L2 is purely sinusoidal
L1 and C1 are tuned such that when the switch is opened, the voltage across the switch will ring back to zero half of a period later
Delivery of Power
Inverter(lossless)
Rectifier(lossless)+
-+-
Vin Vout
Pin Pinv Pout
Pin = Pinv = Pout
Delivery of Power
Inverter(lossless)
Rectifier(lossless)+
-+-
Iin-dc+I1sin(wt)+I2sin(2wt)+…
Vin Vout
Pin Pinv Pout
Pin = Pinv = Pout
Pin=VinIin-dc
Delivery of Power
Inverter(lossless)
Rectifier(lossless)+
-+-
Iin-dc+I1sin(wt)+I2sin(2wt)+… Iout-dc+Io1sin(wt)+Io2sin(2wt)+…
Vin Vout
Pin Pinv Pout
Pin = Pinv = Pout
Pin=VinIin-dc Pout=VoutIout-dc
Delivery of Power
Inverter(lossless)
Rectifier(lossless)+
-+-
Iin-dc+I1sin(wt)+I2sin(2wt)+… Iinv-dc+I1-invsin(wt)
Vin Vout
Pin Pinv Pout
Pin = Pinv = Pout
Pin=VinIin-dc Pout=VoutIout-dcPinv=PAC+PDC
Iout-dc+Io1sin(wt)+Io2sin(2wt)+…
Inverter: Detailed Analysis
Unknowns: wo, zo, IAC, o1, IL(0)
Constraints: <IL(t)> = Pout/Vin, <VC(t)> = VIN, <VC’(Ts/2)> = 0, 0.5 VC-Fund IAC cos(o-o1) = Pout(1-Vin/Vout)
Known Initial Conditions: Vc(0)=0
wo,zo
0 10 20 30 40 50-0.5
0
0.5
1
1.5
Time (ns)
Cur
rent
(A) io(t)
I
0 10 20 30 40 50
0
20
40
Time (ns)
Vol
tage
(Vol
ts) V(t)
Vo(t)
Inverter: Detailed Analysis
Unknowns: wo, zo, IAC, o1, IL(0)
Constraints: <IL(t)> = Pout/Vin, <VC(t)> = VIN, <VC’(Ts/2)> = 0, 0.5 VC-Fund IAC cos(o-o1) = Pout(1-Vin/Vout)
Known Initial Conditions: Vc(0)=0
0 10 20 30 40 50-0.5
0
0.5
1
1.5
Time (ns)
Cur
rent
(A) io(t)
I
0 10 20 30 40 50
0
20
40
Time (ns)
Vol
tage
(Vol
ts) V(t)
Vo(t)
Solve system of non-linear equations for each value of wo
wo,zo
Rectifier: Detailed Analysis
0 10 20 30 40-20
0
20
40
Time (ns)
Vol
tage
(Vol
ts)
VAC+VDC
0 10 20 30 40-50
0
50
Time (ns)
Vol
tage
(Vol
ts)
Vdiode(t)
0 10 20 30 40-2
0
2
4
Time (ns)
Cur
rent
(Am
ps)
Io(t)
Unknowns: wr, zr, ton, toff
Constraints: <VD(t)> = VIN, <IL(t)> = POUT/VOUT, IAC and o1 are constrained by the inverter
Known Initial Conditions: VD(toff) = VOUT, IL(toff) = 0
Rectifier: Detailed Analysis
0 10 20 30 40-20
0
20
40
Time (ns)
Vol
tage
(Vol
ts)
VAC+VDC
0 10 20 30 40-50
0
50
Time (ns)
Vol
tage
(Vol
ts)
Vdiode(t)
0 10 20 30 40-2
0
2
4
Time (ns)
Cur
rent
(Am
ps)
Io(t)
Unknowns: wr, zr, ton, toff
Constraints: <VD(t)> = VIN, <IL(t)> = POUT/VOUT, IAC and o1 are constrained by the inverter
Known Initial Conditions: VD(toff) = VOUT, IL(toff) = 0Solve system of non-linear equations
Gate Drive Options
Hard Switched Gate DriveLoss arises from charging and discharging CISS
through a resistor every cycle. Thus, loss is proportional to switching frequency. Since the converter is operating at 75 MHz this loss can be substantial, however, this scheme has very low complexity.
Resonant Gate DriveAn inductor can be added in series with the gate to form a resonant circuit with CISS. This essentially charges and discharges CISS with a sinusoidal current. Loss occurs in RISS.
Introduction to TI’s LBC5 Process
Removed
LDMOS Layout
Removed
LDMOS Layout Optimization
Large LDMOS transistors are formed by connecting many smaller transistors in parallel
Optimization serves to find the total device size, finger size, finger layout, and metal layout that achieves the highest converter efficiency
Loss Model:
Scaling of Parasitics
Removed
Optimization Procedure
Sweep total device width Sweep number of fingers
Calculate loss
Choose total device width and number of fingers
Find best aspect ratio and top metal layer layout
Solid Lines: Ross set by scaling measured dataDashed Lines: Ross set as 3 Rds
Optimization Result (Hard Switched)
Optimization Result (Hard Switched)Solid Lines: Ross set by scaling measured dataDashed Lines: Ross set as 3 Rds
Choose 45000um and 100 Fingers
Optimization Result (Resonant Gating)Solid Lines: Hard SwitchedDashed Lines: Resonant Gating
Choose Aspect Ratio
Total Area Available: 1500x1000 um Finger Cross Section: 13.8 um Finger Width: 245 um
# of Rows Total Length (um) Total Width (um)
1 1380 245
2 690 490
3 460 735
4 345 980
Choose Aspect Ratio
Total Area Available: 1500x1000 um Finger Cross Section: 13.8 um Finger Width: 245 um
# of Rows Total Length (um) Total Width (um)
1 1380 245
2 690 490
3 460 735
4 345 9803 rows is chosen
Top Metal Design
Top Metal Design Metal 1
Gate
Top Metal Design Metal 1 Metal 2
Sour
ce
Top Metal Design Metal 1D
rain
Metal 2
Top Metal Design Metal 1 Metal 2
Sour
ce
Dra
in
Taper Angle Optimization
Adjust the size of the network based on the number of fingers per row and solve for equivalent resistance using MATLAB
NodeMatrix
VoltageVector
ConstantVector
Taper Angle Optimization
0 10 20 30 40 50 60300
350
400
450
500
550
600
650
700
750
800
Taper Angle (degree)
On
Res
ista
nce
(mO
hm)
On-State Resistance vs. Geometry
100 Fingers/Row50 Fingers/Row33 Fingers/Row25 Fingers/Rows10 Fingers/RowMinimum Possible
Optimization ignores metal resistance in connecting rows
Device Layout
Ideas for Improvement?Break long rows into multiple columns
Ideas for Improvement?
Gate
Metal 1 Metal 2
Ideas for Improvement? Metal 1 Metal 2
Ideas for Improvement? Metal 1 Metal 2
Source