good morning. technology that is driving the world vlsi and asic design very large scale integrated...
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GOOD MORNING
TECHNOLOGY THAT IS DRIVING THE WORLD
VLSI AND ASIC DESIGN
• VERY LARGE SCALE INTEGRATED
CIRCUIT AND
APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN © R.Lamsal
DEVELOPMENT IN INTEGRATED CIRCUIT TECHNOLOGY
SMALL SCALE INTEGRATIONSSI
MEDIUM SCALE INTEGRATIONMSI
LARGE SCALE INTEGRATIONLSI
VERY LARGE SCALE INTEGRATIONVLSI
ULTRA VLSI
< 10 TRANSISTORS
10 TO 100 TRANSISTORS
100 TO 1,000 TRANSISTORS
MORE THAN 1000 TO MILLION OF TRANSISTORS
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VLSI DESIGN CYCLE
Design specification
HDL CAPTURE
RTL SIMULATION
NETLIST GENERATION
IMPLEMENTATIONIN FPGA
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PLACEMENT,ROUTINGPOSTLAYOUT
SIMULATION,MASKINGPACKAGING
VLSI DESIGN DOMAINS
Behavioral
Structural
Physical
1
2
3
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PROCESSORS
DATA PATH; ALU,REGISTERS
TRANSISTOR
ALGORITHM
RTL (HDL)
LOGIC
TRANSISTOR
CELL.
CHIP,MODULE
BOARD,SYSTEM
Introduction to HDL
Hardware descriptive languages are used purely to describe the digital circuits in various level of abstraction ranging from gate to board
and system level.
HDL differs from conventional HLL in the sense they make use of concurrency however
sequential option is also provided.
HDL incorporates timing feature to represent real hardware.
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AND GATE
Some delay occursTo pass the input
Signal at the output
A
B
C
C<=A AND B after propagation delay;
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Transistor representation of And gate
• Delay occurs due to RC effect of the transistor.
A B
CVDD
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Acts as a capacitor
Placement TYPE1
Cell A
Cell C
Cell B
Cell D
Cell E
Cell F
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PLACEMENT TYPE2
Cell A
Cell C
Cell B
Cell D
Cell F
Cell E
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ROUTING
Cell A
Cell C
Cell B
Cell D
Cell F
Cell E
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Nmos transistor
sourcegate
Drain
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FABRICATION OF NMOS TRANSISTOR
BASE SILICON
SIO2 ADDED AT THE TOP
PHOTOMASKING AND UV RAYS
Polysilicon and diffusionTo create base source and drain region
Metaliziation
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IMPORTANT PARAMETERS TO BE CONSIDERED WHILE DESIGINING THE CHIP.
• 1. POWER
• 2.SPEED
• 3.AREA© R.Lamsal
EXAMPLE
• FULL ADDER
FULL ADDER
A
B
CIN
CARRYOUT
SUM
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TRUTH TABLE
A B CIN SUM CARRYOUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Sum<= A XOR B XOR CIN ;
Carry<= (A AND B) OR ( A AND CIN) OR (B AND CIN) ;
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VHDL DESCRIPTION• library IEEE;• use IEEE.STD_LOGIC_1164.ALL;• use IEEE.STD_LOGIC_ARITH.ALL;• use IEEE.STD_LOGIC_UNSIGNED.ALL;
• entity fulladder1 is• Port ( a : in std_logic;• b : in std_logic;• cin : in std_logic;• CARRYout : out std_logic;• SUM : out std_logic);• end fulladder1;
• architecture Behavioral of fulladder1 is
• begin• SUM<=a xor b xor cin;• CARRYOUT<=(a and b )or (a and cin) or (b and cin);• end Behavioral; © R.Lamsal
SIMULATION WAVE
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LIST TABLE
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RTL SCHEMETIC
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SYNTHESIS
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