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46 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 25, NO. 1, JANUARY 2007

Ge-on-SOI-Detector/Si-CMOS-AmplifierReceivers for High-Performance

Optical-Communication ApplicationsSteven J. Koester, Senior Member, IEEE, Clint L. Schow, Laurent Schares, Member, IEEE, Gabriel Dehlinger,

Jeremy D. Schaub, Member, IEEE, Fuad E. Doany, and Richard A. John

Abstract—In this paper, an overview and assessment of high-performance receivers based upon Ge-on-silicon-on-insulator(Ge-on-SOI) photodiodes and Si CMOS amplifier ICs is provided.Receivers utilizing Ge-on-SOI lateral p-i-n photodiodes pairedwith high-gain CMOS amplifiers are shown to operate at 15 Gb/swith a sensitivity of −7.4 dBm (BER = 10−12) while utilizinga single supply voltage of only 2.4 V. The 5-Gb/s sensitivity ofsimilar receivers is constant up to 93 C, and 10-Gb/s operation isdemonstrated at 85 C. Error-free (BER < 10−12) operation ofreceivers combining a Ge-on-SOI photodiode with a single-endedhigh-speed receiver front end is demonstrated at 19 Gb/s, using asupply voltage of 1.8 V. In addition, receivers utilizing Ge-on-SOIphotodiodes integrated with a low-power CMOS IC are shown tooperate at 10 Gb/s using a single 1.1-V supply while consumingonly 11 mW of power. A perspective on the future technologicalcapabilities and applications of Ge-detector/Si-CMOS receivers isalso provided.

Index Terms—CMOS, germanium, optical receivers, photo-detectors.

I. INTRODUCTION

A LL-SILICON-BASED optical receivers have long beenconsidered an attractive alternative to III–V-technology

for low-cost-communication applications [1]. However, III–Vcomponents still dominate high-performance optical communi-cations due to their superior optical and electronic properties.This trend has been reversing somewhat of late, and CMOScomponents are receiving a second look for high-performance-receiver applications. The reason is twofold. First, the electricalperformance of Si CMOS has dramatically improved in recentyears due to the benefits of scaling [2]. For instance, MOSFETswith simultaneous fT and fmax over 300 GHz have beendemonstrated recently [3], and an RF design infrastructure isnow firmly established for CMOS technology. Second, SiGehas emerged as a mainstream Si-compatible technology [4],

Manuscript received July 14, 2006; revised November 20, 2006. This workwas supported in part by the Defense Advanced Research Projects Agencyunder Contract MDA972-03-3-0004.

S. J. Koester, C. L. Schow, L. Schares, F. E. Doany, and R. A. John are withthe IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA(e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]).

G. Dehlinger was with the IBM T. J. Watson Research Center, YorktownHeights, NY 10598 USA. He is now with Infineon Technologies, 9500 Villach,Austria (e-mail: [email protected]).

J. D. Schaub is with the IBM Austin Research Laboratory, Austin, TX 78758USA (e-mail: [email protected]).

Digital Object Identifier 10.1109/JLT.2006.888923

suggesting that the improved absorption properties of SiGe[5] and Ge [6] can be exploited for use in high-performancedetectors. These facts, combined with the cost advantages of Si-based technology compared with III–Vs, suggest that CMOS-based high-performance optical receivers could have a dramaticimpact on the wide-spread adoption of optical solutions forapplications such as local-area networks [7], and could help todisplace electrical links for short-distance high-speed networkcomputing [8]. Additionally, CMOS-compatible integrated re-ceivers are likely to be critical for the realization of future interand intrachip optical communications [9].

In this paper, we provide an overview of our resultson optical receivers that combine Ge-on-silicon-on-insulator(Ge-on-SOI) infrared detectors with CMOS IC amplifier cir-cuits. We review the state-of-the-art Ge-detector research inSection II, specifically describing the advantages of our Ge-on-SOI detector approach, and also provide an overview ofhigh-speed CMOS receiver circuits. In Section III, we describeour Ge-on-SOI detector/Si CMOS receiver results. We showthat these receivers can operate at 15 Gb/s with sensitivity of−7.4 dBm at a bit-error rate (BER) of 10−12, while utilizinga single supply voltage of only 2.4 V. We also demonstratedifferent configurations of these receivers that can operate at bitrates as high as 19 Gb/s, as well at 10-Gb/s using a single 1.1-Vsupply while consuming only 11 mW of power. In Section IV,we provide our perspective on the future technological ca-pabilities and applications of Ge-detector/Si-CMOS receivers,including the performance benefits that can be expected throughdevice and process optimization, the prospects and challengesfor monolithic integration, and the most promising applicationspace where this technology is likely to be realized. Finally,Section V summarizes our results.

II. BACKGROUND

A. Ge Detectors

Extensive reviews of Ge- and SiGe-detector research havebeen provided elsewhere [10], [11] and, therefore, only a briefoverview of the current status of high-speed near-infrared (NIR)Ge-detector technology is provided in this section. Althoughvarious SiGe- and Ge-detector geometries have been investi-gated in the literature [12]–[20], the basic detector design thathas emerged as the most promising is a p-i-n detector utilizinga Ge absorbing layer on top of a Si or SOI substrate [16]–[20].

0733-8724/$25.00 © 2007 IEEE

KOESTER et al.: Ge-on-SOI-DETECTOR/Si-CMOS-AMPLIFIER RECEIVERS 47

In such a detector structure, the Ge is usually grown epitaxiallyon the Si (or SOI) substrate, either directly or using a thin(< 0.5 µm) SiGe buffer layer. Ge has emerged as the preferredabsorbing layer due to the fact that it has an extremely shortabsorption length (∼300 nm) at λ = 850 nm, which is a valueroughly 50 times shorter than that of Si at the same wavelength.Ge is also advantageous because it absorbs at the technologi-cally important 1300- and 1550-nm wavelengths, where Si istransparent. The use of direct growth or thin buffer layers helpsthe detectors achieve high speed by minimizing the absorption-layer thickness and is also likely to be beneficial for integrationwith CMOS. Despite the > 4% lattice mismatch between Siand Ge, it has been found that reasonable defect densities(∼107−108 cm−2) can still be achieved in directly grown andthin buffer structures, particularly if the layers are subjectedto postgrowth annealing or grown in limited areas [21]. Thesedefect-density values are believed to be sufficiently low forhigh-speed-receiver applications, although more studies of theeffect of defects on reliability and yield are still needed.

For Ge photodiodes fabricated on bulk Si substrates, bothlateral and vertical p-i-n structures have been investigated inthe literature. Huang et al. [16] reported vertical p-i-n photo-diodes utilizing Ge on thin SiGe buffers with external quantumefficiency η of 61% and −3-dB bandwidth of 8.1 GHz usingbackside illumination at λ = 1300 nm. More recently, verticalp-i-n photodiodes using Ge layers grown directly on bulk Sihave produced bandwidths of 39 GHz, with η = 16% at λ =1298 nm [17]. High bandwidth (8.5 GHz) and high responsivity(0.56 A/W) have also been achieved at a wavelength of 1550 nmby Liu et al. [18] who showed that tensile strain in the Ge layercan help improve absorption at longer wavelengths. The maindrawback of Ge detectors grown on bulk Si, however, is theirperformance at shorter wavelengths, particularly λ = 850 nm.At this wavelength, parasitic absorption in the bulk Si can causea low-frequency “tail” that severely limits the bandwidth [19].In addition, if high-temperature annealing is utilized to decreasethe defect density, Si up-diffusion into the Ge can dilute theGe with Si, significantly decreasing the absorption coefficient,particularly at long wavelengths. This problem has the effect ofplacing a lower limit on the absorption-layer thickness, therebylimiting the ultimate bandwidth-efficiency product that can beachieved in these devices.

For the reasons outlined above, we have developed aGe-on-SOI-detector design that overcomes the absorptionproblem in Si at λ = 850 nm and also provides a path to ahigher bandwidth-efficiency product compared to Ge-on-bulkSi designs [20]. Our approach could also improve absorptionat longer wavelengths [11] and may allow easier integrationof novel detector geometries such as waveguide structures foroperation at λ = 1550 nm and higher. A schematic diagram ofour photodiode device design is shown in Fig. 1. The devicestructure consists of lateral alternating implanted p+ and n+

surface electrodes on an epitaxially grown Ge absorbing layeron top of an ultrathin SOI substrate. As in our previous work[20], the detectors have a combined Ge and SOI layer thicknessof roughly 400 nm, while the buried oxide layer is 145 nm thick.The width of the implanted fingers is 300 nm, and the fingers arestrapped with 180-nm-thick, 200-nm-wide Ti/Al metal fingers

Fig. 1. Schematic diagram of Ge-on-SOI photodetector structure (not drawnto scale).

that are nominally centered within the doped contact regions.Under normal-incidence-illumination conditions, discrete de-vices with this geometry have produced −3-dB bandwidths ashigh as 29 GHz and a maximum bandwidth-efficiency productof 13.2 GHz [20]. These devices also have excellent low-biasperformance, as we have shown that detectors with finger spac-ings S ≤ 0.8 µm have bandwidths > 20 GHz at bias voltages≤ 1 V [20]. Due to the low-voltage operational capabilities,acceptably low dark currents of ∼10 nA can still be obtained for10 × 10 µm2 detectors, which is a value independent of fingerspacing, down to S = 0.3 µm. Most importantly, we haveshown that Ge-on-SOI p-i-n photodiodes are able to simulta-neously achieve the high-speed, high-responsivity, low-voltage,and low-dark-current operation needed for high-performance-communication applications [11]. A summary of the simul-taneous performance results for our Ge-on-SOI detectors isprovided in Table I. As shown in the table, detectors with 10 ×10 µm2 area and S = 0.6 µm have produced a −3-dB band-width of 27 GHz, η = 46% (33%) at λ = 895 nm (850 nm),and dark current of 24 nA, all at a bias voltage of only −1 V.Similar performance metrics have been achieved for detectorswith S = 0.4 µm at −0.5-V bias.

B. CMOS Receivers

Despite the demonstrated high-speed capabilities of SiCMOS, high-performance CMOS-based optical receivers haveonly recently been realized [22]–[30]. These demonstrationsinclude CMOS transimpedance-amplifier (TIA) circuits withbandwidths in excess of 20 GHz [22], [23], although thoseresults have come at the expense of low transimpedance gain.In only a few of these reports have the ICs been paired witha photodiode and optical sensitivities reported. Of these re-ports, the best performance has been achieved using CMOSamplifier circuits hybridly integrated with III–V photodetectors.Chen et al. [24] demonstrated a fully integrated 10-Gb/soptical-receiver analog front–end that included a TIA and alimiting amplifier (LA) with measured sensitivity of −12 dBm(BER = 10−12) using a 1.8-V supply. The best reportedsensitivity of a CMOS-amplifier-based optical receiver is−13.1 dBm at 10 Gb/s for BER = 10−12 [25]. For CMOS cir-cuits monolithically integrated with Si detectors, however, the


TABLE ISIMULTANEOUS PERFORMANCE METRICS FOR Ge-on-SOI LATERAL p-i-n PHOTODIODES

overall receiver performance typically decreases dramatically[26]–[29] due to the bandwidth limitations of Si photodiodes.Significant improvement in the monolithic receiver sensitivityhas been achieved recently by Swoboda and Zimmerman [30],who demonstrated error-free operation of monolithically inte-grated receivers in a 25-GHz-fT Si BiCMOS technology at11 Gb/s, but these circuits required photodiode bias voltagesof 17 V as well as circuit-equalization techniques to overcomethe limited bandwidth of the silicon detector.

III. OPTICAL RECEIVER RESULTS

A. Experiment

The integrated receiver measurements were performed us-ing lateral p-i-n Ge-on-SOI photodiodes with the same layerstructure and device design as aforementioned and in [20].The active detector area was 10 × 10 µm2, and the deviceswere contacted using wire bonds to 50 × 50 µm2 bond pads.For the receiver measurements, devices with either S = 0.7or 0.8 µm were chosen. All devices were passivated usinga roughly 150-nm-thick polymethyl methacrylate (PMMA)antireflection-coating (ARC) layer. The responsivity of photo-diodes with S = 0.7 µm at λ = 850 nm was measured to be0.35 A/W, corresponding to an external quantum efficiency ηof 52%. The increased responsivity compared to the data inTable I is a direct result of the polymer ARC layer that wasnot present in the previous devices. A dark current of 10 nA at−2 V was measured for the 0.7-µm finger-spacing devices atroom temperature.

The CMOS-amplifier circuits were fabricated using theIBM CMOS8RF-LM technology, a standard eight-metal-layer0.13-µm bulk CMOS process. The n-MOSFET fT of thistechnology is in the range of 100–120 GHz. Three differentamplifier ICs have been paired with the Ge-on-SOI detectorsto form the receiver assemblies that were characterized. TheseICs are as follows: 1) a high-gain differential receiver designedfor 10–20-Gb/s operation that utilizes 1.8–2.2-V power suppliesand provides a 500-mVpp digital differential output; 2) a single-ended high-speed receiver front–end (RFE) consisting of a TIAwith a 50-Ω output driver stage; and 3) a low-power 10-Gb/sdifferential receiver that operates with 1.0–1.2-V supplies. In allthree cases, the photodiodes were connected to the ICs throughshort bond wires. An example of the connection scheme for thehigh-gain receiver is shown in Fig. 2.

A block diagram of the experimental setup used to mea-sure receiver eye diagrams and sensitivity curves is shown inFig. 3. The optical source used for all of the time-domaincharacterization of the receiver assemblies was an 850-nm

Fig. 2. Optical micrograph showing a Ge-on-SOI photodiode wire-bonded toa high-gain CMOS IC. High-magnification optical and SEM micrographs ofthe photodiode are also shown.

Fig. 3. Block diagram of experimental setup for receiver eye-diagram andsensitivity measurements. An eye diagram of the 850-nm VCSEL sourcemodulated at 15 Gb/s is also shown.

vertical-cavity surface-emitting laser (VCSEL) modulated witha 27 − 1 pseudo random bit sequence (PRBS) data pattern at anextinction ratio of 4.3–4.8 dB. The light from the VCSEL wascoupled into a cleaved 50-µm multimode fiber that was routedthrough a variable optical attenuator and focused onto thephotodiode using a two-lens optical system. Power and controlvoltages for the ICs were applied through either dc-needleprobes or bond wires, and the high-speed receiver outputs werecontacted using coplanar ground-signal-signal-ground (single-ended RFE) or ground-signal-ground (high-gain and low-powerreceivers) microwave probes. For the receivers with differentialoutputs (high gain and low power), one output was routed toa high-speed sampling oscilloscope, while the other output wasconnected to the input of an error detector for simultaneous eye-diagram and sensitivity measurements.


Fig. 4. Block diagram and circuit schematics of high-gain receiver.

B. High-Gain Receivers

In this section, we describe the receiver performance of aGe-on-SOI photodetector packaged with a high-gain multistageCMOS-amplifier IC. A portion of these results have beenpreviously reported in [31]. The receiver block diagram andcircuit schematics are shown in Fig. 4. The TIA utilizes adifferential modified common-gate circuit with an architecturesimilar to that reported in [25]. The TIA front–end utilizes apair of multimetal-level interdigitated capacitors to ac-couplethe photodiode to the TIA. The purpose of these capacitorsis to isolate the input stage from the dc bias of the photodi-ode, which is applied through bias resistors integrated in theTIA. Additionally, to maximize its bandwidth, the TIA designutilizes serial inductive peaking applied at the input and loadends. The output of the TIA is fed next into five differentialCherry–Hooper gain stages that comprise the LA. An activeoffset-cancellation feedback loop is incorporated to cancel anyoffsets due to device mismatches in the amplifier chain. Finally,an output-buffer stage has been designed to drive the (off-chip)50-Ω load of the high-speed test equipment. The output ofthe receiver IC is digital over its entire dynamic range, with adifferential amplitude of 280 mVpp (500 mVpp) when poweredwith a 1.8-V (2.2-V) supply. The IC has an active core areaof 250 × 250 µm2, while the total area of the receiver IC,including the probe/wirebond pads, is 560 × 700 µm2.

As described in [31], the measured transimpedance gain ofthe receiver using a 2.2-V supply is 91 dB · Ω, with a −3-dBbandwidth of 6.6 GHz. At a reduced supply voltage of1.8 V, the gain and bandwidth are reduced to 87 dB · Ω and5.7 GHz, respectively. The receiver has been designed for oper-ation with the 8-b/10-b code used for data communications, andthe 30-MHz low-frequency cutoff of the receiver is compatiblewith this data format. It should be noted that the bond padsrequired for the wirebond connection between the photodiode

Fig. 5. Eye diagram at 15 Gb/s of high-gain receiver biased using a 2.4-Vsupply voltage.

and IC contribute ∼200 fF of capacitance at the receiver input,significantly reducing the bandwidth of the receiver. This valueis much larger than the intrinsic capacitance of the photodiode(< 30 fF) [11], suggesting that a monolithically integrateddesign would greatly improve the bandwidth by eliminating theparasitic bond capacitances while also enabling the active areaof the detector to be enlarged.

A 15-Gb/s eye diagram of the high-gain receiver assemblyis shown in Fig. 5. The measured receiver sensitivity curvesat data rates of 10, 12.5, 14, and 15 Gb/s are shown in Fig. 6[31]. At a data rate of 12.5 Gb/s and BER of 10−12, the receiverexhibits sensitivities of −11.0 and −10.4 dBm for supplyvoltages of 2.0 and 1.8 V, respectively. The respective powerconsumptions at these supply voltages are 66 and 50 mW.When powered with a 2.4-V supply, the sensitivity of thereceiver is −9.6 dBm at 14 Gb/s and −7.4 dBm at 15 Gb/s.Finally, at 10 Gb/s, the receiver has a sensitivity of −13.1 dBmfor a 1.8-V supply and operates at a BER < 10−12 with apower consumption of only 30 mW. The power consumptionof the receiver ranges from 3 to 7 mW/Gb/s over the sup-ply voltages (1.5–2.4 V) and bit rates (10–15 Gb/s) coveredin the sensitivity measurements. The bandwidth and sensitiv-ity of the high-gain receiver are relatively insensitive to the


Fig. 6. Plot of BER versus sensitivity for high-gain receiver at 10, 12.5, 14,and 15 Gb/s, using supply voltages of 1.8, 2.0, 2.4, and 2.4 V, respectively.

Fig. 7. Sensitivity reduction (relative to 2 V) versus photodiode bias for high-gain receiver at 10 and 12.5 Gb/s.

photodiode bias. Fig. 7 plots the sensitivity reduction of thereceiver as the photodiode bias is reduced from its nominalvalue of 2 V. At 10 Gb/s, the sensitivity is constant (withinmeasurement error) over the photodiode bias range of 0.5–2 V,while at 12.5 Gb/s, the sensitivity is degraded by less than0.5 dB when the bias is decreased from 2 to 1.0 V. The abilityof the Ge photodiode to retain its performance characteristics atbias voltages in the 0.5–1-V range is an extremely attractive at-tribute, indicating that monolithically integrated receivers couldbe fabricated in advanced CMOS processes where operationwith a single 1-V power supply is needed.

Due to concern over potentially excessive dark current atincreased operating temperatures for receivers utilizing Gephotodetectors, the temperature-dependent properties of thehigh-gain receivers have also been characterized. For theseexperiments, a 10-×10-µm2 Ge-on-SOI photodetector withS = 0.8 µm was wire bonded to the receiver. This detector hasa responsivity of 0.35 A/W at λ = 850 nm, and a dark currentof 30 nA at 25 C. In order to measure the receiver performanceversus temperature, the receiver subsystem was mounted on adual-stage Peltier thermoelectric heater. The temperature wasmonitored using a thermistor (10 kΩ at 25 C) placed next tothe photodetector, and this setup allowed measurements to beperformed within the temperature range of 5 C–93 C.

The results of the receiver-sensitivity measurements areshown in Fig. 8 for different temperatures. At room temper-ature, the receiver has a sensitivity of −13.1 dBm at 10 Gb/s,and the error-free operation is maintained when the temperatureis increased to 85 C. The 1.4-dB shift in sensitivity at 85 Ccompared to room temperature is attributed to decreased gain

Fig. 8. Plot of BER versus sensitivity (relative to 25 C) for high-gain receiverat 10 Gb/s at various temperatures. Inset: BER versus relative sensitivity for thesame receiver at 5 Gb/s and temperatures of 25 C and 93 C.

Fig. 9. Plot of dark current versus bias for a 10 × 10 µm2 Ge-on-SOIphotodetector with finger spacing S of 1.1 µm at temperatures of 24 Cand 86 C.

and bandwidth in the CMOS IC, which was designed foroperation at 50 C. The sensitivity is nearly independent of thephotodiode bias voltages between 1.0 and 2.5 V at 85 C. At5 Gb/s, the receiver performance is not limited by the gain andbandwidth of the IC. Consequently, as shown in the inset ofFig. 8, no change in sensitivity is observed up to temperaturesexceeding 90 C.

In addition to the receiver characterization, separate mea-surements of the dark current of individual photodiodes as afunction of temperature have also been performed. For thesemeasurements, detectors with S = 1.1 µm were wirebonded toa TO5 header and loaded into a closed-cycle 4He-cryostat sys-tem. The I–V characteristics of the devices were then measuredunder vacuum, utilizing a thick-metal vacuum can to ensuregood light isolation throughout the entire measurement. Fig. 9shows the bias dependence of the dark current measured at24 C and 86 C. Over this temperature range, the dark currentat a detector-bias voltage of −2 V is found to increase byroughly an order of magnitude from 21 to 192 nA. Becauseour receiver is still dominated by the thermal noise of CMOSIC, this increase in the dark current does not affect the receiversensitivity. We have recently shown [32] that the dark current isstrongly influenced by trap-assisted generation and recombina-tion. Consequently, improvement in the material quality shouldlead to further reduction of the dark current.


Fig. 10. Circuit diagram of high-speed receiver assembly consisting of aGe-on-SOI photodiode and a high-speed-receiver-transimpedance amplifier.

Fig. 11. Eye diagram of high-speed receiver at 19 Gb/s.

C. High-Speed RFE

In order to assess the ultimate limit of the operating bit rateof the 0.13-µm receiver circuits combined with Ge detectors,an RFE has been assembled consisting of the fastest TIA thatwe have produced in this CMOS technology paired with aGe-on-SOI photodiode. The TIA used in this assembly is a dc-coupled single-ended modified common-gate circuit that hasa bandwidth of 15.4 GHz and a transimpedance of 37 dB · Ω[33]. Fig. 10 shows the circuit schematics of the RFE circuit.The TIA is an inductorless design that occupies an area ofonly 70 × 60 µm2. A buffer consisting of a source–followerfollowed by a common-source stage with inductive load peak-ing is also included in the test circuit to provide broadbanddriving capability for the off-chip 50-Ω load presented by testequipment. The total area of the IC, including probe pads, is400 × 700 µm2.

The RFE attains the highest sensitivity and bandwidth forsupply voltages of 1.8 V for the TIA and 2.4 V for the buffer,and these settings have been used for all measurements. Underthese conditions, the power dissipation of the TIA is 7 mW,and the buffer consumes 24 mW. The dc-coupled TIA designrequires a photodiode supply voltage of 3 V to properly biasboth the detector and the input stage of the amplifier. However,the effective bias across the photodiode, the difference betweenthe 3-V supply, and the 1.2-V bias-point of the TIA input isonly 1.8 V.

A clearly open eye diagram at 19 Gb/s is presented in Fig. 11.The smaller opening (e.g., compared to Fig. 5) of the 19-Gb/sRFE eye diagram is due to bandwidth limitations of both theVCSEL source and the receiver. The −3-dB bandwidth ofthe RFE is measured to be 7 GHz. Similar to the high-gain

Fig. 12. BER versus sensitivity plot for high-speed receiver at data rates of10, 15, 18, and 19 Gb/s.

receiver, the bandwidth is adversely affected by the parasiticcapacitance of the wire-bond pads. The measured-receiver-sensitivity curves are shown in Fig. 12. At a BER of 10−12,the RFE exhibits sensitivities of −14.0, −12.9, and −10.3 dBmat bit rates of 10, 15, and 19 Gb/s, respectively. The powerconsumption of the TIA (without the output buffer included inthe test circuit) at 19 Gb/s is 0.37 mW/Gb/s.

D. Low-Power Receivers

Due to the low-voltage capabilities of the Ge-on-SOI pho-todiodes, we have assessed the performance of a third receiverassembly to illustrate the potential of this technology to enablefuture low-voltage, low-power receivers. For these measure-ments, a receiver utilizing a Ge-on-SOI detector with S =0.7 µm and low-power CMOS amplifier IC has been charac-terized. The CMOS IC, which has been described previouslyin [25], includes a low-noise TIA front–end, a five-stage LA,and a source–follower 50-Ω driver stage. A circuit schematic ofthe low-power receiver is shown in Fig. 13. As indicated in thefigure, the low-power design utilizes the same TIA architectureas in the high-gain receiver and high-speed RFE. However,the LA is quite different from the design used in the high-gain receiver. In order to operate with a nominal 1-V powersupply, the Cherry–Hooper architecture used in the high-gaincircuit has been eliminated, and each of the five stages ofthe LA consist of a differential pair with an active inductorload. The active inductor load is formed by the load transistorwith its gate connected through a resistor to a separate supplyVind. The voltage that is applied to Vind is typically 1.5–1.7 V,further reducing the headroom requirements of the LA stages.Additionally, since effectively no current is supplied by Vind,this voltage source could easily be generated on-chip usingvoltage-doubling or charge-pump circuits. The source–followeroutput stage following the LA provides a broadband 50-Ωdriving capability but contributes a substantial amount of loss(15.5 dB) and may not be required for future monolithicallyintegrated devices where the output of the receiver would be di-rectly connected to digital circuitry. The receiver-core circuitryoccupies an area of 175 × 150 µm2, and the total chip area,including probe pads, is 560 × 700 µm2.


Fig. 13. Block diagram and circuit schematics of low-power receiver.

Fig. 14. Eye diagram at 10 Gb/s of low-power receiver biased with a 1.1-Vsupply.

The low-power capabilities of the receiver have beencharacterized by operating the circuit at supply voltages of1.0–1.3 V. It has been found that a 1.1-V supply voltage anda Vind value of 1.6 V yield a reasonable tradeoff betweenpower consumption and sensitivity. These supply voltagesresult in a total receiver power consumption of 11 mW andwere used for all of the data presented in this paper. Consistentwith single-power-supply operation, the Ge photodiode wasalso biased with a 1.1-V supply. Under these conditions, thetransimpedance of the receiver was measured to be 70 dB · Ω,with a bandwidth of 3 GHz. An eye-diagram produced by thelow-power receiver assembly at a bit rate of 10 Gb/s is shown inFig. 14, and the results of sensitivity measurements at bit ratesfrom 5 to 10 Gb/s are shown in Fig. 15. The receiver attainedsensitivities of −9.8, −12.6, and −14.2 dBm at data rates of 10,7.5, and 5 Gb/s, respectively. The appreciable difference in thesensitivity measured at 10 Gb/s compared to 7.5 Gb/s indicatesthat the intersymbol interference (ISI) penalty due to the limitedreceiver bandwidth becomes significant at the higher data rate.For 10-Gb/s operation, the receiver consumes 1.1 mW/Gb/s

Fig. 15. BER versus sensitivity for low-power receiver utilizing a single 1.1-Vsupply at data rates of 5, 7.5, and 10 Gb/s.

from a 1.1-V supply, representing both the lowest power con-sumption and lowest voltage single-supply operation for anysilicon-based receiver at gigabits-per-second bit rates to date.

E. Summary of Receiver Results

A summary of the results for the three receiver configurationsdescribed above are listed in Table II. A few points are worthnoting. First of all, the high-gain receiver clearly provides thehighest sensitivity at 10 Gb/s with a power consumption ofonly 5 mW/Gb/s. Additionally, the high-gain receiver providesthe most complete light-to-logic function by providing largedigital-output amplitudes over its entire dynamic range. Thelow-power receiver also provides complete receiver function-ality but with less gain and a reduced output swing in orderto further reduce power consumption to 1.1 mW/Gb/s. Finally,the high-speed receiver has the lowest power consumption,but it is unfair to compare it against the full receivers sinceits simple architecture (TIA + output driver) provides low


TABLE IIPERFORMANCE METRICS FOR PHOTORECEIVERS UTILIZING Ge-on-SOI PHOTODIODES PAIRED WITH THREE DIFFERENT CMOS-AMPLIFIER ICS

OPTIMIZED FOR HIGH-SENSITIVITY, LOW-VOLTAGE, OR HIGH-SPEED OPERATION

Fig. 16. Sensitivity versus data-rate results for the receivers described in thispaper compared with results reported in the literature [27], [30]. All sensitivityvalues are for average optical power P and quoted at BER = 10−9.

transimpedance gain and, thus, would need a significant amountof post amplification to produce a reasonable output-signalamplitude. Rather, the high-speed TIA was included in thegroup to illustrate the potential of the CMOS circuits and Gedetectors to attain high operating speed at low-power-supplyvoltages (1.8 V). For all of the receivers to achieve theirhighest sensitivity and greatest power efficiency, it is criticalfor the detector to provide as much responsivity as possible tomaximize the signal-to-noise ratio at the TIA input as well asto relieve the gain requirements on the CMOS circuitry. Forinstance, if the detector responsivity could be increased by afactor of two to the ideal value of 0.69 A/W at λ = 850 nm,the sensitivity of the receivers would be improved by 3 dB andthe gain could be lowered by a corresponding factor of two toreduce power consumption while maintaining the same output-signal amplitudes as the current receivers.

Fig. 16 provides a summary of the measured sensitivities ofour three receivers as a function of bit rate and, for reference,also includes the sensitivities of two recent all-silicon receiverscapable of ∼10-Gb/s operation [27], [30]. Although we havequoted the receiver sensitivity throughout this paper at a BERof 10−12 (the standard for modern data communications), inFig. 16, all of the sensitivities are quoted at a BER of 10−9

to maintain consistency with the values reported in [27] and[30]. As Fig. 16 illustrates, the receivers in this paper not onlyachieve operation at the highest bit rates but also exhibit thehighest sensitivity at 10 Gb/s. Additionally, our receivers com-pare favorably in terms of power dissipation (1.1–5 mW/Gb/s)to the highest speed monolithically integrated devices that havebeen reported (28 mW/Gb/s) [30]. In summary, the results of

this section provide a starting point for the assessment of Ge-detector/Si CMOS receiver technology for various applicationspaces and constitute a basis for potential optimizations thatmay be needed to meet practical performance specifications.In the next section, we will describe the most promising appli-cations and outline how the technology can be optimized bothfrom a device and integration standpoint.

IV. OUTLOOK

This section provides an overview of the potential appli-cations that could be enabled by the Ge-detector/Si-CMOS-receiver-technology platform and the device improvements thatwould be needed to meet the particular application specifica-tions. We then present an overview of some of the integrationissues that will need to be addressed in order to realize theenvisioned monolithically integrated receiver technology.

A. Applications and Device Optimization

Cost-sensitive high-performance datacomm systems areamong the most important initial applications likely to developfor monolithically integrated Ge-detector/CMOS-IC receivers,due to the expected cost reduction compared to III–Vs. Forinstance, a silicon-based integrated-receiver technology couldhelp to accelerate the deployment of fiber links in enterprise andcampus environments and could displace short-distance high-speed electrical links for network computing.

From a performance point of view, for Ge-based receiversto be successful in short-reach data communications, theymust be able to achieve the performance and reliability of-fered by receivers using III–V photodetectors while, at thesame time, comply with the sensitivity and other specificationsof the various datacomm standards. The bulk of datacommoptical transceivers are currently used in short-reach applica-tions, which typically operate at λ = 850 nm. The 10-Gb/sEthernet [34] and Infiniband [35] standards require receiversto have an optical-modulation-amplitude (OMA) sensitivity of−11.1 dBm at BER = 10−12 for their 850-nm versions. Ourcurrent high-gain receiver has an average power (P ) sensitivityof −13.1 dBm at 10 Gb/s, a value that corresponds to an OMAsensitivity of −10.1 dBm. Therefore, the sensitivity of ourcurrent receivers would need to be improved by a minimumof 1 dB to meet the aforementioned standards. Other datacommunications standards such as Fibre Channel [36] may alsobenefit from low-cost Ge-detector/CMOS-amplifier receivers.The 8x version of Fibre Channel (8.5 Gb/s) is currently beingstandardized, and the physical-interface specifications are in


line with those of the aforementioned standards. The nextgeneration of Fibre Channel (16x) has a signaling speed of17 Gb/s and links operating at these data rates using multimodefiber at distances of up to 200 m have been demonstrated[37]. Therefore, no barriers appear to utilizing Ge-detector/CMOS-IC receivers for such links. Since the quantum effi-ciency of our devices is still only approximately half of theideal value, the 1-dB deficit mentioned above could be madeup by using photodiodes with an optimized-layer-structuredesign to improve the responsivity [11]. For instance, weanticipate that, without increasing the Ge-layer thickness, adevice with S = 0.8 µm and optimized ARC and buried-SiO2-layer thickness should have a responsivity of 0.5 A/W. For10-Gb/s applications, even greater responsivity improvementscould be achieved, since the bandwidth of our current detectorsis much higher than needed at this data rate, and therefore, theabsorption-region thickness could be increased at the expenseof bandwidth while still achieving the same overall receiverspeed.

It should be noted that unless new coupling optics are used,the 10-×−10-µm2 active area is too small for the multimodefiber links typically encountered at λ = 850 nm. A larger detec-tor area usually comes at the expense of increased capacitanceand, thus, reduced bandwidth. However, monolithic integrationshould allow such larger detectors to be implemented withoutsacrificing performance, since elimination of the bonding-padparasitic capacitances would enable larger detector area whilekeeping the total capacitance constant. Reductions in the in-trinsic device capacitance (through n- and p-implant processoptimization) and series resistance (by using thicker metal-strapping layers) should also be possible [11], and the resultingRC-delay reduction should improve the bandwidth especiallyin large-area devices.

An integrated-low-power-receiver technology is also ex-pected to have an impact on future parallel interchip [38] andintrachip optical interconnects [39], where cost, power, anddensity considerations are paramount. A particularly attractivefeature of the Ge detectors is the fact that they can operate atreverse voltages of only 1 V or less. This means that Ge-basedreceivers may be operated from a single supply in future low-voltage-CMOS technologies. The reduced power consumptionof low-voltage ICs constitutes an additional benefit for largeparallel optical interconnects, in which low-heat-dissipation-per-unit area will be required in order to allow high-densityarrays. A critical factor for optical interconnects in high-performance computing systems is the receiver sensitivity atdata rates that could be on the order of 20 Gb/s, with BERsthat may need to be significantly lower than the BER = 10−12

specified in data communications. In typical onboard parallelchip-to-chip links like those studied in the Terabus program[38], with lengths on the order of 10–100 cm, the powerbudgets have receiver sensitivities on the order of OMA ≈ -12 –-13 dBm in order to overcome coupling/transmission lossesand crosstalk. It is thus important that Ge detectors with highbandwidth-efficiency numbers can be integrated with low-noisehigh-speed receiver circuitry. To this end, moving to a moreadvanced CMOS technology (90 or 65 nm) would be desirable.Advanced CMOS technologies would greatly improve the noise

performance of the CMOS-amplifier circuitry [40], potentiallyextending the capabilities of these devices to serial data rates of40 Gb/s or even higher.

For both interchip and intrachip optical interconnects, itwould be advantageous to operate at wavelengths > 1.1 µm toenable silicon-waveguide structures to be utilized and also toallow through-wafer illumination. Ge is ideally suited for thisapplication, due to its sensitivity at wavelengths up to ∼1.6 µm.For instance, at λ = 1300 nm, our simulations [11] show thatusing an optimized-layer structure, the bandwidth-efficiencyproduct of normal-incidence Ge-on-SOI detectors should onlybe a factor of two smaller than detectors optimized for 850-nmoperation. This leads to the result that detectors with S =0.8 µm should be able to achieve responsivities of 0.45 A/Wusing only a slightly increased Ge-absorbing-layer thickness of450 nm. However, for applications at λ = 1550 nm, not takinginto account strain effects, the bandwidth-efficiency product atnormal incidence is over an order of magnitude smaller than forthe 850-nm operation. Therefore, a waveguide geometry maybe preferable, since this configuration can overcome the inher-ent bandwidth-responsivity limitations of normal-incidence de-tectors. Recently, high-performance waveguide detectors havebeen demonstrated with bandwidths as high as 35 GHz [41].The waveguide-detector structure is also compatible with otherSi/SiO2 optical devices such as modulators and optical switchesand could be a key component to realizing fully integrated on-chip optical-interconnect networks [42].

The broad absorption spectrum of Ge in the NIR is alsoattractive for various applications based on fast imaging orNIR spectroscopy. Standard low-cost silicon detectors, likep-i-n photodiodes or charge-coupled devices, cannot be usedin the NIR, since Si detectors are insensitive at wavelengthsabove 1.1 µm. Currently, InGaAs photodiodes grown on InPsubstrates are mostly used to detect light in the NIR (up to1.7 µm). These III–V detectors offer many of the characteristicsrequired for fast-imaging applications—high responsivity, largebandwidth, and low dark current—but widespread monolithicintegration into standard Si processes has proven elusive todate. Integrated Ge detectors with CMOS circuitry would of-fer a near-ideal solution for fast NIR imaging, and mono-lithic 64-element detector arrays with readout electronics havebeen recently demonstrated in a commercial 0.7-µm CMOStechnology [43]. Possible applications of integrated Ge-basedreceivers may be found in high-resolution and inexpensiveNIR imaging and sensing, as well as in various other fieldssuch as medical equipment, security and ranging, or test andmeasurement.

B. Issues for Monolithic Integration

Although it appears promising that, with some device op-timization, Ge detectors paired with CMOS ICs can meet theperformance specifications needed for the applications outlinedabove, the integration issues associated with creating a trulymonolithic technology are far from settled. In this section, wedetail the main problems that will need to be addressed inorder to integrate Ge-on-SOI detectors with CMOS and thendescribe some of the specific issues associated with optimizing


this integrated technology for applications at λ = 850, 1300,and 1550 nm.

Perhaps the primary challenge to monolithically integratingGe detectors with Si CMOS is the thermal budget of the Geepitaxy and postgrowth annealing. On one hand, it is useful toanneal the Ge at temperatures as high as possible (≥ 900 C)to minimize the density of dislocations in the Ge absorptionlayer [20]. On the other hand, this anneal could degrade theCMOS-device performance, if the Ge detectors are integratedafter the formation of the CMOS. Therefore, the develop-ment of lower temperature Ge deposition and postannealingprocesses that still provide acceptable Ge dislocation densitieswill be critical for the successful implementation of a mono-lithic technology.

Despite the fact that our current receivers have been demon-strated using bulk CMOS ICs for monolithic integration withthe Ge-on-SOI photodiodes, it would be preferable to utilize anSOI-CMOS technology. Fortunately, SOI CMOS has becomea very standard technology for CMOS manufacturing, andtherefore, no major problems are envisioned transitioning thereceiver design from a bulk to SOI-CMOS platform. However,for very cost-sensitive applications, the receiver technologywould ideally utilize a photodiode integrated with bulk CMOS.Therefore, approaches for integrating Ge-on-SOI photodetec-tors on bulk Si substrates may be needed. Several promisingtechniques to this end have been demonstrated in the literature,including lateral Ge overgrowth [44], local SIMOX formation[45], and germanium-on-insulator formation using an epitaxi-ally grown buried oxide [46].

The application targeted for the receivers will be critical foroptimizing the integrated technology, since the wavelength ofoperation could dramatically affect the detector design. Inte-gration of the Ge-on-SOI photodiode optimized for operationat 850 nm appears to be the most straightforward for severalreasons. First of all, due to the extremely short absorptionlength at 850 nm, Ge absorption layers of only 200–400 nm willbe needed to achieve the necessary performance. These thick-nesses are only about two times the CMOS-polysilicon-gateheight, and it is therefore conceivable that the CMOS metalliza-tion layers could be utilized for making electrical contact to theGe photodetector. However, the impact of the nonplanarity ofthe detector with the CMOS on deep-UV lithography still needsto be assessed. An additional advantage of detectors designedfor 850-nm-wavelength operation is that the optimal buried-oxide-layer thickness for maximum responsivity is 140–150nm, which is a thickness range similar to the standard buried-oxide thicknesses utilized for high-performance SOI CMOS.

For normal-incidence detectors operating at 1300 nm, inte-gration with CMOS could be more challenging due to the in-creased height of the Ge absorbing layer needed for acceptableresponsivity. In order to achieve similar quantum efficiencies asaforementioned for λ = 850 nm, an absorption-layer thicknessof 400–800 nm would be needed, making it more difficult toutilize standard planar processing to contact the detector. Anadditional inconvenience at this wavelength is that the optimumburied-oxide thickness is on the order of 200 nm, althoughthis somewhat nonstandard thickness value is not expected toappreciably affect the CMOS performance.

Due to the nonplanarity issues associated with integratingnormal-incidence detectors, for applications both at λ = 1300and 1550 nm, a waveguide geometry might be preferable. Sucha geometry is beneficial for integration, because the absorption-layer thickness in a waveguide detector would only need tobe a few hundred nanometers, which is on the same order asthe Ge thickness in the 850-nm normal-incidence detectors.Also because of the small lateral dimensions of the waveguide,this detector geometry may lend itself better to the implemen-tation of novel defect-reduction techniques such as selective-area epitaxy. The main performance problems of waveguidedetectors are associated with fiber-coupling losses. Whereasnormal-incidence detectors can reasonably be expected to haveexternal quantum efficiencies of 80% or higher, coupling lossesmay limit the waveguide devices to much lower ultimate effi-ciency values. For both applications, however, fiber couplingand alignment will be an important issue to determine the mostappropriate detector geometry and integration scheme.

V. CONCLUSION

In conclusion, we have performed a thorough assessmentof high-performance receivers based upon Ge-on-SOI photo-diodes and Si-CMOS-amplifier ICs. Receivers utilizing Ge-on-SOI lateral p-i-n photodiodes wire-bond integrated withhigh-gain CMOS amplifiers have been shown to operate error-free at 15 Gb/s with sensitivity of −7.4 dBm while utilizing asingle supply voltage of only 2.4 V. The operation is found tobe insensitive to temperature at 5 Gb/s, and error-free operationat 85 C and 10 Gb/s has been demonstrated. More impor-tantly, the receiver performance shows no detrimental effectsdue to the increased dark current. A Ge-on-SOI photodiodeintegrated with a single-ended high-speed RFE has also beendemonstrated and shown to operate error-free at a bit rate of19 Gb/s. Finally, receivers utilizing Ge-on-SOI photodiodesintegrated with a low-power CMOS IC have been shown tooperate error-free at 10 Gb/s, while utilizing a single 1.1-Vsupply and consuming only 11 mW of power. We have pro-vided a perspective on the future technological capabilities andapplications of Ge-detector/Si-CMOS receivers and describedthe device optimization and integration challenges that needto be addressed. In particular, receivers optimized for 850-nmapplications appear to have the most straightforward path toproduction, both from a performance and integration point ofview. The Ge-detector/Si-CMOS approach also has the poten-tial to be an enabling technology for future high-performanceinterchip and intrachip optical interconnects, as well as CMOS-based NIR-imaging systems.

ACKNOWLEDGMENT

The authors would like to thank P. Pepeljugoski andH. Ainspan for the useful discussions.

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Steven J. Koester (M’96–SM’02) was born in Defiance, OH, in 1966. Hereceived the B.S.E.E. and M.S.E.E. degrees from the University of Notre Dame,Notre Dame, IN, in 1989 and 1991, respectively.

He was a Research Fellow at the University of California, Santa Barbara.There, he performed research involving the fabrication of quantum devices inthe InAs/AlSb heterostructure system. After receiving the Ph.D. degree in 1995,he joined the IBM T. J. Watson Research Center, Yorktown Heights, NY, asa Postdoctoral Researcher working on the fabrication and characterization ofnanostructured devices in Si/SiGe strained-layer materials. Since 1997, he hasbeen performing research on Group-IV heterostructure materials and devices,with an emphasis on strained-layer field-effect transistors and photodetectors.He has authored or coauthored over 100 technical publications and conferencepresentations. He is also the holder of 15 U.S. patents.

Clint L. Schow, photograph and biography not available at the time ofpublication.

Laurent Schares (S’99–M’03) received the Diploma and Ph.D. degreesin physics from the Swiss Federal Institute of Technology (ETH), Zurich,Switzerland, in 1998 and 2004, respectively.

He is currently a Research Staff Member at the IBM T. J. Watson ResearchCenter, Yorktown Heights, NY, where he has been engaged in projects onchip-to-chip optical interconnects, high-speed optical receivers, and equalizedmultimode fiber links. He is the author or coauthor of more than 50 paperspublished in technical journals and conference proceedings.

Gabriel Dehlinger received the degree (Magna Cum Laude) from the Univer-sity of Tübingen, Tübingen, Germany, in 1997 and the Ph.D. degree from thesolid state group of Prof. Ensslin, Swiss Federal Institute of Technology, Zürich,Switzerland, in 2001. His thesis research was performed in the Laboratory ofMicro and Nanotechnology, Paul Scherrer Institute, Villigen, Switzerland, onthe subject of vertical transport and intersubband emission in SiGe resonanttunneling diodes and quantum cascade structures.

In 2001, he joined IBM T. J. Watson Research Center, Yorktown Heights,NY, working on direct epitaxial growth of Ge on Si and on the processing andmeasurement of Ge high-speed photodetectors. In 2003, he joined with InfineonTechnologies, Villach, Austria, where he is currently a Staff Engineer, workingon high-power bipolar-transistor-technology development.

Jeremy D. Schaub (S’93–M’00) received the B.S degree in engineeringscience from Trinity University, San Antonio, TX, in 1995 and the M.S. andPh.D. degrees in electrical and computer engineering from the University ofTexas at Austin, in 1998 and 2000, respectively.

He is currently a Research Staff Member with the IBM Austin ResearchLaboratory, where he has focused on computer interconnects and high-speedmeasurement of on-chip signals.

Fuad E. Doany received the Ph.D. degree in physical chemistry from theUniversity of Pennsylvania, Philadelphia, in 1984.

He was a Postdoctoral Fellow at the California Institute of Technology,Pasadena. He joined the IBM T. J. Watson Research Center, Yorktown Heights,NY, in 1985, as a Research Staff Member and worked on laser spectroscopy,applied optics, projection displays, and laser material processing for electronicpackaging. He is the author or coauthor of numerous technical papers andis the holder of over 40 U.S. patents. His current research interests includeoptoelectronic packaging and high-speed optical link and systems design.

Richard A. John, photograph and biography not available at the time ofpublication.

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