04/10/2023 | 1 Confidential | Copyright © Larsen & Toubro Infotech Ltd.

Design Challenges & Trengs in High Speed Interconnect

IPs

Ravi ThummarukudyL&T Infotech/GDASept 2010

04/10/2023 | 2

Agenda

Introduction and BackgroundRationale for High Speed Serial InterconnectsComparison of High Speed ConnectivityChallenges of IP adoptionSoftware IPUSB 3.0 OverviewAnswer any questions on the above topics

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Company Overview Manufact

uring –

Hi Tech Products

Insurance

Energy & Petroche

mical

Manufacturing –

Packaged Goods

Product Engineeri

ng Services

Banking &

Financial Services

Global provider of comprehensive, end-to-end

software & hardware services & solutions 15+ years of international experience

Presence : NA, APAC, Europe, Middle East, Africa

Company Strength: 11,000+; Revenue: US$ 432M

Amongst India’s Leading software companies

25 Fortune-100 customers

Wholly owned subsidiary of Larsen & Toubro Ltd.

7 decade history in India as a premier engineering company

Revenues: US$ 9.8 Billion Corporate Certifications Top 100

innovative service providers,

2009 - Global

Services

Industry Presence

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Product Engineering Services

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High Speed Interconnect Rationale

Space Space

REDUCTION REDUCTION

Power Power

REDUCTION REDUCTION

Cost Cost

REDUCTION REDUCTION

Performance Performance

INCREASE INCREASE

Integration & Bandwidth Process Nodes SiP

SOC

Connectivity Requirements

Chip Cost System Cost Pins Application Awareness

Multi-Core CPU-GPU Cabling

Power Awareness

PS >1Kwatt

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SOC versus SiP Tradeoffs

Processor Cores

Glue Logic

IP Core

s DFT Logi

c

Bus Architecture Memory

Embedded

Core Analog Circuitry

Communication & Interface

Peripherals

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PCI Express Interconnect

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MIPI IPs

Application

Processor SoC

RF

PA

Tx

Rx Tx

CSI -2

DSI -1

D-PHY

D-PHY

DSI -2

Co-Processor

SoC

Tx Displ

ay Rx

MPHY

DIG RF

Display Rx

Camera

Tx

Base Band

Processor SOC

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USB – Super Speed Interconnect

Source: USB IF

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High Speed Interconnects – Comparison

• PCIe 2.5 Gb/s – 8Gb/s• SRIO – Rev 1.3 supports 1.0Gbps; Rev 2.0 -

3.125Gbps, 5Gbps & 6.125Gbps• XAUI – 3.125Gbps – 6.125Gbps• USB 3.0 – 5Gbps• MULTI – PROTOCOL SERDES 1Gb/s – 10Gb/s –

PHY’s

13

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Memberships

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IP Channels

IP Vendor

ASIC/Design Service

Companies

Silicon Vendors OEM/ODMIP

IP Integration Services

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HW Interconnect IP Portfolio

Security IPs 3DES, AES,

MD5, RSA, SHA2, HDCP, BISS-E

Processor* IBM

Power PC 405 Power PC 460

Hyper Transport Cave Tunnel Host

Bridge Switch Port

USB3.0 Device Host Hub

Ethernet* 10/100/1G MAC

10G MAC HiGig

PCI Express* Endpoint

Root Complex Switch port/Switch

AMBA Bridge

SPI 4.2* Single channel Multi channel

DDR3/2 Controller Interlaken DP/HDMI

MIPI*

Rapid IO* Serial

Parallel AXI Bridge

GPON OLT MAC

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AM

BA

3 A

XI &

AM

BA

2.0

AH

BMemory

DDR3/2 CTRL

USB 2.0/3.0Host, Hub

Device

PCIe Gen1/2/3

Controller

SRIO

HDMI

Controller

MIPI/UNIPRO

Display Port Controller

Ethernet

HTARM Power PC

X86

MIPS DSP

LTE- UE

DLNA

DVB-H TRO69

IPMI

Software IP

HW IP

IP Portfolio

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INTERCONNECT APPLICATIONS

IP Computing Networking Storage Consumer Wireless Embedded

PCI Express √ √ √ √ √ √

Ethernet √ √ √ √ √ √

RapidIO √ √

HT √           MIPI √ √ √ √

HDMI √     √    

Display Port √        

USB √ √ √ √ √ √

DDR √ √ √ √   √

SPI 4.2   √        

GPON   √      

Security IPS √ √ √ √   √

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HW IP Reference Platforms

Market Leader in

Interconnect IP

Reference Platforms

USB 3.0 Platform 10-GbE Platform

PCIe Platform

DDR Memory Platform

MIPI Platform

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IP Adoption Challenges

0% 5% 10% 15% 20% 25% 30%

Vendor Relation

Reuse

Timing

Lack of Stds

Cost

Qualifying IP

Verification

Quality

Integration

Source: Gartner

Top 3 Issues

Percentage of Survey Respondents

04/10/2023 | 21 Confidential | Copyright © Larsen & Toubro Infotech Ltd. 21

04/10/2023 | 22 22

LTE UE Stack

Compliance to latest 3GPP

Release 8 Specification for

MAC, RLC, RRC, PDCP and

NAS Layer implementation

FDD Mode operation

PHY and OS agnostic

protocol stack

Protocol abstraction for

allowing inter-operability

with 3rd party applications

APIs for MAC-PHY interface

Commercial Grade UE stack compliant to 3GPP Rel.8 March’09 specs

04/10/2023 | 23 .

Broadcast Server

Broadcast

Network

Content

DVB-H

Users

L&T Infotech’s DVB-H Component fulfill core software functions as part of the DVB-H middleware

This components is completely modular in architecture and ANSI C compliant

Support for JSR 272 This component can be easily portable to various OS

oWindows Mobile, SymbianoCustomizable to be integrated with 3rd party components

Overview

FLUTE PSI/SI ESG Engine OS Abstraction Layer Receiver Abstraction Layer for tuner abstraction Integration Layers for XML, Media Player and Zip Application APIs OMA-BCAST and IPDC support IPv4 and IPv6 support

Features

DVB-H Client

04/10/2023 | 24 Confidential | Copyright © Larsen & Toubro Infotech Ltd. 24

TR-069 Component Technical Details

\

• Auto Configuration of CPE at initial connection• ACS initiated dynamic provisioning of CPE •Diagnostics information reporting from CPE and diagnostic

test •Web identity management for customizing web content •Configurable transport level security •Authentication with shared secrets and MD5 Digest •Platform independent – integration layers • APIs and Parameter Mapping for device specific

integration• Vendor specific parameter support• Data Models support - IGD, STB, VoIP, NAS, PON devices

• TR-069 CWMP v1.1 Amendment 2• TR-111 LAN device management• HTTP v1.1• SSL 3.0 / TLS 1.0 • SOAP v1.1 (Using GSOAP v2.7.10) • Linux kernel v2.6• Supported Data Models:

TR-098, TR-106 (IGD) TR-104, TR-110 (VoIP) TR-135 (STB) TR-140 (NAS) TR-142 (PON)

Features Technical Specification

Server ConfigurationManager

ATA

ACS

LAN HomeNetwork

STB

BRAS

ManagedRG

BroadbandNetwork

CPE WAN Management Protocol

ACS South InterfaceACS North Interface

MobileDevice

DSLAMMSANOLT

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USB 3.0 (Super Speed)

25

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USB 3.0 (Super Speed USB)

Increase the USB speed by 10X (5Gb/Sec)Backwards compatible to USB 2.0Almost 2X more power over cable Similar connector foot printNew power management featuresNewer transfer modes

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Need for Super Speed USB

Address the need for higher data rates for Disk drives, Flash Storage, Blu-ray , HD DVD etc

Newer applications demanding faster connectivity between PC and peripherals

HD Video applications in Net books, Portable Media Players, Mobile phones etc

Better energy efficiency overallStay ahead of competing technologiesUSB 3.0 effort was started in 2007 and the initial

deployment started in 2009; Technology is now ready for industry deployment.

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USB 3.0 expected Ramp

Source www.ptgrey.com

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USB 2.0 vs. USB 3.0

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• Integration of Design IP, VIP and SW Stack• Legacy Integration• Verification and Validation• Compliance and Interoperability• Performance, Latency• Low Power• Software Support

USB3.0 Design Challenges

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Pravega USB3 Device/Host Solution

USB3 & USB2

Device

xHCI Host

Dual Mode

Hub

32 & 64 DP*8/16/32 Bit PIPEPCS

PMA

PRX PTXPCTL

LRX LTXLCTL

Application Layer

Protocol Layer

Application Interface

Receive Control Transmit

Link

Layer

DMA/xHCIEP0

Processor

PBUS/APB Interface

ROM Interface

Speed Select

USB2.0Controller(Optional)

USB3 PIPE IF UTMI /ULPIIF

USB3 IF USB2 IF

USB2 PHY

Pravega SuperSpeed Core

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Pravega USB3 Hub Solution

Confidential © L&T Infotech / GDA Technologies, Inc.

PRX PTXPCTL

LRX LTXLCTL

Protocol Layer

Receive Control Transmit

Link

Layer

USB3 PIPE IF

Pravega SuperSpeed DP0

PRX PTXPCTL

LRX LTXLCTL

Protocol Layer

Receive Control Transmit

Link

Layer

USB3 PIPE IF

Pravega SuperSpeed DPN

LRX LTXLCTL

PRX PTXPCTL

Link

Layer

Receive Control Transmit

Protocol Layer

USB3 PIPE IF

Pravega SuperSpeed UP

Hub Core Matrix

PNPI PNPI

PNPI

Header Router EP0 Processor Header Aggregator

REGISTER

SET

USB3

Hub

32 & 64 DP*8/16/32 Bit PIPE

ROM Interface

PBUS Interface

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Overcoming Adoption Challenges from Vendor side• Highly configurable solution to adapt to customer design

• Provides huge options for Hardware and Software configurability

• Verified against 3rd Party VIPs

• Interoperated with USB3 PIPE Compliant PHYs

• Passes Protocol Compliance tests (USB3CV)

• In-House Validation platform for Device, Host and Hub functionality and Application Drivers

• Collaboration with MCCI for Compliant USB 3.0SW Stack

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Pravega Device Controller Validation Setup

USB3 Cable

Pravega

Device

Controller

Xilinx

FPGA

USB3 STD B

Connector

ONFI MSC

CTLR

GDA IPVP Board

(Pravega Device Controller)

USB3 STD A

Connector

USBCV Test Suite

USBIF Host (NEC/Fresco)

Board

04/10/2023 | 35

GDA USB Validation Platform

Xilinx Virtex5-xcv110T-2 FPGA or xcv200T-2

One USB3 STD A Host Receptacle

One USB3 STD B Device Receptacle

USB PIPE Connector On board micron ONFI

Flash One PCIe Edge

Connector One PCIe Slot

Connector

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Pravega Device Controller Validation Setup

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Summary

• Integrating high speed interconnect is a design necessity to increase performance, Reliability while reducing cost

• There are many challenges in IP adoption and careful planning and verification is the key

• Configurability , Compliance and inter operability are key requirements in selecting the right IP

• Questions?