FSSR2 Capacitive Noise Measurement and Analysis

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The goal of this measurement is to determine the capacitive noise affecting the FSSR2s ADC thresholds.

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<p>FSSR2 Capacitive Noise Measurement and AnalysisL. Vitale, A. Srebrni c 13th Feb, 2012Abstract The goal of this measurement is to determine the capacitive noise aecting the FSSR2s ADC thresholds.</p> <p>Contents1 Introduction 1.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Measurements 2.1 Initial checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . 3 Data analysis 3.1 Encountered problems . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3 3 4 4 4 6</p> <p>1</p> <p>Figure 1: The FSSR2 module with the lid open.</p> <p>11.1</p> <p>IntroductionEquipment</p> <p>The FSSR2 is a self-triggered low noise readout chip for silicon detectors. It services 128 channels and provides address, time and magnitude information for each hit[2]. Magnitude information is obtained for each channel via 7-bit Flash ADC with settable thresholds. The chip uses LVDS1 to communicate with the outside world, so several layers of equipment are needed in order to interface with it. We used the following: A PCB for the chip to t on, and to hold the various capacitors in place. Custom adapter board CAEN V1495 FPGA board with custom bit-stream Agilent E3631A Power Supply1 Low</p> <p>Voltage Dierential Signal</p> <p>2</p> <p> A computer running LabView 2009 A ROOT script to cut and t the calibration data</p> <p>Figure 2: Detail of the FSSR2 board: three chips are present, but only the middle one is tested. At the bottom of the board, the pins for the capacitors can be seen.</p> <p>22.1</p> <p>MeasurementsInitial checks</p> <p>When starting, its important to check the ADC threshold settings: if the thresholds are too low, the FSSR2 picks up ambient noise and calibration is impossible. Threshold settings are considered adequate when the chip produces less than 10 hits per second when in acquisition mode. The capacitance of the test capacitors is measured with a high precision capacitance meter. This turned out to be unnecessary, because the 5% tolerance on the nominal capacitor value turned out to be far inferior than the error on our data. The test capacitors are then inserted into their sockets on the main PCB. At this stage its crucial to check whether the bonds are still connected and functional. Bond failures are quite common due to mechanical stress (e.i. PCB bending) upon capacitor insertion. Failures of course lead to unexpected behavior (and headaches). We noted that if a bond fails at the far end from the chip, it acts as an antenna and picks up ambient noise far more than any other channel, causing 3</p> <p>the chip to saturate, which often results in it ignoring all the hits on other channels.</p> <p>2.2</p> <p>Calibration procedure</p> <p>Calibration of the FSSR2 is obtained by pulsing each channel with a square wave signal with increasing amplitude (see gure 3). This procedure is then repeated up to 10000 times to gain more data. The start and stop amplitude, along with the number of repeats can be set in software. Additionally, the FSSR2s channel kill mask can be used to exclude all the channels not under observation. Once the module is set up, it is enclosed in a metallic container to shield it from EMI. Calibration is set up via a program in LabView which let us control all the FSSR2s registers and send commands to the chip. We repeated 100 and 1000 acquisition per channel, which resulted in a large amount of data, even when we killed the unused channels. We later discovered that due to software limitations, we were collecting data from two additional FSSR2 chips that were bonded on the same PCB. Fortunately we were able to lter out the unused bits after the data acquisition phase.</p> <p>3</p> <p>Data analysis</p> <p>Data analysis is performed using ROOT and two scripts: one cuts out the unused data and puts it into histograms while the second one ts them and outputs a graph of the measurements. The function used to t the data is the following: x p1 1 1 + erf (1) 2 p2 2 where p1 and p2 are the mean and standard deviation of the hit distribution respectively. The standard deviation represents the threshold error, and is expressed in DAC units. The conversion rate between threshold error and ENC is 300 e/th .</p> <p>3.1</p> <p>Encountered problems</p> <p>The rst problem encountered was probably due to a bug in the FPGA bitstream. We noticed a pattern in some inconsistent data (see gure 4) Some calibration amplitudes were getting an inexplicable low count, for every ADC threshold. We deducted it could be a bug and ignored the awed data by setting the error to a value high enough so it could not interfere with the t. Fortunately as long as this happenes outside the transition region, the awed data can be safely ignored and the t converges. Another problem was ambient noise (possibly noise generated by FSSR2 control circuitry or supply): when the calibration pulser was outputting small amplitudes, ambient noise would add onto the signal causing the chip to register a hit. This showed up as a noise oor (seen in gure 5 and 6) in the graphs 4</p> <p>v Vstart</p> <p>v v+1 Ch 1 no</p> <p>impulse(v,Ch)</p> <p>v = Vstop ?</p> <p>yes Ch = 128?</p> <p>no</p> <p>Ch Ch + 1</p> <p>yes</p> <p>END Figure 3: FSSR2 calibration owchart</p> <p>Figure 4: Inconsisted data points are circled in purple.</p> <p>5</p> <p>and made the t diverge. This problem was mitigated by eliminating all data outside the BCO range 128 5.</p> <p>3.2</p> <p>Results</p> <p>Fitting the calculated ENC from all the intermediate ts to a straight line, we can approximate the ENC by capacitance, and nally obtain the FSSR2s intrinsic noise by extrapolating to zero capacitance. The slope of the tted line is 19 8 e /pF and the intercept is (0.29 0.15) 103 e . If we exclude the last point in the t (the one for 33 pF), the tted line has a slope of 28 10 e /pF and the intercept is (0.20 0.16) 103 e .</p> <p>References[1] The INFN SLIM5 website [2] V. Re, M. Manghisoni, L. Ratti, J. Ho, A. Mekkauoi, R. Yarema, FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors</p> <p>6</p> <p>Figure 5: Really noisy data, t is impossible.</p> <p>Figure 6: Less noise, but t is still impossible without modifying the t function. Notice some inconsistant data is still present!</p> <p>Capacitance [pF] 3.9 6.8 10 18 18 27 33</p> <p>ENC [e ] 235 21 223 21 700 42 727 39 806 39 836 42 743 36</p> <p>Table 1: Results</p> <p>7</p> <p>1000</p> <p>Legend y=18.97*x+293.6</p> <p>800</p> <p>ENC [e rms]</p> <p>600</p> <p>400</p> <p>200</p> <p>0 0 5 10 15 20 Capacitance [pF] 25 30 35</p> <p>Figure 7: Final linear t of data</p> <p>8</p>

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